tangxifan
|
ec1ad94d4a
|
[doc] add syntax about internal drivers
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2024-06-25 13:06:47 -07:00 |
|
tangxifan
|
c99178f350
|
[test] fixed a bug on pin locations
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2024-06-25 12:34:52 -07:00 |
|
tangxifan
|
4640e74e7e
|
[core] code format
|
2024-06-25 12:25:16 -07:00 |
|
tangxifan
|
66af73e91e
|
[lib] now accept reset and set in programmable clock network
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2024-06-25 12:24:46 -07:00 |
|
tangxifan
|
fbece49047
|
[core] fixed a bug where unexpected OPINs are added as internal drivers
|
2024-06-25 12:07:19 -07:00 |
|
tangxifan
|
2cbb04b90d
|
[test] add a new testcase to validate programmable clock network with internal drivers
|
2024-06-25 11:58:05 -07:00 |
|
tangxifan
|
7bcbd8a88b
|
[core] code format
|
2024-06-25 11:44:50 -07:00 |
|
tangxifan
|
3b2c13402a
|
[core] syntax
|
2024-06-25 11:44:25 -07:00 |
|
tangxifan
|
31d4b4c402
|
[core] now support add internal drivers to clock tree
|
2024-06-25 11:27:22 -07:00 |
|
tangxifan
|
272d78eb43
|
[test] add a new unit test
|
2024-06-24 19:13:36 -07:00 |
|
tangxifan
|
22bee35fd1
|
[lib] mem allocate
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2024-06-24 18:47:56 -07:00 |
|
tangxifan
|
36ef555dda
|
[lib] add example arch for clock arch with internal drivers
|
2024-06-24 18:33:47 -07:00 |
|
tangxifan
|
2eda2825b7
|
[lib] syntax
|
2024-06-24 18:28:42 -07:00 |
|
tangxifan
|
0c442f6238
|
[lib] add syntax to support internal drivers in clock network parsers
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2024-06-24 17:54:58 -07:00 |
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tangxifan
|
582efc0501
|
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_clkntwk2
|
2024-06-24 10:42:29 -07:00 |
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tangxifan
|
8f770a6e3c
|
Merge pull request #1725 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-06-24 10:37:07 -07:00 |
github-actions[bot]
|
a436afcc4f
|
Updated Patch Count
|
2024-06-24 17:21:57 +00:00 |
|
tangxifan
|
cd680fd21d
|
Merge pull request #1724 from lnis-uofu/dependabot/submodules/vtr-verilog-to-routing-6a4f0ca
Bump vtr-verilog-to-routing from `2ff460a` to `6a4f0ca`
|
2024-06-24 10:21:36 -07:00 |
dependabot[bot]
|
9bdcc27913
|
Bump vtr-verilog-to-routing from `2ff460a` to `6a4f0ca`
Bumps [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing) from `2ff460a` to `6a4f0ca`.
- [Release notes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/releases)
- [Commits](2ff460a245...6a4f0cac3b)
---
updated-dependencies:
- dependency-name: vtr-verilog-to-routing
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-06-24 06:55:52 +00:00 |
|
tangxifan
|
253e3e0cba
|
[doc] add new syntax for clock network
|
2024-06-23 17:43:38 -07:00 |
|
tangxifan
|
9bb076d892
|
[test] fixed a bug on pin mapping of tetbenche
|
2024-06-21 20:29:21 -07:00 |
|
tangxifan
|
d2053db21c
|
[core] removing the restrictions on only 1 clock tree is supported in programmable clock network
|
2024-06-21 19:00:01 -07:00 |
|
tangxifan
|
292f4a9273
|
[test] fixed a bug where ace is no required
|
2024-06-21 18:43:25 -07:00 |
|
tangxifan
|
2193f108ee
|
[core] add debugging messages
|
2024-06-21 18:42:35 -07:00 |
|
tangxifan
|
c2e759fa70
|
[arch] fixed some bugs
|
2024-06-21 18:42:29 -07:00 |
|
tangxifan
|
7d67b9d5b9
|
[test] deploy new tests to basic reg tests
|
2024-06-21 18:14:54 -07:00 |
|
tangxifan
|
8d7dba2d57
|
[test] add a new testcase to programmable clock network on supporting reset signals
|
2024-06-21 18:13:37 -07:00 |
|
tangxifan
|
3f08b83b3a
|
[core] remove restrictions on 1 clock tree definition
|
2024-06-21 17:12:10 -07:00 |
|
tangxifan
|
ecd31955b1
|
[core] code format
|
2024-06-21 17:11:32 -07:00 |
|
tangxifan
|
3ddaefc2a2
|
[lib] syntax
|
2024-06-21 17:02:37 -07:00 |
|
tangxifan
|
6c5988575c
|
[test] update clock network testcase
|
2024-06-21 16:59:21 -07:00 |
|
tangxifan
|
486cd01c15
|
[core] now clock graph builder supports two types of switches
|
2024-06-21 16:54:22 -07:00 |
|
tangxifan
|
1ab75cf76c
|
[lib] now link clock arch supports tap and driver default switches
|
2024-06-21 16:52:22 -07:00 |
|
tangxifan
|
9ccd14bf4d
|
[lib] now default switch of clk ntwk is split to default_tap_switch and default_driver_switch
|
2024-06-21 16:45:05 -07:00 |
|
tangxifan
|
4fea194bac
|
Merge pull request #1722 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-06-20 10:27:18 -07:00 |
|
github-actions[bot]
|
1edbdf9f22
|
Updated Patch Count
|
2024-06-20 17:26:30 +00:00 |
|
tangxifan
|
3dab0f19c8
|
Merge pull request #1720 from lnis-uofu/dependabot/submodules/yosys-6c8ae44
Bump yosys from `74a1dd9` to `6c8ae44`
|
2024-06-20 10:26:09 -07:00 |
|
tangxifan
|
edd2aa9fb5
|
Merge pull request #1717 from lnis-uofu/dependabot/submodules/vtr-verilog-to-routing-2ff460a
Bump vtr-verilog-to-routing from `e099206` to `2ff460a`
|
2024-06-20 10:25:58 -07:00 |
|
dependabot[bot]
|
2d6c9c3428
|
Bump yosys from `74a1dd9` to `6c8ae44`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `74a1dd9` to `6c8ae44`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](74a1dd99ac...6c8ae44ae7)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-06-20 06:48:40 +00:00 |
|
dependabot[bot]
|
6ae96d9717
|
Bump vtr-verilog-to-routing from `e099206` to `2ff460a`
Bumps [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing) from `e099206` to `2ff460a`.
- [Release notes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/releases)
- [Commits](e099206db3...2ff460a245)
---
updated-dependencies:
- dependency-name: vtr-verilog-to-routing
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-06-19 06:23:30 +00:00 |
|
tangxifan
|
077c6ef1b0
|
Merge pull request #1716 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-06-18 10:17:56 -07:00 |
|
github-actions[bot]
|
ae3296ca8d
|
Updated Patch Count
|
2024-06-18 17:02:13 +00:00 |
|
tangxifan
|
8d4b1bd0be
|
Merge pull request #1715 from lnis-uofu/dependabot/submodules/vtr-verilog-to-routing-e099206
Bump vtr-verilog-to-routing from `6e8ac62` to `e099206`
|
2024-06-18 10:01:50 -07:00 |
|
dependabot[bot]
|
920b43feaf
|
Bump vtr-verilog-to-routing from `6e8ac62` to `e099206`
Bumps [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing) from `6e8ac62` to `e099206`.
- [Release notes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/releases)
- [Commits](6e8ac62b77...e099206db3)
---
updated-dependencies:
- dependency-name: vtr-verilog-to-routing
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-06-18 06:23:44 +00:00 |
|
tangxifan
|
0cd48bd427
|
Merge pull request #1714 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-06-17 09:42:24 -07:00 |
|
github-actions[bot]
|
0ee61a895b
|
Updated Patch Count
|
2024-06-17 16:41:06 +00:00 |
|
tangxifan
|
1422495783
|
Merge pull request #1713 from lnis-uofu/dependabot/submodules/yosys-74a1dd9
Bump yosys from `2fd2b65` to `74a1dd9`
|
2024-06-17 09:40:47 -07:00 |
|
dependabot[bot]
|
69fe78d2f9
|
Bump yosys from `2fd2b65` to `74a1dd9`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `2fd2b65` to `74a1dd9`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](2fd2b6538d...74a1dd99ac)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-06-17 06:09:27 +00:00 |
|
tangxifan
|
66baf7e605
|
Merge pull request #1712 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-06-14 10:13:32 -07:00 |
|
github-actions[bot]
|
e44facba04
|
Updated Patch Count
|
2024-06-14 16:50:19 +00:00 |