tangxifan
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1d3c9ff192
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[Script] Adapt python scripts to support include directory
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2022-02-01 13:55:25 -08:00 |
Aram Kostanyan
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588ee14920
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Merge branch 'master' into issue-483
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2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
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fb2e4377c8
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Added missing changes from previous commit.
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2022-01-17 19:42:40 +05:00 |
|
Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
Awais Abbas
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fc52a4696c
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Yosys only support added in OpenFPGA
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2022-01-06 14:44:11 +05:00 |
|
Aram Kostanyan
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a355977420
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Adding Yosys+Verific support.
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2021-10-29 18:34:27 +05:00 |
Christophe Alexandre
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c42acec81e
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Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py
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2021-10-18 10:45:35 +00:00 |
|
Christophe Alexandre
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c3dd704bf3
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Fixing typo in run_fpga_flow.py
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2021-10-18 09:13:42 +00:00 |
|
Christophe Alexandre
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d411967159
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Fixing small typo in run_fpga_flow.py
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2021-10-15 10:01:12 +00:00 |
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tangxifan
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7119075253
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[Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated
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2021-06-29 15:52:42 -06:00 |
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tangxifan
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e1f8b252b1
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Merge branch 'master' into yosys_heterogeneous_block_support
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2021-03-16 20:05:21 -06:00 |
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tangxifan
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090f483a11
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[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
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2021-03-16 16:45:57 -06:00 |
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tangxifan
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b42541d84e
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[Flow] Support multiple iterations in rewriting yosys scripts
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2021-03-10 14:10:35 -07:00 |
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tangxifan
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aafd87c3f9
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[Flow] Update flow-run to support custom yosys rewrite scripts
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2021-03-10 11:36:29 -07:00 |
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tangxifan
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131643dcc0
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[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
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2021-03-08 21:08:55 -07:00 |
ganeshgore
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b860722893
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Fixed parameter ys_rewrite_params name bug
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2021-03-08 10:34:39 -07:00 |
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ganeshgore
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52de55e7eb
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Merge branch 'master' into ganesh_dev
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2021-03-08 10:15:06 -07:00 |
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Ganesh Gore
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7a35811430
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[Flow] Yosys rewrite support
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2021-03-08 00:35:47 -07:00 |
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Ganesh Gore
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67cd9a69b7
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[Flow] Extended yosys variable subtitution
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2021-03-08 00:21:07 -07:00 |
Lalit Sharma
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6a1ce01084
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Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
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2021-03-07 22:02:11 -08:00 |
|
Lalit Sharma
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0cbad747a1
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Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
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2021-03-04 01:10:47 -08:00 |
|
Lalit Sharma
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817729ac86
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Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
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2021-03-01 22:31:15 -08:00 |
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tangxifan
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a819375f69
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[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
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2021-02-16 16:53:13 -07:00 |
Tarachand Pagarani
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3a587f663a
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copy yosys output file in case power analysis setting is off
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2021-02-15 02:36:02 -08:00 |
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Ganesh Gore
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6cdc31f073
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[Flow] ACE is optional duign flow script
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2021-02-03 19:07:48 -07:00 |
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Ganesh Gore
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df4a397470
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[Cleanup] Removed deadcode
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2021-02-03 10:35:14 -07:00 |
|
ganeshgore
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289d9d2169
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[Bugfix] Honors yosys_tmpl parameter in flow script
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2020-12-03 12:24:24 -07:00 |
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ganeshgore
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59bd7d0f18
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[Flow] Changed substitute to safe_sustitute option
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2020-11-25 22:09:36 -07:00 |
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ganeshgore
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fefba0db59
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Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
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2020-11-25 17:29:53 -07:00 |
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ganeshgore
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1554f583b7
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[Flow] Now support explicit variable file for task
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2020-11-25 17:22:41 -07:00 |
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tangxifan
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521accdc88
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Merge pull request #104 from lukefahr/disp_fix
FLOW: fixed display flag
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2020-10-07 09:54:06 -06:00 |
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tangxifan
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7b12c28e4f
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Merge pull request #102 from lukefahr/blif_bug
Fixed blif formatting bug
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2020-10-06 20:05:02 -06:00 |
Andrew Lukefahr
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33bbe0ec48
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FLOW: fixed display flag
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2020-10-06 20:52:28 -04:00 |
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Andrew Lukefahr
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d68427e47b
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Fixed blif formatting bug
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2020-10-06 20:46:50 -04:00 |
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Andrew Lukefahr
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2d92a1f1af
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Edits to enable basic run_fpga_flow.py
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2020-10-02 10:18:10 -04:00 |
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ganeshgore
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747c062f86
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BugFix : Flow script accepts extra OpenFPGA arguments
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2020-07-27 18:10:43 -06:00 |
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ganeshgore
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3b6cd885f3
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BugFix: Fixed yosys_vpr with openFPGA_Shell
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2020-07-22 11:57:04 -06:00 |
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ganeshgore
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41585436c8
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Added external_fabric_key_file key
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2020-06-12 15:37:12 -06:00 |
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ganeshgore
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c1b73efa62
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Added support for simulation setting file in the task flow
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2020-06-10 23:12:30 -06:00 |
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ganeshgore
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689c4a3e19
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BugFix: The filename in the previous commit
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2020-04-15 12:44:22 -06:00 |
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ganeshgore
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7f37bf1441
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Added formal verification support to fpga_flow script
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2020-04-15 12:24:51 -06:00 |
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ganeshgore
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f6b3c5854a
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Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
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2020-04-11 16:45:22 -06:00 |
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ganeshgore
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8ea272dc2c
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Patched the OpenFPGA shell execution bug
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2020-04-08 21:28:14 -06:00 |
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ganeshgore
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583a4d8767
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Fixed bug in openfpga_flow script
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2020-04-08 12:04:08 -06:00 |
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ganeshgore
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ea4122a8a4
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Updated openfpga_flow and task file to support sheel run
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2020-04-06 00:34:36 -06:00 |
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ganeshgore
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d1d3446568
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backedup partial upgrade for fpga_flow script
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2020-04-05 11:36:24 -06:00 |
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ganeshgore
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46bb5ef9d0
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Added disp option in openfpga_flow, Default is --nodisp
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2020-01-23 10:04:38 -07:00 |
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ganeshgore
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f0bed1244c
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Added blif file folding before VPR run
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2020-01-09 16:50:34 -07:00 |
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ganeshgore
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74b650e9e1
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Added fpga_x2p_duplicate_grid_pin option
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2019-12-30 12:25:28 -07:00 |
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ganeshgore
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d1e260f54f
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Spice related option added
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2019-12-30 12:16:04 -07:00 |