tangxifan
|
f89b7a82cf
|
[arch] fixed a bug where the array size mismatch the layout name
|
2023-05-03 22:23:20 +08:00 |
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tangxifan
|
a3f2ae3c33
|
[arch] format
|
2023-05-03 15:23:47 +08:00 |
|
tangxifan
|
68f2d9fe5e
|
[arch] add new example arch using subtile in I/O blocks; Updated documentation
|
2023-05-03 15:16:39 +08:00 |
|
tangxifan
|
02b02d18a5
|
[test] fixed a bug in clock arch
|
2023-04-20 11:35:36 +08:00 |
|
tangxifan
|
b242fd97d6
|
[test] adding new arch and testcase for 2-clock network
|
2023-04-20 11:31:49 +08:00 |
|
tangxifan
|
571a012724
|
[test] xml format
|
2023-03-07 18:47:55 -08:00 |
|
tangxifan
|
7e3b656c51
|
[test] fixed a bug in arch
|
2023-03-06 23:06:32 -08:00 |
|
tangxifan
|
b9f7c72a96
|
[test] fixed some bugs in arch
|
2023-03-02 18:16:59 -08:00 |
|
tangxifan
|
5917446fbe
|
[arch] code format
|
2023-02-28 22:01:49 -08:00 |
|
tangxifan
|
780dec6b1b
|
[test] add a new test to validate the programmable clock arch
|
2023-02-28 21:46:57 -08:00 |
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tangxifan
|
d1e951e52e
|
[test] debugging
|
2023-01-24 17:57:34 -08:00 |
|
tangxifan
|
1d8c1a6803
|
[arch] adding a new arch to validate fracturable dsp
|
2023-01-24 15:17:50 -08:00 |
|
tangxifan
|
acc905fa11
|
[arch] add support to route reset to LUTs
|
2023-01-18 18:22:37 -08:00 |
|
tangxifan
|
c9e00b7abc
|
[arch] add a new example arch that supports local reset
|
2023-01-18 18:05:52 -08:00 |
|
tangxifan
|
297092f1fe
|
[arch] now use a local clock as an input of a CLB
|
2023-01-14 22:12:00 -08:00 |
|
tangxifan
|
9222d085cd
|
[test] now use local clock as one of the pins in a clock bus, but connected to global routing
|
2023-01-13 22:04:56 -08:00 |
|
tangxifan
|
9e462d96e0
|
[arch] now use a dedicated input for locally generated clock signals
|
2023-01-13 20:46:04 -08:00 |
|
tangxifan
|
1fb39f803b
|
[doc] updated vpr arch naming rules
|
2023-01-13 19:52:58 -08:00 |
|
tangxifan
|
a06ee30ca0
|
[arch] added a new vpr arch where clock can be generated by internal logics
|
2023-01-13 19:35:00 -08:00 |
|
tangxifan
|
32f48f16c7
|
[arch] fixed a few bugs
|
2022-10-13 11:54:58 -07:00 |
|
tangxifan
|
7f67794787
|
[arch]add new arch to test
|
2022-10-13 10:54:40 -07:00 |
|
tangxifan
|
85089cbc88
|
[arch] apply xml format for all the architecture files
|
2022-10-07 10:31:51 -07:00 |
|
tangxifan
|
ab53f88c2b
|
[test] now use a fixed device layout for the single-mode LUT design testcase
|
2022-10-04 10:05:22 -07:00 |
|
tangxifan
|
0565ca7aca
|
[script] add missing files
|
2022-09-29 16:14:38 -07:00 |
|
tangxifan
|
2ed4a60f36
|
[arch] reduce clb inputs to force net remapping during routing
|
2022-09-29 15:52:30 -07:00 |
|
tangxifan
|
ce0fbe1765
|
[test] fixed a few bugs
|
2022-09-29 15:32:31 -07:00 |
|
tangxifan
|
f7a02422b5
|
[arch] add a new arch to reproduce the wire-lut bug in repacker
|
2022-09-29 13:59:08 -07:00 |
|
tangxifan
|
40edf859e3
|
Merge branch 'vtr_upgrade' of github.com:lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-20 22:38:06 -07:00 |
|
tangxifan
|
97f0445787
|
[arch] upgrade arch file which was designed for v1.1
|
2022-09-20 22:37:35 -07:00 |
|
tangxifan
|
36603f9772
|
Merge branch 'master' into vtr_upgrade
|
2022-09-20 21:08:06 -07:00 |
|
tangxifan
|
a137f7148c
|
[arch] fixed a bug
|
2022-09-20 15:47:15 -07:00 |
|
tangxifan
|
3f8106f12e
|
[arch] fixed a bug in the custom I/O location assignment: no more I/Os on the corner of centre fabric
|
2022-09-20 15:19:32 -07:00 |
|
tangxifan
|
b3449a338f
|
[arch] update out-of-date vpr arch from v1.1 to v1.2
|
2022-09-20 09:51:43 -07:00 |
|
tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-16 16:47:21 -07:00 |
|
tangxifan
|
f2e13e5ea9
|
[arch] add more flexible layout to test I/O center features
|
2022-09-16 10:00:08 -07:00 |
|
tangxifan
|
ec38b3990f
|
[arch] update to check OpenFPGA I/O indexing
|
2022-09-14 13:58:12 -07:00 |
|
tangxifan
|
83c89ae1bf
|
[arch] add more corner case to test the custom I/O location feature
|
2022-09-13 23:05:41 -07:00 |
|
tangxifan
|
a37e270f25
|
[arch] now custom I/O loc test case cover I/Os in the center of the fabric
|
2022-09-13 16:57:18 -07:00 |
|
tangxifan
|
cc974a80f7
|
[arch] added a new architecture to test the local routing architecture where reset is on LUT
|
2022-09-09 16:48:10 -07:00 |
|
tangxifan
|
95d7a17b3c
|
Merge branch 'master' into vtr_upgrade
|
2022-09-09 14:32:42 -07:00 |
|
tangxifan
|
419a3a1e46
|
[arch] fixed a bug
|
2022-09-08 16:53:52 -07:00 |
|
tangxifan
|
122a323668
|
[arch] fixed bugs
|
2022-09-08 16:50:33 -07:00 |
|
tangxifan
|
218e6d0a47
|
[arch] fixed syntax errors
|
2022-09-08 16:31:52 -07:00 |
|
tangxifan
|
b1fad0b4e5
|
[arch] add an example architecture to show the use extended syntax
|
2022-09-08 16:19:21 -07:00 |
|
tangxifan
|
9e1abf5898
|
Merge branch 'master' into vtr_upgrade
|
2022-09-01 21:39:14 -07:00 |
|
tangxifan
|
c48f750f86
|
[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
|
2022-09-01 20:10:29 -07:00 |
|
tangxifan
|
dbacee8a0a
|
[script] turn off equivalent for soft adder architecture as we do not expect any routing optimization
|
2022-08-27 20:25:50 -07:00 |
|
tangxifan
|
bdb051f787
|
[arch] update arch files
|
2022-08-22 18:24:37 -07:00 |
|
tangxifan
|
2bbf2f02c9
|
[script] now return status on each arch upgrade task
|
2022-08-22 18:23:00 -07:00 |
|
tangxifan
|
b6e1175517
|
[script] update doc and avoid modify README.MD when updating arch files
|
2022-08-22 18:19:23 -07:00 |