Ganesh Gore
|
a880802803
|
Bug Fix: Corrected read VPR stat filename
|
2019-11-01 20:51:05 -06:00 |
tangxifan
|
a9c02cd2a5
|
fix errors in travis
|
2019-11-01 20:32:40 -06:00 |
|
tangxifan
|
550df19ee2
|
use a stable cmake now
|
2019-11-01 20:26:29 -06:00 |
|
tangxifan
|
3669a47d3b
|
reworked the ini writer
|
2019-11-01 20:25:01 -06:00 |
|
tangxifan
|
dab66b8be7
|
start adding auto check cpp files
|
2019-11-01 19:49:50 -06:00 |
|
tangxifan
|
e2b042c61c
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-11-01 18:27:27 -06:00 |
|
Ganesh Gore
|
370a5ed408
|
Bug Fix: shifter ff.v include path to tcl script
|
2019-11-01 18:22:40 -06:00 |
|
Ganesh Gore
|
595d2d3070
|
Simple argument shuffle
|
2019-11-01 18:21:26 -06:00 |
|
Ganesh Gore
|
27005d6640
|
Added Modelsim Python Script
|
2019-11-01 18:20:40 -06:00 |
|
Ganesh Gore
|
a0512e40b1
|
Created intermidiate file for modelsim simulation
|
2019-11-01 18:20:00 -06:00 |
|
tangxifan
|
4d4ef1113d
|
give up iverilog on travis
|
2019-11-01 17:53:50 -06:00 |
|
tangxifan
|
1d78725d4d
|
add installation
|
2019-11-01 17:48:17 -06:00 |
|
tangxifan
|
9a37b66d53
|
move installation to a script
|
2019-11-01 17:39:30 -06:00 |
|
tangxifan
|
161664f253
|
try to comfort iverilog package extraction
|
2019-11-01 17:24:06 -06:00 |
|
tangxifan
|
2dc3a4eb1f
|
fixing bugs in iVerilog installation
|
2019-11-01 17:03:21 -06:00 |
|
tangxifan
|
5332588e82
|
retrying travis installation of iVerilog 10.3
|
2019-11-01 16:36:29 -06:00 |
|
tangxifan
|
3ae841b80f
|
start refactoring auto-check top testbench generation
|
2019-11-01 16:33:12 -06:00 |
|
tangxifan
|
b61b81b8d8
|
tuning iverilog version display
|
2019-11-01 15:29:08 -06:00 |
|
tangxifan
|
d4fedb76d7
|
revert to default iverilog of Ubuntu 18.04
|
2019-11-01 15:24:58 -06:00 |
|
tangxifan
|
b54bec1609
|
streamline regression tes
|
2019-11-01 15:23:38 -06:00 |
|
tangxifan
|
000f93ffd7
|
try to fix travis bugs
|
2019-11-01 15:19:34 -06:00 |
|
tangxifan
|
480478e545
|
reorganizing travis
|
2019-11-01 15:12:08 -06:00 |
|
tangxifan
|
8c0d60abd6
|
debugging travis
|
2019-11-01 15:00:33 -06:00 |
|
tangxifan
|
c2cef205a4
|
update travis: try to compile iverilog through source
|
2019-11-01 14:52:42 -06:00 |
|
tangxifan
|
b53a9b13bf
|
update travis with installation
|
2019-11-01 14:03:55 -06:00 |
|
tangxifan
|
32953b0292
|
rework on Travis Scripts
|
2019-11-01 13:41:30 -06:00 |
|
tangxifan
|
de0be72634
|
try to make travis install latest iVerilog
|
2019-11-01 13:25:29 -06:00 |
|
tangxifan
|
a49010d2d3
|
reorganize the Travis regression test, temporarily shadow s298
|
2019-11-01 11:09:35 -06:00 |
|
tangxifan
|
49bfb3223c
|
add compact routing to regression test
|
2019-11-01 10:53:47 -06:00 |
|
tangxifan
|
139ea8b3e3
|
add s298 single mode arch to Travis
|
2019-11-01 10:49:37 -06:00 |
|
tangxifan
|
531cc064fc
|
bug fixing for formal top-level testbench
|
2019-11-01 10:47:40 -06:00 |
|
Ganesh Gore
|
da0778e813
|
Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev
|
2019-11-01 00:46:34 -06:00 |
|
tangxifan
|
d709868463
|
adding more regression tests which is quick run but very helpful for debugging
|
2019-10-31 20:17:40 -06:00 |
|
tangxifan
|
2dff779005
|
critical bug fixed for bitstream generation for offset truth tables
|
2019-10-31 20:16:08 -06:00 |
|
tangxifan
|
a6a3e7c36b
|
adding mcnc_big20 to regression test
|
2019-10-31 19:31:27 -06:00 |
|
Ganesh Gore
|
81180939ca
|
Bug fix: Missing exit_if_fail flag in fpga_flow script
|
2019-10-31 09:56:57 -06:00 |
|
tangxifan
|
de78718724
|
remove unused gcc setting in travis
|
2019-10-30 20:07:32 -06:00 |
|
tangxifan
|
7eac8be475
|
try to upgrade travis OS linux for the latest iverilog
|
2019-10-30 20:04:20 -06:00 |
|
tangxifan
|
858c1aefce
|
try use force for Icarus
|
2019-10-30 19:50:34 -06:00 |
|
tangxifan
|
5531422186
|
update regression test with no-explicit port mapping cases
|
2019-10-30 19:37:06 -06:00 |
|
tangxifan
|
7460dc8cab
|
pass current regression tests
|
2019-10-30 19:10:36 -06:00 |
|
tangxifan
|
55fbd72293
|
many bugs have been fixed
|
2019-10-30 15:50:42 -06:00 |
|
tangxifan
|
4398cffaaa
|
single mode is working, multi-mode is under debugging
|
2019-10-29 22:32:36 -06:00 |
|
tangxifan
|
1faacfa3cf
|
keep autocheck testbenches underwater now, bring them back when refactored. Start plugging in the new engine
|
2019-10-29 14:23:09 -06:00 |
|
tangxifan
|
7c116aac2f
|
added Verilog generation for preconfig top module
|
2019-10-29 13:54:35 -06:00 |
|
tangxifan
|
10491c4291
|
bring single mode test case online with bug fixing
|
2019-10-28 17:04:10 -06:00 |
|
tangxifan
|
5cb3717433
|
add single mode test case to regression test. debugging now
|
2019-10-28 15:57:17 -06:00 |
|
tangxifan
|
fe005f1f56
|
remove legacy codes for Verilog formal verification testbench generation
|
2019-10-28 15:21:14 -06:00 |
|
tangxifan
|
c047fd3cb2
|
plugged in the refactored formal verification Verilog testbench using random vectors
|
2019-10-28 15:10:29 -06:00 |
|
tangxifan
|
ccabe4ce2a
|
refactoring Verilog formal verification top testbench using random vectors
|
2019-10-28 14:45:51 -06:00 |