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5025 Commits

Author SHA1 Message Date
github-actions[bot] 32319f7efc Updated Patch Count 2022-02-02 00:21:57 +00:00
tangxifan 9b3560baca
Merge pull request #511 from lnis-uofu/verilog_rel_path 
Now Verilog Testbench Generator has a new option ``--use_relative_path``
 2022-02-01 15:20:54 -08:00
tangxifan 1d3c9ff192 [Script] Adapt python scripts to support include directory 2022-02-01 13:55:25 -08:00
tangxifan 27ac2fafe5 [Test] Add the new test case to regression tests 2022-02-01 13:45:46 -08:00
tangxifan 532af96243 [Test] Add a new testcase to validate ``--use_relative_path`` in preconfigured testbench 2022-02-01 13:44:47 -08:00
tangxifan 35c7968c98 [Script] Add a new example openfpga shell script 2022-02-01 13:40:22 -08:00
tangxifan 2b5fded2a9 [Doc] Update documentation on the new option 2022-02-01 13:25:58 -08:00
tangxifan 1c94d0f285 [FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path`` 2022-02-01 13:25:09 -08:00
tangxifan b7b0a2a5d8 [Doc] Update doc about the new option 2022-02-01 12:19:26 -08:00
tangxifan f311a034bb [FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path`` 2022-02-01 12:17:02 -08:00
tangxifan d8c1492a91
Merge pull request #510 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-01-31 16:26:49 -08:00
github-actions[bot] 87a4b0263c Updated Patch Count 2022-02-01 00:23:15 +00:00
tangxifan 6f6dc4bd41
Merge pull request #509 from lnis-uofu/verilog_rel_path 
[FPGA-Verilog] Now have a new option ``--use_relative_path``
 2022-01-31 15:15:55 -08:00
tangxifan 09ef516de8 [Script] Tune OpenFPGA shell script to enable testing on relative paths 2022-01-31 14:23:13 -08:00
tangxifan 2b8e2de0c9 [FPGA-Verilog] Fix bugs 2022-01-31 14:23:04 -08:00
tangxifan 6c29c286bc [FPGA-Verilog] Fix a bug which cause errors 2022-01-31 14:06:58 -08:00
tangxifan 9871fe88fb [Test] Typo fix 2022-01-31 13:03:45 -08:00
tangxifan da8fc0f5d4 [Test] Add a new test case to validate ``--use_relative_path`` 2022-01-31 13:02:19 -08:00
tangxifan 63f44adf15 [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
tangxifan f72bf4ba1c
Merge pull request #507 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-01-28 16:46:17 -08:00
github-actions[bot] 74f76d3858 Updated Patch Count 2022-01-29 00:18:22 +00:00
tangxifan 6fe2a84a89
Merge pull request #506 from lnis-uofu/dependabot/submodules/yosys-plugins-003c697 
Bump yosys-plugins from `eaecd87` to `003c697`
 2022-01-28 09:22:07 -08:00
dependabot[bot] 16a8d7630e
Bump yosys-plugins from `eaecd87` to `003c697` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `eaecd87` to `003c697`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](eaecd87583...003c697169)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-01-28 07:21:06 +00:00
tangxifan 68d3628bac
Merge pull request #505 from emincetin452/tb-fix 
changing condition of bitstream downloading
 2022-01-27 23:03:58 -08:00
Emin Cetin 6c2c4e8b14 adding comment 2022-01-28 08:57:45 +03:00
Emin Cetin f9b47c3b34 missing semicolon 2022-01-27 16:49:04 +03:00
Emin Cetin 8f7ee4e338 changing condition of bitstream downloading 2022-01-27 11:49:55 +03:00
tangxifan 7ed92b732f
Merge pull request #503 from lnis-uofu/gsb2xml 
New option ``--unique`` available in command ``write_gsb_to_xml``
 2022-01-26 19:22:25 -08:00
tangxifan b5989a85a4
Merge branch 'master' into gsb2xml 2022-01-26 16:46:41 -08:00
tangxifan 699793ddcd
Merge pull request #504 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-01-26 16:46:20 -08:00
github-actions[bot] 380049a7ac Updated Patch Count 2022-01-27 00:19:58 +00:00
tangxifan c2390886d4
Merge branch 'master' into gsb2xml 2022-01-26 11:58:01 -08:00
tangxifan ee4ab919a5
Merge pull request #500 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-01-26 11:57:50 -08:00
tangxifan e59ea91ad6 [Script] Fixed a bug which causes errors 2022-01-26 11:49:32 -08:00
tangxifan f8ef3df560 [Test] Now use 4x4 fabric in testing write_rr_gsb commands 2022-01-26 11:41:48 -08:00
tangxifan a9042318cf [Test] Deploy the test case to regression tests 2022-01-26 11:26:17 -08:00
tangxifan 3b7588cd48 [Test] Rename test case to be consistent with the name of options 2022-01-26 11:25:54 -08:00
tangxifan 6b26ed0819 [Test] Add test cases on writing gsb files 2022-01-26 11:22:39 -08:00
tangxifan 5db049522d [Script] Add an example script about write GSB 2022-01-26 11:22:23 -08:00
tangxifan a9a56686e2 [Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml`` 2022-01-26 11:10:29 -08:00
tangxifan 04e280b050
Merge pull request #502 from lnis-uofu/dependabot/submodules/yosys-plugins-eaecd87 
Bump yosys-plugins from `7fa69f8` to `eaecd87`
 2022-01-26 09:49:42 -08:00
dependabot[bot] 789685901b
Bump yosys-plugins from `7fa69f8` to `eaecd87` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `7fa69f8` to `eaecd87`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](7fa69f80c9...eaecd87583)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-01-26 07:23:31 +00:00
tangxifan d3eb304b22
Merge pull request #501 from lnis-uofu/time_stamp 
Patch the errors in basic regression tests due to ``--no_time_stamp`` support
 2022-01-25 22:17:08 -08:00
tangxifan 11e045992d [Test] Now only compare on the golden netlist changes to branch 2022-01-25 21:24:10 -08:00
tangxifan 23795d6474 [Test] Update golden netlists 2022-01-25 20:37:08 -08:00
tangxifan a9e6b7c12e [FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled 2022-01-25 20:33:49 -08:00
tangxifan c2c827ee10 [Script] Fix a bug in git-diff for regression tests 2022-01-25 20:27:41 -08:00
tangxifan 4a89d17505
Merge pull request #499 from lnis-uofu/time_stamp 
FPGA-Verilog/FPGA-Bitstream/FPGA-SDC commands have a new option ``--no_time_stamp``
 2022-01-25 17:36:40 -08:00
tangxifan fedb1bd2e3 [Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp 2022-01-25 16:41:36 -08:00
tangxifan 5c0f63ddd9 [Test] Update regression tests for the new test about ``--no_time_stamp`` 2022-01-25 16:30:48 -08:00