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Merge pull request #499 from lnis-uofu/time_stamp 

FPGA-Verilog/FPGA-Bitstream/FPGA-SDC commands have a new option ``--no_time_stamp``
This commit is contained in:
tangxifan 2022-01-25 17:36:40 -08:00 committed by GitHub
parent dd1365919f fedb1bd2e3
commit 4a89d17505
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GPG Key ID: 4AEE18F83AFDEB23
137 changed files with 19093 additions and 330 deletions
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16
docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst
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@ -41,6 +41,10 @@ build_architecture_bitstream
.. option:: --write_file <string>
Output the fabric-independent bitstream to an XML file. See details at :ref:`file_formats_architecture_bitstream`.
.. option:: --no_time_stamp
Do not print time stamp in bitstream files
.. option:: --verbose
@ -81,6 +85,10 @@ write_fabric_bitstream
Keep don't care bits (``x``) in the outputted bitstream file. This is only applicable to plain text file format. If not enabled, the don't care bits are converted to either logic ``0`` or ``1``.
.. option:: --no_time_stamp
Do not print time stamp in bitstream files
.. option:: --verbose
Show verbose log
@ -95,6 +103,10 @@ write_io_mapping
Specify the file name where the I/O mapping will be outputted to.
See file formats in :ref:`file_format_io_mapping_file`.
.. option:: --no_time_stamp
Do not print time stamp in bitstream files
.. option:: --verbose
Show verbose log
@ -113,6 +125,10 @@ report_bitstream_distribution
Specify the maximum depth of the block which should appear in the block
.. option:: --no_time_stamp
Do not print time stamp in bitstream files
.. option:: --verbose
Show verbose log

15
docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
View File

@ -28,6 +28,10 @@ write_fabric_verilog
Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists
.. option:: --no_time_stamp
Do not print time stamp in Verilog netlists
.. option:: --verbose
Show verbose log
@ -82,6 +86,9 @@ write_full_testbench
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
.. option:: --no_time_stamp
Do not print time stamp in Verilog netlists
.. option:: --verbose
@ -133,6 +140,10 @@ __ iverilog_website_
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
.. option:: --no_time_stamp
Do not print time stamp in Verilog netlists
.. option:: --verbose
Show verbose log
@ -169,6 +180,10 @@ write_preconfigured_testbench
Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
.. option:: --no_time_stamp
Do not print time stamp in Verilog netlists
.. option:: --verbose
Show verbose log

17
libopenfpga/libfpgabitstream/src/report_arch_bitstream_distribution.cpp
View File

@ -27,16 +27,20 @@ namespace openfpga {
* This function write header information for an XML file of bitstream distribution
*******************************************************************/
static
void report_architecture_bitstream_distribution_xml_file_head(std::fstream& fp) {
void report_architecture_bitstream_distribution_xml_file_head(std::fstream& fp,
const bool& include_time_stamp) {
valid_file_stream(fp);
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "<!-- " << std::endl;
fp << "\t- Report Architecture Bitstream Distribution" << std::endl;
fp << "\t- Version: " << openfpga::VERSION << std::endl;
fp << "\t- Date: " << std::ctime(&end_time) ;
if (include_time_stamp) {
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "\t- Date: " << std::ctime(&end_time) ;
}
fp << "--> " << std::endl;
fp << std::endl;
}
@ -88,6 +92,7 @@ void rec_report_block_bitstream_distribution_to_xml_file(std::fstream& fp,
*******************************************************************/
int report_architecture_bitstream_distribution(const BitstreamManager& bitstream_manager,
const std::string& fname,
const bool& include_time_stamp,
const size_t& max_hierarchy_level) {
/* Ensure that we have a valid file name */
if (true == fname.empty()) {
@ -105,7 +110,7 @@ int report_architecture_bitstream_distribution(const BitstreamManager& bitstream
check_file_stream(fname.c_str(), fp);
/* Put down a brief introduction */
report_architecture_bitstream_distribution_xml_file_head(fp);
report_architecture_bitstream_distribution_xml_file_head(fp, include_time_stamp);
/* Find the top block, which has not parents */
std::vector<ConfigBlockId> top_block = find_bitstream_manager_top_blocks(bitstream_manager);

1
libopenfpga/libfpgabitstream/src/report_arch_bitstream_distribution.h
View File

@ -16,6 +16,7 @@ namespace openfpga {
int report_architecture_bitstream_distribution(const BitstreamManager& bitstream_manager,
const std::string& fname,
const bool& include_time_stamp,
const size_t& max_hierarchy_level = 1);
} /* end namespace openfpga */

19
libopenfpga/libfpgabitstream/src/write_xml_arch_bitstream.cpp
View File

@ -27,17 +27,21 @@ namespace openfpga {
* This function write header information to a bitstream file
*******************************************************************/
static
void write_bitstream_xml_file_head(std::fstream& fp) {
void write_bitstream_xml_file_head(std::fstream& fp,
const bool& include_time_stamp) {
valid_file_stream(fp);
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "<!--" << std::endl;
fp << "\t- Architecture independent bitstream" << std::endl;
fp << "\t- Author: Xifan TANG" << std::endl;
fp << "\t- Organization: University of Utah" << std::endl;
fp << "\t- Date: " << std::ctime(&end_time) ;
if (include_time_stamp) {
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "\t- Date: " << std::ctime(&end_time) ;
}
fp << "-->" << std::endl;
fp << std::endl;
}
@ -172,7 +176,8 @@ void rec_write_block_bitstream_to_xml_file(std::fstream& fp,
* 3. TODO: support FASM format
*******************************************************************/
void write_xml_architecture_bitstream(const BitstreamManager& bitstream_manager,
const std::string& fname) {
const std::string& fname,
const bool& include_time_stamp) {
/* Ensure that we have a valid file name */
if (true == fname.empty()) {
VTR_LOG_ERROR("Received empty file name to output bitstream!\n\tPlease specify a valid file name.\n");
@ -188,7 +193,7 @@ void write_xml_architecture_bitstream(const BitstreamManager& bitstream_manager,
check_file_stream(fname.c_str(), fp);
/* Put down a brief introduction */
write_bitstream_xml_file_head(fp);
write_bitstream_xml_file_head(fp, include_time_stamp);
/* Find the top block, which has not parents */
std::vector<ConfigBlockId> top_block = find_bitstream_manager_top_blocks(bitstream_manager);

3
libopenfpga/libfpgabitstream/src/write_xml_arch_bitstream.h
View File

@ -15,7 +15,8 @@
namespace openfpga {
void write_xml_architecture_bitstream(const BitstreamManager& bitstream_manager,
const std::string& fname);
const std::string& fname,
const bool& include_time_stamp);
} /* end namespace openfpga */

16
libopenfpga/libfpgabitstream/test/test_arch_bitstream.cpp
View File

@ -14,7 +14,7 @@
int main(int argc, const char** argv) {
/* Ensure we have only one or two or 3 argument */
VTR_ASSERT((2 == argc) || (3 == argc) || (4 == argc));
VTR_ASSERT((2 == argc) || (3 == argc) || (4 == argc) || (5 == argc));
/* Parse the bitstream from an XML file */
openfpga::BitstreamManager test_bitstream = openfpga::read_xml_architecture_bitstream(argv[1]);
@ -25,16 +25,22 @@ int main(int argc, const char** argv) {
* This is optional only used when there is a second argument
*/
if (3 <= argc) {
openfpga::write_xml_architecture_bitstream(test_bitstream, argv[2]);
VTR_LOG("Echo the bitstream to an XML file: %s.\n",
openfpga::write_xml_architecture_bitstream(test_bitstream, argv[2], true);
VTR_LOG("Echo the bitstream (with time stamp) to an XML file: %s.\n",
argv[2]);
openfpga::write_xml_architecture_bitstream(test_bitstream, argv[2], false);
VTR_LOG("Echo the bitstream (w/o time stamp) to an XML file: %s.\n",
argv[2]);
}
/* Output the bitstream distribution to an XML file
* This is optional only used when there is a third argument
*/
if (4 <= argc) {
openfpga::report_architecture_bitstream_distribution(test_bitstream, argv[3]);
VTR_LOG("Echo the bitstream distribution to an XML file: %s.\n",
openfpga::report_architecture_bitstream_distribution(test_bitstream, argv[3], true);
VTR_LOG("Echo the bitstream distribution (with time stamp) to an XML file: %s.\n",
argv[3]);
openfpga::report_architecture_bitstream_distribution(test_bitstream, argv[3], false);
VTR_LOG("Echo the bitstream distribution (w/o time stamp) to an XML file: %s.\n",
argv[3]);
}

11
openfpga/src/base/openfpga_bitstream.cpp
View File

@ -40,6 +40,7 @@ int fpga_bitstream(OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context) {
CommandOptionId opt_verbose = cmd.option("verbose");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_write_file = cmd.option("write_file");
CommandOptionId opt_read_file = cmd.option("read_file");
@ -58,7 +59,8 @@ int fpga_bitstream(OpenfpgaContext& openfpga_ctx,
create_directory(src_dir_path);
write_xml_architecture_bitstream(openfpga_ctx.bitstream_manager(),
cmd_context.option_value(cmd, opt_write_file));
cmd_context.option_value(cmd, opt_write_file),
!cmd_context.option_enable(cmd, opt_no_time_stamp));
}
/* TODO: should identify the error code from internal function execution */
@ -95,6 +97,7 @@ int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_file_format = cmd.option("format");
CommandOptionId opt_fast_config = cmd.option("fast_configuration");
CommandOptionId opt_keep_dont_care_bits = cmd.option("keep_dont_care_bits");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
/* Write fabric bitstream if required */
int status = CMD_EXEC_SUCCESS;
@ -117,6 +120,7 @@ int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx,
openfpga_ctx.fabric_bitstream(),
openfpga_ctx.arch().config_protocol,
cmd_context.option_value(cmd, opt_file),
!cmd_context.option_enable(cmd, opt_no_time_stamp),
cmd_context.option_enable(cmd, opt_verbose));
} else {
/* By default, output in plain text format */
@ -128,6 +132,7 @@ int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx,
cmd_context.option_value(cmd, opt_file),
cmd_context.option_enable(cmd, opt_fast_config),
cmd_context.option_enable(cmd, opt_keep_dont_care_bits),
!cmd_context.option_enable(cmd, opt_no_time_stamp),
cmd_context.option_enable(cmd, opt_verbose));
}
@ -141,6 +146,7 @@ int write_io_mapping(const OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context) {
CommandOptionId opt_verbose = cmd.option("verbose");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_file = cmd.option("file");
/* Write fabric bitstream if required */
@ -175,6 +181,7 @@ int write_io_mapping(const OpenfpgaContext& openfpga_ctx,
status = write_io_mapping_to_xml_file(io_map,
cmd_context.option_value(cmd, opt_file),
!cmd_context.option_enable(cmd, opt_no_time_stamp),
cmd_context.option_enable(cmd, opt_verbose));
return status;
@ -187,6 +194,7 @@ int report_bitstream_distribution(const OpenfpgaContext& openfpga_ctx,
const Command& cmd, const CommandContext& cmd_context) {
CommandOptionId opt_file = cmd.option("file");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
int status = CMD_EXEC_SUCCESS;
@ -212,6 +220,7 @@ int report_bitstream_distribution(const OpenfpgaContext& openfpga_ctx,
status = report_architecture_bitstream_distribution(openfpga_ctx.bitstream_manager(),
cmd_context.option_value(cmd, opt_file),
!cmd_context.option_enable(cmd, opt_no_time_stamp),
depth);
return status;

11
openfpga/src/base/openfpga_bitstream_command.cpp
View File

@ -57,6 +57,8 @@ ShellCommandId add_openfpga_build_arch_bitstream_command(openfpga::Shell<Openfpg
CommandOptionId opt_read_file = shell_cmd.add_option("read_file", false, "file path to read the bitstream database");
shell_cmd.set_option_require_value(opt_read_file, openfpga::OPT_STRING);
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print time stamp in output files");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");
@ -92,6 +94,9 @@ ShellCommandId add_openfpga_report_bitstream_distribution_command(openfpga::Shel
CommandOptionId opt_depth = shell_cmd.add_option("depth", false, "Specify the max. depth of blocks which will appear in report");
shell_cmd.set_option_require_value(opt_depth, openfpga::OPT_STRING);
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print time stamp in output files");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");
@ -157,6 +162,9 @@ ShellCommandId add_openfpga_write_fabric_bitstream_command(openfpga::Shell<Openf
/* Add an option '--keep_dont_care_bit' */
shell_cmd.add_option("keep_dont_care_bits", false, "Keep don't care bits in bitstream file; If not enabled, don't care bits are converted to logic '0' or '1'");
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print time stamp in output files");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");
@ -187,6 +195,9 @@ ShellCommandId add_openfpga_write_io_mapping_command(openfpga::Shell<OpenfpgaCon
shell_cmd.set_option_short_name(opt_file, "f");
shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print time stamp in output files");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");

8
openfpga/src/base/openfpga_sdc.cpp
View File

@ -45,6 +45,7 @@ int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_constrain_routing_multiplexer_outputs = cmd.option("constrain_routing_multiplexer_outputs");
CommandOptionId opt_constrain_switch_block_outputs = cmd.option("constrain_switch_block_outputs");
CommandOptionId opt_constrain_zero_delay_paths = cmd.option("constrain_zero_delay_paths");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
/* This is an intermediate data structure which is designed to modularize the FPGA-SDC
* Keep it independent from any other outside data structures
@ -74,6 +75,7 @@ int write_pnr_sdc(const OpenfpgaContext& openfpga_ctx,
options.set_constrain_routing_multiplexer_outputs(cmd_context.option_enable(cmd, opt_constrain_routing_multiplexer_outputs));
options.set_constrain_switch_block_outputs(cmd_context.option_enable(cmd, opt_constrain_switch_block_outputs));
options.set_constrain_zero_delay_paths(cmd_context.option_enable(cmd, opt_constrain_zero_delay_paths));
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
/* We first turn on default sdc option and then disable part of them by following users' options */
if (false == options.generate_sdc_pnr()) {
@ -118,6 +120,7 @@ int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_time_unit = cmd.option("time_unit");
CommandOptionId opt_min_delay = cmd.option("min_delay");
CommandOptionId opt_max_delay = cmd.option("max_delay");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
@ -128,6 +131,7 @@ int write_configuration_chain_sdc(const OpenfpgaContext& openfpga_ctx,
time_unit,
std::stof(cmd_context.option_value(cmd, opt_max_delay)),
std::stof(cmd_context.option_value(cmd, opt_min_delay)),
!cmd_context.option_enable(cmd, opt_no_time_stamp),
openfpga_ctx.module_graph());
return CMD_EXEC_SUCCESS;
@ -143,6 +147,7 @@ int write_sdc_disable_timing_configure_ports(const OpenfpgaContext& openfpga_ctx
/* Get command options */
CommandOptionId opt_output_dir = cmd.option("file");
CommandOptionId opt_flatten_names = cmd.option("flatten_names");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_verbose = cmd.option("verbose");
std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
@ -154,6 +159,7 @@ int write_sdc_disable_timing_configure_ports(const OpenfpgaContext& openfpga_ctx
openfpga_ctx.mux_lib(),
openfpga_ctx.arch().circuit_lib,
openfpga_ctx.module_graph(),
!cmd_context.option_enable(cmd, opt_no_time_stamp),
cmd_context.option_enable(cmd, opt_verbose))) {
return CMD_EXEC_FATAL_ERROR;
}
@ -170,6 +176,7 @@ int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_output_dir = cmd.option("file");
CommandOptionId opt_flatten_names = cmd.option("flatten_names");
CommandOptionId opt_time_unit = cmd.option("time_unit");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
/* This is an intermediate data structure which is designed to modularize the FPGA-SDC
* Keep it independent from any other outside data structures
@ -182,6 +189,7 @@ int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx,
AnalysisSdcOption options(sdc_dir_path);
options.set_generate_sdc_analysis(true);
options.set_flatten_names(cmd_context.option_enable(cmd, opt_flatten_names));
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
if (true == cmd_context.option_enable(cmd, opt_time_unit)) {
options.set_time_unit(string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit)));

12
openfpga/src/base/openfpga_sdc_command.cpp
View File

@ -66,6 +66,9 @@ ShellCommandId add_openfpga_write_pnr_sdc_command(openfpga::Shell<OpenfpgaContex
/* Add an option '--constrain_zero_delay_paths' */
shell_cmd.add_option("constrain_zero_delay_paths", false, "Constrain zero-delay paths in FPGA fabric");
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print time stamp in output files");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");
@ -108,6 +111,9 @@ ShellCommandId add_openfpga_write_configuration_chain_sdc_command(openfpga::Shel
CommandOptionId max_dly_opt = shell_cmd.add_option("max_delay", false, "Specify the maximum delay to be used.");
shell_cmd.set_option_require_value(max_dly_opt, openfpga::OPT_STRING);
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print time stamp in output files");
/* Add command 'write_configuration_chain_sdc' to the Shell */
ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files to constrain the configuration chain for FPGA fabric");
shell.set_command_class(shell_cmd_id, cmd_class_id);
@ -138,6 +144,9 @@ ShellCommandId add_openfpga_write_sdc_disable_timing_configure_ports_command(ope
/* Add an option '--flatten_name' */
shell_cmd.add_option("flatten_names", false, "Use flatten names (no wildcards) in SDC files");
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print time stamp in output files");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose outputs");
@ -178,6 +187,9 @@ ShellCommandId add_openfpga_write_analysis_sdc_command(openfpga::Shell<OpenfpgaC
CommandOptionId time_unit_opt = shell_cmd.add_option("time_unit", false, "Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|kM]s");
shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print time stamp in output files");
/* Add command 'write_fabric_verilog' to the Shell */
ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SDC files for timing analysis a PnRed FPGA fabric mapped by a benchmark");
shell.set_command_class(shell_cmd_id, cmd_class_id);

8
openfpga/src/base/openfpga_verilog.cpp
View File

@ -34,6 +34,7 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_include_timing = cmd.option("include_timing");
CommandOptionId opt_print_user_defined_template = cmd.option("print_user_defined_template");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -43,6 +44,7 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_include_timing(cmd_context.option_enable(cmd, opt_include_timing));
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
options.set_print_user_defined_template(cmd_context.option_enable(cmd, opt_print_user_defined_template));
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
@ -80,6 +82,7 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -92,6 +95,7 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_fast_configuration(cmd_context.option_enable(cmd, opt_fast_configuration));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
options.set_print_top_testbench(true);
options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
@ -134,6 +138,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -143,6 +148,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
options.set_print_formal_verification_top_netlist(true);
@ -186,6 +192,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -196,6 +203,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_preconfig_top_testbench(true);
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {

12
openfpga/src/base/openfpga_verilog_command.cpp
View File

@ -40,6 +40,9 @@ ShellCommandId add_openfpga_write_fabric_verilog_command(openfpga::Shell<Openfpg
CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print a time stamp in the output files");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");
@ -103,6 +106,9 @@ ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell<Openfpg
/* add an option '--include_signal_init' */
shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print a time stamp in the output files");
/* add an option '--verbose' */
shell_cmd.add_option("verbose", false, "enable verbose output");
@ -156,6 +162,9 @@ ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga:
/* add an option '--include_signal_init' */
shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print a time stamp in the output files");
/* add an option '--verbose' */
shell_cmd.add_option("verbose", false, "enable verbose output");
@ -206,6 +215,9 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel
CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print a time stamp in the output files");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");

16
openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp
View File

@ -30,15 +30,18 @@ namespace openfpga {
* This function write header information to a bitstream file
*******************************************************************/
static
void write_fabric_bitstream_text_file_head(std::fstream& fp) {
void write_fabric_bitstream_text_file_head(std::fstream& fp,
const bool& include_time_stamp) {
valid_file_stream(fp);
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "// Fabric bitstream" << std::endl;
fp << "// Version: " << openfpga::VERSION << std::endl;
fp << "// Date: " << std::ctime(&end_time);
if (include_time_stamp) {
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "// Date: " << std::ctime(&end_time);
}
}
/********************************************************************
@ -370,6 +373,7 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage
const std::string& fname,
const bool& fast_configuration,
const bool& keep_dont_care_bits,
const bool& include_time_stamp,
const bool& verbose) {
/* Ensure that we have a valid file name */
if (true == fname.empty()) {
@ -399,7 +403,7 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage
}
/* Write file head */
write_fabric_bitstream_text_file_head(fp);
write_fabric_bitstream_text_file_head(fp, include_time_stamp);
/* Output fabric bitstream to the file */
int status = 0;

1
openfpga/src/fpga_bitstream/write_text_fabric_bitstream.h
View File

@ -27,6 +27,7 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage
const std::string& fname,
const bool& fast_configuration,
const bool& keep_dont_care_bits,
const bool& include_time_stamp,
const bool& verbose);
} /* end namespace openfpga */

17
openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp
View File

@ -28,17 +28,21 @@ namespace openfpga {
* This function write header information to a bitstream file
*******************************************************************/
static
void write_fabric_bitstream_xml_file_head(std::fstream& fp) {
void write_fabric_bitstream_xml_file_head(std::fstream& fp,
const bool& include_time_stamp) {
valid_file_stream(fp);
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "<!--" << std::endl;
fp << "\t- Fabric bitstream" << std::endl;
fp << "\t- Author: Xifan TANG" << std::endl;
fp << "\t- Organization: University of Utah" << std::endl;
fp << "\t- Date: " << std::ctime(&end_time) ;
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
if (include_time_stamp) {
fp << "\t- Date: " << std::ctime(&end_time) ;
}
fp << "-->" << std::endl;
fp << std::endl;
}
@ -201,6 +205,7 @@ int write_fabric_bitstream_to_xml_file(const BitstreamManager& bitstream_manager
const FabricBitstream& fabric_bitstream,
const ConfigProtocol& config_protocol,
const std::string& fname,
const bool& include_time_stamp,
const bool& verbose) {
/* Ensure that we have a valid file name */
if (true == fname.empty()) {
@ -217,7 +222,7 @@ int write_fabric_bitstream_to_xml_file(const BitstreamManager& bitstream_manager
check_file_stream(fname.c_str(), fp);
/* Write XML head */
write_fabric_bitstream_xml_file_head(fp);
write_fabric_bitstream_xml_file_head(fp, include_time_stamp);
int xml_hierarchy_depth = 0;
fp << "<fabric_bitstream>\n";

1
openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.h
View File

@ -21,6 +21,7 @@ int write_fabric_bitstream_to_xml_file(const BitstreamManager& bitstream_manager
const FabricBitstream& fabric_bitstream,
const ConfigProtocol& config_protocol,
const std::string& fname,
const bool& include_time_stamp,
const bool& verbose);
} /* end namespace openfpga */

17
openfpga/src/fpga_bitstream/write_xml_io_mapping.cpp
View File

@ -29,16 +29,20 @@ namespace openfpga {
* This function write header information to an I/O mapping file
*******************************************************************/
static
void write_io_mapping_xml_file_head(std::fstream& fp) {
void write_io_mapping_xml_file_head(std::fstream& fp,
const bool& include_time_stamp) {
valid_file_stream(fp);
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "<!--" << std::endl;
fp << "\t- I/O mapping" << std::endl;
fp << "\t- Version: " << openfpga::VERSION << std::endl;
fp << "\t- Date: " << std::ctime(&end_time) ;
if (include_time_stamp) {
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "\t- Date: " << std::ctime(&end_time) ;
}
fp << "-->" << std::endl;
fp << std::endl;
}
@ -93,6 +97,7 @@ int write_io_mapping_pair_to_xml_file(std::fstream& fp,
*******************************************************************/
int write_io_mapping_to_xml_file(const IoMap& io_map,
const std::string& fname,
const bool& include_time_stamp,
const bool& verbose) {
/* Ensure that we have a valid file name */
if (true == fname.empty()) {
@ -110,7 +115,7 @@ int write_io_mapping_to_xml_file(const IoMap& io_map,
check_file_stream(fname.c_str(), fp);
/* Write XML head */
write_io_mapping_xml_file_head(fp);
write_io_mapping_xml_file_head(fp, include_time_stamp);
int xml_hierarchy_depth = 0;
fp << "<io_mapping>\n";

1
openfpga/src/fpga_bitstream/write_xml_io_mapping.h
View File

@ -18,6 +18,7 @@ namespace openfpga {
int write_io_mapping_to_xml_file(const IoMap& io_map,
const std::string& fname,
const bool& include_time_stamp,
const bool& verbose);
} /* end namespace openfpga */

9
openfpga/src/fpga_sdc/analysis_sdc_option.cpp
View File

@ -13,6 +13,7 @@ AnalysisSdcOption::AnalysisSdcOption(const std::string& sdc_dir) {
sdc_dir_ = sdc_dir;
flatten_names_ = false;
time_unit_ = 1.;
time_stamp_ = true;
generate_sdc_analysis_ = false;
}
@ -31,6 +32,10 @@ float AnalysisSdcOption::time_unit() const {
return time_unit_;
}
bool AnalysisSdcOption::time_stamp() const {
return time_stamp_;
}
bool AnalysisSdcOption::generate_sdc_analysis() const {
return generate_sdc_analysis_;
}
@ -50,6 +55,10 @@ void AnalysisSdcOption::set_time_unit(const float& time_unit) {
time_unit_ = time_unit;
}
void AnalysisSdcOption::set_time_stamp(const bool& enable) {
time_stamp_ = enable;
}
void AnalysisSdcOption::set_generate_sdc_analysis(const bool& generate_sdc_analysis) {
generate_sdc_analysis_ = generate_sdc_analysis;
}

3
openfpga/src/fpga_sdc/analysis_sdc_option.h
View File

@ -19,9 +19,11 @@ class AnalysisSdcOption {
bool flatten_names() const;
float time_unit() const;
bool generate_sdc_analysis() const;
bool time_stamp() const;
public: /* Public mutators */
void set_sdc_dir(const std::string& sdc_dir);
void set_flatten_names(const bool& flatten_names);
void set_time_stamp(const bool& time_stamp);
void set_time_unit(const float& time_unit);
void set_generate_sdc_analysis(const bool& generate_sdc_analysis);
private: /* Internal data */
@ -29,6 +31,7 @@ class AnalysisSdcOption {
bool generate_sdc_analysis_;
bool flatten_names_;
float time_unit_;
bool time_stamp_;
};
} /* end namespace openfpga */

4
openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
View File

@ -235,7 +235,9 @@ void print_analysis_sdc(const AnalysisSdcOption& option,
check_file_stream(sdc_fname.c_str(), fp);
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Constrain for Timing/Power analysis on the mapped FPGA"));
print_sdc_file_header(fp,
std::string("Constrain for Timing/Power analysis on the mapped FPGA"),
option.time_stamp());
/* Find the top_module */
ModuleId top_module = openfpga_ctx.module_graph().find_module(generate_fpga_top_module_name());

5
openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
View File

@ -133,6 +133,7 @@ void print_pnr_sdc_constrain_configurable_chain(const std::string& sdc_fname,
const float& time_unit,
const float& max_delay,
const float& min_delay,
const bool& include_time_stamp,
const ModuleManager& module_manager) {
/* Create the directory */
@ -149,7 +150,9 @@ void print_pnr_sdc_constrain_configurable_chain(const std::string& sdc_fname,
check_file_stream(sdc_fname.c_str(), fp);
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Timing constraints for configurable chains used in PnR"));
print_sdc_file_header(fp,
std::string("Timing constraints for configurable chains used in PnR"),
include_time_stamp);
/* Print time unit for the SDC file */
print_sdc_timescale(fp, time_unit_to_string(time_unit));

1
openfpga/src/fpga_sdc/configuration_chain_sdc_writer.h
View File

@ -19,6 +19,7 @@ void print_pnr_sdc_constrain_configurable_chain(const std::string& sdc_fname,
const float& time_unit,
const float& max_delay,
const float& min_delay,
const bool& include_time_stamp,
const ModuleManager& module_manager);
} /* end namespace openfpga */

5
openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
View File

@ -187,6 +187,7 @@ int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager,
const bool& include_time_stamp,
const bool& verbose) {
/* Create the directory */
create_directory(find_path_dir_name(sdc_fname));
@ -202,7 +203,9 @@ int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
check_file_stream(sdc_fname.c_str(), fp);
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Disable configuration outputs of all the programmable cells for PnR"));
print_sdc_file_header(fp,
std::string("Disable configuration outputs of all the programmable cells for PnR"),
include_time_stamp);
std::string top_module_name = generate_fpga_top_module_name();
ModuleId top_module = module_manager.find_module(top_module_name);

1
openfpga/src/fpga_sdc/configure_port_sdc_writer.h
View File

@ -20,6 +20,7 @@ int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager,
const bool& include_time_stamp,
const bool& verbose);
} /* end namespace openfpga */

15
openfpga/src/fpga_sdc/pnr_sdc_global_port.cpp
View File

@ -163,13 +163,16 @@ void print_pnr_sdc_global_non_clock_ports(std::fstream& fp,
* should be treated in CTS or not
* In general, we do not recommend to do this
*******************************************************************/
void print_pnr_sdc_global_ports(const std::string& sdc_dir,
const float& time_unit,
void print_pnr_sdc_global_ports(const PnrSdcOption& options,
const ModuleManager& module_manager,
const ModuleId& top_module,
const FabricGlobalPortInfo& global_ports,
const SimulationSetting& sim_setting,
const bool& constrain_non_clock_port) {
const SimulationSetting& sim_setting) {
std::string sdc_dir = options.sdc_dir();
float time_unit = options.time_unit();
bool include_time_stamp = options.time_stamp();
bool constrain_non_clock_port = options.constrain_non_clock_global_port();
/* Create the file name for Verilog netlist */
std::string sdc_fname(sdc_dir + std::string(SDC_GLOBAL_PORTS_FILE_NAME));
@ -185,7 +188,9 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir,
check_file_stream(sdc_fname.c_str(), fp);
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Clock contraints for PnR"));
print_sdc_file_header(fp,
std::string("Clock contraints for PnR"),
include_time_stamp);
/* Print time unit for the SDC file */
print_sdc_timescale(fp, time_unit_to_string(time_unit));

7
openfpga/src/fpga_sdc/pnr_sdc_global_port.h
View File

@ -9,6 +9,7 @@
#include "module_manager.h"
#include "fabric_global_port_info.h"
#include "simulation_setting.h"
#include "pnr_sdc_option.h"
/********************************************************************
* Function declaration
@ -17,13 +18,11 @@
/* begin namespace openfpga */
namespace openfpga {
void print_pnr_sdc_global_ports(const std::string& sdc_dir,
const float& time_unit,
void print_pnr_sdc_global_ports(const PnrSdcOption& options,
const ModuleManager& module_manager,
const ModuleId& top_module,
const FabricGlobalPortInfo& global_ports,
const SimulationSetting& sim_setting,
const bool& constrain_non_clock_port);
const SimulationSetting& sim_setting);
} /* end namespace openfpga */

90
openfpga/src/fpga_sdc/pnr_sdc_grid_writer.cpp
View File

@ -240,14 +240,16 @@ void print_pnr_sdc_constrain_pb_interc_timing(std::fstream& fp,
* 3. output port of child_pb_graph_node and input port of child_pb_graph_nodes
*******************************************************************/
static
void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_constrain_pb_graph_node_timing(const PnrSdcOption& options,
const std::string& module_path,
const ModuleManager& module_manager,
t_pb_graph_node* parent_pb_graph_node,
t_mode* physical_mode,
const bool& constrain_zero_delay_paths) {
t_mode* physical_mode) {
std::string sdc_dir = options.sdc_dir();
float time_unit = options.time_unit();
bool hierarchical = options.hierarchical();
bool include_time_stamp = options.time_stamp();
bool constrain_zero_delay_paths = options.constrain_zero_delay_paths();
/* Get the pb_type definition related to the node */
t_pb_type* physical_pb_type = parent_pb_graph_node->pb_type;
@ -267,7 +269,9 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
check_file_stream(sdc_fname.c_str(), fp);
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Timing constraints for Grid " + pb_module_name + " in PnR"));
print_sdc_file_header(fp,
std::string("Timing constraints for Grid " + pb_module_name + " in PnR"),
include_time_stamp);
/* Print time unit for the SDC file */
print_sdc_timescale(fp, time_unit_to_string(time_unit));
@ -326,13 +330,10 @@ void print_pnr_sdc_constrain_pb_graph_node_timing(const std::string& sdc_dir,
* When PnR the modules, we want to minimize the interconnect delay
*******************************************************************/
static
void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_constrain_primitive_pb_graph_node(const PnrSdcOption& options,
const std::string& module_path,
const ModuleManager& module_manager,
t_pb_graph_node* primitive_pb_graph_node,
const bool& constrain_zero_delay_paths) {
t_pb_graph_node* primitive_pb_graph_node) {
/* Validate pb_graph node */
if (nullptr == primitive_pb_graph_node) {
VTR_LOGF_ERROR(__FILE__, __LINE__,
@ -378,7 +379,7 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
/* Create the file name for SDC */
std::string sdc_fname(sdc_dir + pb_module_name + std::string(SDC_FILE_NAME_POSTFIX));
std::string sdc_fname(options.sdc_dir() + pb_module_name + std::string(SDC_FILE_NAME_POSTFIX));
/* Create the file stream */
std::fstream fp;
@ -387,10 +388,12 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
check_file_stream(sdc_fname.c_str(), fp);
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Timing constraints for Grid " + pb_module_name + " in PnR"));
print_sdc_file_header(fp,
std::string("Timing constraints for Grid " + pb_module_name + " in PnR"),
options.time_stamp());
/* Print time unit for the SDC file */
print_sdc_timescale(fp, time_unit_to_string(time_unit));
print_sdc_timescale(fp, time_unit_to_string(options.time_unit()));
/* We traverse the pb_graph pins where we can find pin-to-pin timing annotation
* We walk through input pins here, build timing constraints by pair each input to output
@ -424,32 +427,32 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
/* Generate module path in hierarchy depending if the hierarchical is enabled */
std::string module_hie_path = pb_module_name;
if (false == hierarchical) {
if (false == options.hierarchical()) {
module_hie_path = module_path + pb_module_name;
}
/* If the delay is zero, constrain only when user wants it */
if ( (true == constrain_zero_delay_paths)
if ( (true == options.constrain_zero_delay_paths())
|| (0. != tmax) ) {
print_pnr_sdc_constrain_max_delay(fp,
module_hie_path,
generate_sdc_port(src_port),
module_hie_path,
generate_sdc_port(sink_port),
tmax / time_unit);
tmax / options.time_unit());
}
/* Find min delay between src and sink pin */
float tmin = src_pin->pin_timing_del_min[itiming];
/* If the delay is zero, constrain only when user wants it */
if ( (true == constrain_zero_delay_paths)
if ( (true == options.constrain_zero_delay_paths())
|| (0. != tmin) ) {
print_pnr_sdc_constrain_min_delay(fp,
module_hie_path,
generate_sdc_port(src_port),
module_hie_path,
generate_sdc_port(sink_port),
tmin / time_unit);
tmin / options.time_unit());
}
}
}
@ -465,14 +468,11 @@ void print_pnr_sdc_constrain_primitive_pb_graph_node(const std::string& sdc_dir,
* constraining the pin-to-pin timing
*******************************************************************/
static
void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void rec_print_pnr_sdc_constrain_pb_graph_timing(const PnrSdcOption& options,
const std::string& module_path,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
t_pb_graph_node* parent_pb_graph_node,
const bool& constrain_zero_delay_paths) {
t_pb_graph_node* parent_pb_graph_node) {
/* Validate pb_graph node */
if (nullptr == parent_pb_graph_node) {
VTR_LOGF_ERROR(__FILE__, __LINE__,
@ -485,13 +485,10 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
/* Constrain the primitive node if a timing matrix is defined */
if (true == is_primitive_pb_type(parent_pb_type)) {
print_pnr_sdc_constrain_primitive_pb_graph_node(sdc_dir,
time_unit,
hierarchical,
print_pnr_sdc_constrain_primitive_pb_graph_node(options,
module_path,
module_manager,
parent_pb_graph_node,
constrain_zero_delay_paths);
parent_pb_graph_node);
return;
}
@ -501,41 +498,32 @@ void rec_print_pnr_sdc_constrain_pb_graph_timing(const std::string& sdc_dir,
t_mode* physical_mode = device_annotation.physical_mode(parent_pb_type);
/* Write a SDC file for this pb_type */
print_pnr_sdc_constrain_pb_graph_node_timing(sdc_dir,
time_unit,
hierarchical,
print_pnr_sdc_constrain_pb_graph_node_timing(options,
module_path,
module_manager,
parent_pb_graph_node,
physical_mode,
constrain_zero_delay_paths);
physical_mode);
/* Go recursively to the lower level in the pb_graph
* Note that we assume a full hierarchical P&R, we will only visit pb_graph_node of unique pb_type
*/
for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
time_unit,
hierarchical,
rec_print_pnr_sdc_constrain_pb_graph_timing(options,
format_dir_path(module_path + generate_physical_block_instance_name(&(physical_mode->pb_type_children[ipb]), ipb)),
module_manager,
device_annotation,
&(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]),
constrain_zero_delay_paths);
&(parent_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]));
}
}
/********************************************************************
* Top-level function to print timing constraints for pb_types
*******************************************************************/
void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_constrain_grid_timing(const PnrSdcOption& options,
const DeviceContext& device_ctx,
const VprDeviceAnnotation& device_annotation,
const ModuleManager& module_manager,
const ModuleId& top_module,
const bool& constrain_zero_delay_paths) {
const ModuleId& top_module) {
/* Start time count */
vtr::ScopedStartFinishTimer timer("Write SDC for constraining grid timing for P&R flow");
@ -580,14 +568,11 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
std::string module_path = format_dir_path(root_path + grid_module_name);
module_path = format_dir_path(module_path + generate_physical_block_instance_name(pb_graph_head->pb_type, pb_graph_head->placement_index));
rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
time_unit,
hierarchical,
rec_print_pnr_sdc_constrain_pb_graph_timing(options,
module_path,
module_manager,
device_annotation,
pb_graph_head,
constrain_zero_delay_paths);
pb_graph_head);
}
} else {
/* For CLB and heterogenenous blocks */
@ -602,14 +587,11 @@ void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
std::string module_path = format_dir_path(root_path + grid_module_name);
module_path = format_dir_path(module_path + generate_physical_block_instance_name(pb_graph_head->pb_type, pb_graph_head->placement_index));
rec_print_pnr_sdc_constrain_pb_graph_timing(sdc_dir,
time_unit,
hierarchical,
rec_print_pnr_sdc_constrain_pb_graph_timing(options,
module_path,
module_manager,
device_annotation,
pb_graph_head,
constrain_zero_delay_paths);
pb_graph_head);
}
}
}

8
openfpga/src/fpga_sdc/pnr_sdc_grid_writer.h
View File

@ -9,6 +9,7 @@
#include "vpr_context.h"
#include "vpr_device_annotation.h"
#include "module_manager.h"
#include "pnr_sdc_option.h"
/********************************************************************
* Function declaration
@ -17,14 +18,11 @@
/* begin namespace openfpga */
namespace openfpga {
void print_pnr_sdc_constrain_grid_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_constrain_grid_timing(const PnrSdcOption& options,
const DeviceContext& device_ctx,
const VprDeviceAnnotation& device_annotation,
const ModuleManager& module_manager,
const ModuleId& top_module,
const bool& constrain_zero_delay_paths);
const ModuleId& top_module);
} /* end namespace openfpga */

9
openfpga/src/fpga_sdc/pnr_sdc_option.cpp
View File

@ -23,6 +23,7 @@ PnrSdcOption::PnrSdcOption(const std::string& sdc_dir) {
constrain_routing_multiplexer_outputs_ = false;
constrain_switch_block_outputs_ = false;
constrain_zero_delay_paths_ = false;
time_stamp_ = true;
}
/********************************************************************
@ -94,6 +95,10 @@ bool PnrSdcOption::constrain_zero_delay_paths() const {
return constrain_zero_delay_paths_;
}
bool PnrSdcOption::time_stamp() const {
return time_stamp_;
}
/********************************************************************
* Public mutators
********************************************************************/
@ -163,4 +168,8 @@ void PnrSdcOption::set_constrain_zero_delay_paths(const bool& constrain_zero_del
constrain_zero_delay_paths_ = constrain_zero_delay_paths;
}
void PnrSdcOption::set_time_stamp(const bool& enable) {
time_stamp_ = enable;
}
} /* end namespace openfpga */

3
openfpga/src/fpga_sdc/pnr_sdc_option.h
View File

@ -30,6 +30,7 @@ class PnrSdcOption {
bool constrain_routing_multiplexer_outputs() const;
bool constrain_switch_block_outputs() const;
bool constrain_zero_delay_paths() const;
bool time_stamp() const;
public: /* Public mutators */
void set_sdc_dir(const std::string& sdc_dir);
void set_flatten_names(const bool& flatten_names);
@ -46,6 +47,7 @@ class PnrSdcOption {
void set_constrain_routing_multiplexer_outputs(const bool& constrain_routing_mux_outputs);
void set_constrain_switch_block_outputs(const bool& constrain_sb_outputs);
void set_constrain_zero_delay_paths(const bool& constrain_zero_delay_paths);
void set_time_stamp(const bool& enable);
private: /* Internal data */
std::string sdc_dir_;
bool flatten_names_;
@ -61,6 +63,7 @@ class PnrSdcOption {
bool constrain_routing_multiplexer_outputs_;
bool constrain_switch_block_outputs_;
bool constrain_zero_delay_paths_;
bool time_stamp_;
};
} /* end namespace openfpga */

115
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
View File

@ -142,16 +142,18 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
* file for each unique SB module
*******************************************************************/
static
void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_constrain_sb_timing(const PnrSdcOption& options,
const std::string& module_path,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const bool& constrain_zero_delay_paths) {
const RRGSB& rr_gsb) {
std::string sdc_dir = options.sdc_dir();
float time_unit = options.time_unit();
bool hierarchical = options.hierarchical();
bool include_time_stamp = options.time_stamp();
bool constrain_zero_delay_paths = options.constrain_zero_delay_paths();
/* Create the file name for Verilog netlist */
vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
@ -169,7 +171,9 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Constrain timing of Switch Block " + sb_module_name + " for PnR"));
print_sdc_file_header(fp,
std::string("Constrain timing of Switch Block " + sb_module_name + " for PnR"),
include_time_stamp);
/* Print time unit for the SDC file */
print_sdc_timescale(fp, time_unit_to_string(time_unit));
@ -210,16 +214,13 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
* Print SDC timing constraints for Switch blocks
* This function is designed for flatten routing hierarchy
*******************************************************************/
void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_flatten_routing_constrain_sb_timing(const PnrSdcOption& options,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths) {
const DeviceRRGSB& device_rr_gsb) {
/* Start time count */
vtr::ScopedStartFinishTimer timer("Write SDC for constrain Switch Block timing for P&R flow");
@ -244,16 +245,13 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
std::string module_path = format_dir_path(root_path) + sb_instance_name;
print_pnr_sdc_constrain_sb_timing(sdc_dir,
time_unit,
hierarchical,
print_pnr_sdc_constrain_sb_timing(options,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
rr_gsb,
constrain_zero_delay_paths);
rr_gsb);
}
}
}
@ -262,16 +260,13 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
* Print SDC timing constraints for Switch blocks
* This function is designed for compact routing hierarchy
*******************************************************************/
void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_compact_routing_constrain_sb_timing(const PnrSdcOption& options,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths) {
const DeviceRRGSB& device_rr_gsb) {
/* Start time count */
vtr::ScopedStartFinishTimer timer("Write SDC for constrain Switch Block timing for P&R flow");
@ -295,16 +290,13 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
std::string module_path = format_dir_path(root_path) + sb_module_name;
print_pnr_sdc_constrain_sb_timing(sdc_dir,
time_unit,
hierarchical,
print_pnr_sdc_constrain_sb_timing(options,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
rr_gsb,
constrain_zero_delay_paths);
rr_gsb);
}
}
@ -420,17 +412,20 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
* This function is designed for compact routing hierarchy
*******************************************************************/
static
void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_constrain_cb_timing(const PnrSdcOption& options,
const std::string& module_path,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const bool& constrain_zero_delay_paths) {
const t_rr_type& cb_type) {
std::string sdc_dir = options.sdc_dir();
float time_unit = options.time_unit();
bool include_time_stamp = options.time_stamp();
bool hierarchical = options.hierarchical();
bool constrain_zero_delay_paths = options.constrain_zero_delay_paths();
/* Create the netlist */
vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
@ -449,7 +444,9 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Constrain timing of Connection Block " + cb_module_name + " for PnR"));
print_sdc_file_header(fp,
std::string("Constrain timing of Connection Block " + cb_module_name + " for PnR"),
include_time_stamp);
/* Print time unit for the SDC file */
print_sdc_timescale(fp, time_unit_to_string(time_unit));
@ -538,17 +535,14 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
* and print SDC file for each of them
*******************************************************************/
static
void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_flatten_routing_constrain_cb_timing(const PnrSdcOption& options,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const t_rr_type& cb_type,
const bool& constrain_zero_delay_paths) {
const t_rr_type& cb_type) {
/* Build unique X-direction connection block modules */
vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
@ -575,17 +569,14 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
std::string module_path = format_dir_path(root_path) + cb_instance_name;
print_pnr_sdc_constrain_cb_timing(sdc_dir,
time_unit,
hierarchical,
print_pnr_sdc_constrain_cb_timing(options,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
rr_gsb,
cb_type,
constrain_zero_delay_paths);
cb_type);
}
}
@ -595,55 +586,45 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
* Iterate over all the connection blocks in a device
* and print SDC file for each of them
*******************************************************************/
void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_flatten_routing_constrain_cb_timing(const PnrSdcOption& options,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths) {
const DeviceRRGSB& device_rr_gsb) {
/* Start time count */
vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, time_unit,
hierarchical,
print_pnr_sdc_flatten_routing_constrain_cb_timing(options,
module_manager, top_module,
device_annotation,
grids,
rr_graph,
device_rr_gsb,
CHANX,
constrain_zero_delay_paths);
CHANX);
print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, time_unit,
hierarchical,
print_pnr_sdc_flatten_routing_constrain_cb_timing(options,
module_manager, top_module,
device_annotation,
grids,
rr_graph,
device_rr_gsb,
CHANY,
constrain_zero_delay_paths);
CHANY);
}
/********************************************************************
* Print SDC timing constraints for Connection blocks
* This function is designed for compact routing hierarchy
*******************************************************************/
void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_compact_routing_constrain_cb_timing(const PnrSdcOption& options,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths) {
const DeviceRRGSB& device_rr_gsb) {
/* Start time count */
vtr::ScopedStartFinishTimer timer("Write SDC for constrain Connection Block timing for P&R flow");
@ -664,17 +645,14 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
std::string module_path = format_dir_path(root_path) + cb_module_name;
print_pnr_sdc_constrain_cb_timing(sdc_dir,
time_unit,
hierarchical,
print_pnr_sdc_constrain_cb_timing(options,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
unique_mirror,
CHANX,
constrain_zero_delay_paths);
CHANX);
}
/* Print SDC for unique Y-direction connection block modules */
@ -691,17 +669,14 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
std::string module_path = format_dir_path(root_path) + cb_module_name;
print_pnr_sdc_constrain_cb_timing(sdc_dir,
time_unit,
hierarchical,
print_pnr_sdc_constrain_cb_timing(options,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
unique_mirror,
CHANY,
constrain_zero_delay_paths);
CHANY);
}
}

29
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
View File

@ -11,6 +11,7 @@
#include "rr_graph_obj.h"
#include "device_grid.h"
#include "vpr_device_annotation.h"
#include "pnr_sdc_option.h"
/********************************************************************
* Function declaration
@ -19,49 +20,37 @@
/* begin namespace openfpga */
namespace openfpga {
void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_flatten_routing_constrain_sb_timing(const PnrSdcOption& options,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths);
const DeviceRRGSB& device_rr_gsb);
void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_compact_routing_constrain_sb_timing(const PnrSdcOption& options,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths);
const DeviceRRGSB& device_rr_gsb);
void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_flatten_routing_constrain_cb_timing(const PnrSdcOption& options,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths);
const DeviceRRGSB& device_rr_gsb);
void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_dir,
const float& time_unit,
const bool& hierarchical,
void print_pnr_sdc_compact_routing_constrain_cb_timing(const PnrSdcOption& options,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths);
const DeviceRRGSB& device_rr_gsb);
} /* end namespace openfpga */

54
openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
View File

@ -47,6 +47,7 @@ namespace openfpga {
static
void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_dir,
const bool& flatten_names,
const bool& include_time_stamp,
const ModuleManager& module_manager,
const ModuleId& top_module) {
@ -64,7 +65,7 @@ void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_
check_file_stream(sdc_fname.c_str(), fp);
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Disable configurable memory outputs for PnR"));
print_sdc_file_header(fp, std::string("Disable configurable memory outputs for PnR"), include_time_stamp);
/* Go recursively in the module manager, starting from the top-level module: instance id of the top-level module is 0 by default */
rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, flatten_names,
@ -84,6 +85,7 @@ void print_pnr_sdc_constrain_configurable_memory_outputs(const std::string& sdc_
static
void print_pnr_sdc_flatten_routing_disable_switch_block_outputs(const std::string& sdc_dir,
const bool& flatten_names,
const bool& include_time_stamp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const DeviceRRGSB& device_rr_gsb) {
@ -101,7 +103,7 @@ void print_pnr_sdc_flatten_routing_disable_switch_block_outputs(const std::strin
check_file_stream(sdc_fname.c_str(), fp);
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR"));
print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR"), include_time_stamp);
std::string root_path = format_dir_path(module_manager.module_name(top_module));
@ -201,6 +203,7 @@ void print_pnr_sdc_flatten_routing_disable_switch_block_outputs(const std::strin
static
void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::string& sdc_dir,
const bool& flatten_names,
const bool& include_time_stamp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const DeviceRRGSB& device_rr_gsb) {
@ -218,7 +221,7 @@ void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::strin
check_file_stream(sdc_fname.c_str(), fp);
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR"));
print_sdc_file_header(fp, std::string("Disable Switch Block outputs for PnR"), include_time_stamp);
std::string root_path = format_dir_path(module_manager.module_name(top_module));
@ -335,17 +338,16 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
/* Constrain global ports */
if (true == sdc_options.constrain_global_port()) {
print_pnr_sdc_global_ports(sdc_options.sdc_dir(),
sdc_options.time_unit(),
print_pnr_sdc_global_ports(sdc_options,
module_manager, top_module, global_ports,
sim_setting,
sdc_options.constrain_non_clock_global_port());
sim_setting);
}
/* Output Design Constraints to disable outputs of memory cells */
if (true == sdc_options.constrain_configurable_memory_outputs()) {
print_pnr_sdc_constrain_configurable_memory_outputs(sdc_options.sdc_dir(),
sdc_options.flatten_names(),
sdc_options.time_stamp(),
module_manager,
top_module);
}
@ -354,6 +356,7 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
if (true == sdc_options.constrain_routing_multiplexer_outputs()) {
print_sdc_disable_routing_multiplexer_outputs(sdc_options.sdc_dir(),
sdc_options.flatten_names(),
sdc_options.time_stamp(),
mux_lib, circuit_lib,
module_manager,
top_module);
@ -364,12 +367,14 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
if (true == compact_routing_hierarchy) {
print_pnr_sdc_compact_routing_disable_switch_block_outputs(sdc_options.sdc_dir(),
sdc_options.flatten_names(),
sdc_options.time_stamp(),
module_manager, top_module,
device_rr_gsb);
} else {
VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
print_pnr_sdc_flatten_routing_disable_switch_block_outputs(sdc_options.sdc_dir(),
sdc_options.flatten_names(),
sdc_options.time_stamp(),
module_manager, top_module,
device_rr_gsb);
}
@ -378,28 +383,22 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
/* Output routing constraints for Switch Blocks */
if (true == sdc_options.constrain_sb()) {
if (true == compact_routing_hierarchy) {
print_pnr_sdc_compact_routing_constrain_sb_timing(sdc_options.sdc_dir(),
sdc_options.time_unit(),
sdc_options.hierarchical(),
print_pnr_sdc_compact_routing_constrain_sb_timing(sdc_options,
module_manager,
top_module,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
device_rr_gsb,
sdc_options.constrain_zero_delay_paths());
device_rr_gsb);
} else {
VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
print_pnr_sdc_flatten_routing_constrain_sb_timing(sdc_options.sdc_dir(),
sdc_options.time_unit(),
sdc_options.hierarchical(),
print_pnr_sdc_flatten_routing_constrain_sb_timing(sdc_options,
module_manager,
top_module,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
device_rr_gsb,
sdc_options.constrain_zero_delay_paths());
device_rr_gsb);
}
}
@ -416,28 +415,22 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
/* Output routing constraints for Connection Blocks */
if (true == sdc_options.constrain_cb()) {
if (true == compact_routing_hierarchy) {
print_pnr_sdc_compact_routing_constrain_cb_timing(sdc_options.sdc_dir(),
sdc_options.time_unit(),
sdc_options.hierarchical(),
print_pnr_sdc_compact_routing_constrain_cb_timing(sdc_options,
module_manager,
top_module,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
device_rr_gsb,
sdc_options.constrain_zero_delay_paths());
device_rr_gsb);
} else {
VTR_ASSERT_SAFE (false == compact_routing_hierarchy);
print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_options.sdc_dir(),
sdc_options.time_unit(),
sdc_options.hierarchical(),
print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_options,
module_manager,
top_module,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
device_rr_gsb,
sdc_options.constrain_zero_delay_paths());
device_rr_gsb);
}
}
@ -460,14 +453,11 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
/* Output Timing constraints for Programmable blocks */
if (true == sdc_options.constrain_grid()) {
print_pnr_sdc_constrain_grid_timing(sdc_options.sdc_dir(),
sdc_options.time_unit(),
sdc_options.hierarchical(),
print_pnr_sdc_constrain_grid_timing(sdc_options,
device_ctx,
device_annotation,
module_manager,
top_module,
sdc_options.constrain_zero_delay_paths());
top_module);
}
if ( (true == sdc_options.constrain_grid())

3
openfpga/src/fpga_sdc/sdc_mux_utils.cpp
View File

@ -35,6 +35,7 @@ namespace openfpga {
*******************************************************************/
void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
const bool& flatten_names,
const bool& include_time_stamp,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager,
@ -53,7 +54,7 @@ void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
check_file_stream(sdc_fname.c_str(), fp);
/* Generate the descriptions*/
print_sdc_file_header(fp, std::string("Disable routing multiplexer outputs for PnR"));
print_sdc_file_header(fp, std::string("Disable routing multiplexer outputs for PnR"), include_time_stamp);
/* Iterate over the MUX modules */
for (const MuxId& mux_id : mux_lib.muxes()) {

1
openfpga/src/fpga_sdc/sdc_mux_utils.h
View File

@ -19,6 +19,7 @@ namespace openfpga {
void print_sdc_disable_routing_multiplexer_outputs(const std::string& sdc_dir,
const bool& flatten_names,
const bool& include_time_stamp,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const ModuleManager& module_manager,

14
openfpga/src/fpga_sdc/sdc_writer_utils.cpp
View File

@ -24,20 +24,24 @@ namespace openfpga {
* Write a head (description) in SDC file
*******************************************************************/
void print_sdc_file_header(std::fstream& fp,
const std::string& usage) {
const std::string& usage,
const bool& include_time_stamp) {
valid_file_stream(fp);
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "#############################################" << std::endl;
fp << "#\tSynopsys Design Constraints (SDC)" << std::endl;
fp << "#\tFor FPGA fabric " << std::endl;
fp << "#\tDescription: " << usage << std::endl;
fp << "#\tAuthor: Xifan TANG " << std::endl;
fp << "#\tOrganization: University of Utah " << std::endl;
fp << "#\tDate: " << std::ctime(&end_time);
if (include_time_stamp) {
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "#\tDate: " << std::ctime(&end_time);
}
fp << "#############################################" << std::endl;
fp << std::endl;
}

3
openfpga/src/fpga_sdc/sdc_writer_utils.h
View File

@ -17,7 +17,8 @@
namespace openfpga {
void print_sdc_file_header(std::fstream& fp,
const std::string& usage);
const std::string& usage,
const bool& include_time_stamp);
void print_sdc_timescale(std::fstream& fp,
const std::string& timescale);

9
openfpga/src/fpga_verilog/fabric_verilog_options.cpp
View File

@ -19,6 +19,7 @@ FabricVerilogOption::FabricVerilogOption() {
compress_routing_ = false;
print_user_defined_template_ = false;
default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
time_stamp_ = true;
verbose_output_ = false;
}
@ -33,6 +34,10 @@ bool FabricVerilogOption::include_timing() const {
return include_timing_;
}
bool FabricVerilogOption::time_stamp() const {
return time_stamp_;
}
bool FabricVerilogOption::explicit_port_mapping() const {
return explicit_port_mapping_;
}
@ -64,6 +69,10 @@ void FabricVerilogOption::set_include_timing(const bool& enabled) {
include_timing_ = enabled;
}
void FabricVerilogOption::set_time_stamp(const bool& enabled) {
time_stamp_ = enabled;
}
void FabricVerilogOption::set_explicit_port_mapping(const bool& enabled) {
explicit_port_mapping_ = enabled;
}

3
openfpga/src/fpga_verilog/fabric_verilog_options.h
View File

@ -19,6 +19,7 @@ class FabricVerilogOption {
FabricVerilogOption();
public: /* Public accessors */
std::string output_directory() const;
bool time_stamp() const;
bool include_timing() const;
bool explicit_port_mapping() const;
bool compress_routing() const;
@ -27,6 +28,7 @@ class FabricVerilogOption {
bool verbose_output() const;
public: /* Public mutators */
void set_output_directory(const std::string& output_dir);
void set_time_stamp(const bool& enabled);
void set_include_timing(const bool& enabled);
void set_explicit_port_mapping(const bool& enabled);
void set_compress_routing(const bool& enabled);
@ -40,6 +42,7 @@ class FabricVerilogOption {
bool compress_routing_;
bool print_user_defined_template_;
e_verilog_default_net_type default_net_type_;
bool time_stamp_;
bool verbose_output_;
};

11
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -133,7 +133,8 @@ void fpga_fabric_verilog(ModuleManager &module_manager,
/* Generate an netlist including all the fabric-related netlists */
print_verilog_fabric_include_netlist(const_cast<const NetlistManager &>(netlist_manager),
src_dir_path,
circuit_lib);
circuit_lib,
options.time_stamp());
/* Given a brief stats on how many Verilog modules have been written to files */
VTR_LOGV(options.verbose_output(),
@ -193,9 +194,7 @@ int fpga_verilog_full_testbench(const ModuleManager &module_manager,
/* Generate a Verilog file including all the netlists that have been generated */
print_verilog_full_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path(),
options.no_self_checking());
options);
return status;
}
@ -284,9 +283,7 @@ int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager,
/* Generate a Verilog file including all the netlists that have been generated */
print_verilog_preconfigured_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path(),
options.no_self_checking());
options);
return status;
}

27
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
View File

@ -32,7 +32,8 @@ namespace openfpga {
*******************************************************************/
void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
const std::string& src_dir,
const CircuitLibrary& circuit_lib) {
const CircuitLibrary& circuit_lib,
const bool& include_time_stamp) {
std::string verilog_fname = src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME);
/* Create the file stream */
@ -43,7 +44,7 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Fabric Netlist Summary"));
print_verilog_file_header(fp, std::string("Fabric Netlist Summary"), include_time_stamp);
/* Print preprocessing flags */
print_verilog_comment(fp, std::string("------ Include defines: preproc flags -----"));
@ -96,10 +97,11 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
*******************************************************************/
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking) {
const VerilogTestbenchOption& options) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
std::string fabric_netlist_file = options.fabric_netlist_file_path();
std::string reference_benchmark_file = options.reference_benchmark_file_path();
bool no_self_checking = options.no_self_checking();
/* Create the file stream */
std::fstream fp;
@ -109,7 +111,7 @@ void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"));
print_verilog_file_header(fp, std::string("Netlist Summary"), options.time_stamp());
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
@ -142,10 +144,11 @@ void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
*******************************************************************/
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking) {
const VerilogTestbenchOption& options) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
std::string fabric_netlist_file = options.fabric_netlist_file_path();
std::string reference_benchmark_file = options.reference_benchmark_file_path();
bool no_self_checking = options.no_self_checking();
/* Create the file stream */
std::fstream fp;
@ -155,7 +158,7 @@ void print_verilog_preconfigured_testbench_include_netlists(const std::string& s
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"));
print_verilog_file_header(fp, std::string("Netlist Summary"), options.time_stamp());
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
@ -200,7 +203,9 @@ void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable features in FPGA Verilog modules"));
print_verilog_file_header(fp,
std::string("Preprocessing flags to enable/disable features in FPGA Verilog modules"),
fabric_verilog_opts.time_stamp());
/* To enable timing */
if (true == fabric_verilog_opts.include_timing()) {

11
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
View File

@ -19,19 +19,16 @@ namespace openfpga {
void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
const std::string& src_dir,
const CircuitLibrary& circuit_lib);
const CircuitLibrary& circuit_lib,
const bool& include_time_stamp);
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking);
const VerilogTestbenchOption& options);
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking);
const VerilogTestbenchOption& options);
void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
const FabricVerilogOption& fabric_verilog_opts);

14
openfpga/src/fpga_verilog/verilog_decoders.cpp
View File

@ -166,7 +166,7 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type) {
const FabricVerilogOption& options) {
std::string verilog_fname(submodule_dir + std::string(LOCAL_ENCODER_VERILOG_FILE_NAME));
/* Create the file stream */
@ -179,7 +179,7 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
VTR_LOG("Writing Verilog netlist for local decoders for multiplexers '%s'...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Local Decoders for Multiplexers");
print_verilog_file_header(fp, "Local Decoders for Multiplexers", options.time_stamp());
/* Create a library for local encoders with different sizes */
DecoderLibrary decoder_lib;
@ -214,7 +214,7 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
/* Generate Verilog modules for the found unique local encoders */
for (const auto& decoder : decoder_lib.decoders()) {
print_verilog_mux_local_decoder_module(fp, module_manager, decoder_lib, decoder, default_net_type);
print_verilog_mux_local_decoder_module(fp, module_manager, decoder_lib, decoder, options.default_net_type());
}
/* Close the file stream */
@ -648,7 +648,7 @@ void print_verilog_submodule_arch_decoders(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const DecoderLibrary& decoder_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type) {
const FabricVerilogOption& options) {
std::string verilog_fname(submodule_dir + std::string(ARCH_ENCODER_VERILOG_FILE_NAME));
/* Create the file stream */
@ -661,14 +661,14 @@ void print_verilog_submodule_arch_decoders(const ModuleManager& module_manager,
VTR_LOG("Writing Verilog netlist for configuration decoders '%s'...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Decoders for fabric configuration protocol ");
print_verilog_file_header(fp, "Decoders for fabric configuration protocol", options.time_stamp());
/* Generate Verilog modules for the found unique local encoders */
for (const auto& decoder : decoder_lib.decoders()) {
if (true == decoder_lib.use_data_in(decoder)) {
print_verilog_arch_decoder_with_data_in_module(fp, module_manager, decoder_lib, decoder, default_net_type);
print_verilog_arch_decoder_with_data_in_module(fp, module_manager, decoder_lib, decoder, options.default_net_type());
} else {
print_verilog_arch_decoder_module(fp, module_manager, decoder_lib, decoder, default_net_type);
print_verilog_arch_decoder_module(fp, module_manager, decoder_lib, decoder, options.default_net_type());
}
}

5
openfpga/src/fpga_verilog/verilog_decoders.h
View File

@ -15,6 +15,7 @@
#include "module_manager.h"
#include "netlist_manager.h"
#include "verilog_port_types.h"
#include "fabric_verilog_options.h"
/********************************************************************
* Function declaration
@ -28,13 +29,13 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type);
const FabricVerilogOption& options);
void print_verilog_submodule_arch_decoders(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const DecoderLibrary& decoder_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type);
const FabricVerilogOption& options);
} /* end namespace openfpga */

14
openfpga/src/fpga_verilog/verilog_essential_gates.cpp
View File

@ -505,7 +505,7 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const std::string& submodule_dir,
const CircuitLibrary& circuit_lib,
const e_verilog_default_net_type& default_net_type) {
const FabricVerilogOption& options) {
/* TODO: remove .bak when this part is completed and tested */
std::string verilog_fname = submodule_dir + std::string(ESSENTIALS_VERILOG_FILE_NAME);
@ -520,13 +520,13 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
VTR_LOG("Generating Verilog netlist '%s' for essential gates...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Essential gates");
print_verilog_file_header(fp, "Essential gates", options.time_stamp());
/* Print constant generators */
/* VDD */
print_verilog_constant_generator_module(module_manager, fp, 0, default_net_type);
print_verilog_constant_generator_module(module_manager, fp, 0, options.default_net_type());
/* GND */
print_verilog_constant_generator_module(module_manager, fp, 1, default_net_type);
print_verilog_constant_generator_module(module_manager, fp, 1, options.default_net_type());
for (const auto& circuit_model : circuit_lib.models()) {
/* By pass user-defined modules */
@ -534,15 +534,15 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
continue;
}
if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
print_verilog_invbuf_module(module_manager, fp, circuit_lib, circuit_model, default_net_type);
print_verilog_invbuf_module(module_manager, fp, circuit_lib, circuit_model, options.default_net_type());
continue;
}
if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) {
print_verilog_passgate_module(module_manager, fp, circuit_lib, circuit_model, default_net_type);
print_verilog_passgate_module(module_manager, fp, circuit_lib, circuit_model, options.default_net_type());
continue;
}
if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model)) {
print_verilog_gate_module(module_manager, fp, circuit_lib, circuit_model, default_net_type);
print_verilog_gate_module(module_manager, fp, circuit_lib, circuit_model, options.default_net_type());
continue;
}
}

3
openfpga/src/fpga_verilog/verilog_essential_gates.h
View File

@ -9,6 +9,7 @@
#include "module_manager.h"
#include "netlist_manager.h"
#include "verilog_port_types.h"
#include "fabric_verilog_options.h"
/********************************************************************
* Function declaration
@ -21,7 +22,7 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const std::string& submodule_dir,
const CircuitLibrary& circuit_lib,
const e_verilog_default_net_type& default_net_type);
const FabricVerilogOption& options);
} /* end namespace openfpga */

2
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -291,7 +291,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
/* Generate a brief description on the Verilog file*/
std::string title = std::string("FPGA Verilog Testbench for Formal Top-level netlist of Design: ") + circuit_name;
print_verilog_file_header(fp, title);
print_verilog_file_header(fp, title, options.time_stamp());
/* Preparation: find all the clock ports */
std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);

12
openfpga/src/fpga_verilog/verilog_grid.cpp
View File

@ -95,7 +95,9 @@ void print_verilog_primitive_block(NetlistManager& netlist_manager,
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for primitive pb_type: " + std::string(primitive_pb_graph_node->pb_type->name)));
print_verilog_file_header(fp,
std::string("Verilog modules for primitive pb_type: " + std::string(primitive_pb_graph_node->pb_type->name)),
options.time_stamp());
/* Generate the module name for this primitive pb_graph_node*/
std::string primitive_module_name = generate_physical_block_module_name(primitive_pb_graph_node->pb_type);
@ -207,7 +209,9 @@ void rec_print_verilog_logical_tile(NetlistManager& netlist_manager,
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for pb_type: " + std::string(physical_pb_type->name)));
print_verilog_file_header(fp,
std::string("Verilog modules for pb_type: " + std::string(physical_pb_type->name)),
options.time_stamp());
/* Generate the name of the Verilog module for this pb_type */
std::string pb_module_name = generate_physical_block_module_name(physical_pb_type);
@ -320,7 +324,9 @@ void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager,
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for physical tile: " + std::string(phy_block_type->name) + "]"));
print_verilog_file_header(fp,
std::string("Verilog modules for physical tile: " + std::string(phy_block_type->name) + "]"),
options.time_stamp());
/* Create a Verilog Module for the top-level physical block, and add to module manager */
std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_VERILOG_FILE_NAME_PREFIX), std::string(phy_block_type->name), is_io_type(phy_block_type), border_side);

2
openfpga/src/fpga_verilog/verilog_lut.cpp
View File

@ -47,7 +47,7 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
VTR_LOG("Writing Verilog netlist for LUTs '%s'...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Look-Up Tables");
print_verilog_file_header(fp, "Look-Up Tables", options.time_stamp());
/* Search for each LUT circuit model */
for (const auto& lut_model : circuit_lib.models()) {

2
openfpga/src/fpga_verilog/verilog_memory.cpp
View File

@ -116,7 +116,7 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
VTR_LOG("Writing Verilog netlist for memories '%s' ...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Memories used in FPGA");
print_verilog_file_header(fp, "Memories used in FPGA", options.time_stamp());
/* Create the memory circuits for the multiplexer */
for (auto mux : mux_lib.muxes()) {

4
openfpga/src/fpga_verilog/verilog_mux.cpp
View File

@ -1274,7 +1274,7 @@ void print_verilog_submodule_mux_primitives(ModuleManager& module_manager,
VTR_LOG("Writing Verilog netlist for Multiplexer primitives '%s' ...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Multiplexer primitives");
print_verilog_file_header(fp, "Multiplexer primitives", options.time_stamp());
/* Record if the branch module has been outputted
* since different sizes of routing multiplexers may share the same branch module
@ -1332,7 +1332,7 @@ void print_verilog_submodule_mux_top_modules(ModuleManager& module_manager,
VTR_LOG("Writing Verilog netlist for Multiplexers '%s' ...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Multiplexers");
print_verilog_file_header(fp, "Multiplexers", options.time_stamp());
/* Generate unique Verilog modules for the multiplexers */
for (auto mux : mux_lib.muxes()) {

2
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -436,7 +436,7 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
/* Generate a brief description on the Verilog file*/
std::string title = std::string("Verilog netlist for pre-configured FPGA fabric by design: ") + circuit_name;
print_verilog_file_header(fp, title);
print_verilog_file_header(fp, title, options.time_stamp());
print_verilog_default_net_type_declaration(fp,
options.default_net_type());

8
openfpga/src/fpga_verilog/verilog_routing.cpp
View File

@ -91,7 +91,9 @@ void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]"));
print_verilog_file_header(fp,
std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]"),
options.time_stamp());
/* Create a Verilog Module based on the circuit model, and add to module manager */
ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate));
@ -194,7 +196,9 @@ void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_mana
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]"));
print_verilog_file_header(fp,
std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]"),
options.time_stamp());
/* Create a Verilog Module based on the circuit model, and add to module manager */
ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate));

2
openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
View File

@ -51,7 +51,7 @@ void print_verilog_submodule_shift_register_banks(const ModuleManager& module_ma
VTR_LOG("Writing Verilog netlist for shift register banks '%s' ...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Shift register banks used in FPGA");
print_verilog_file_header(fp, "Shift register banks used in FPGA", options.time_stamp());
/* Create the memory circuits for the multiplexer */
for (const ModuleId& sr_module : blwl_sr_banks.bl_bank_unique_modules()) {

10
openfpga/src/fpga_verilog/verilog_submodule.cpp
View File

@ -51,14 +51,14 @@ void print_verilog_submodule(ModuleManager& module_manager,
netlist_manager,
submodule_dir,
circuit_lib,
fpga_verilog_opts.default_net_type());
fpga_verilog_opts);
/* Decoders for architecture */
print_verilog_submodule_arch_decoders(const_cast<const ModuleManager&>(module_manager),
netlist_manager,
decoder_lib,
submodule_dir,
fpga_verilog_opts.default_net_type());
fpga_verilog_opts);
/* Routing multiplexers */
/* NOTE: local decoders generation must go before the MUX generation!!!
@ -68,7 +68,7 @@ void print_verilog_submodule(ModuleManager& module_manager,
netlist_manager,
mux_lib, circuit_lib,
submodule_dir,
fpga_verilog_opts.default_net_type());
fpga_verilog_opts);
print_verilog_submodule_muxes(module_manager, netlist_manager, mux_lib, circuit_lib,
submodule_dir,
fpga_verilog_opts);
@ -84,7 +84,7 @@ void print_verilog_submodule(ModuleManager& module_manager,
print_verilog_submodule_wires(const_cast<const ModuleManager&>(module_manager),
netlist_manager, circuit_lib,
submodule_dir,
fpga_verilog_opts.default_net_type());
fpga_verilog_opts);
/* Memories */
print_verilog_submodule_memories(const_cast<const ModuleManager&>(module_manager),
@ -106,7 +106,7 @@ void print_verilog_submodule(ModuleManager& module_manager,
print_verilog_submodule_templates(const_cast<const ModuleManager&>(module_manager),
circuit_lib,
submodule_dir,
fpga_verilog_opts.default_net_type());
fpga_verilog_opts);
}
/* Create a header file to include all the subckts */

6
openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
View File

@ -174,7 +174,7 @@ void print_one_verilog_template_module(const ModuleManager& module_manager,
void print_verilog_submodule_templates(const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type) {
const FabricVerilogOption& options) {
std::string verilog_fname(submodule_dir + USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME);
/* Create the file stream */
@ -187,7 +187,7 @@ void print_verilog_submodule_templates(const ModuleManager& module_manager,
VTR_LOG("Creating template for user-defined Verilog modules '%s'...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Template for user-defined Verilog modules");
print_verilog_file_header(fp, "Template for user-defined Verilog modules", options.time_stamp());
/* Output essential models*/
for (const auto& model : circuit_lib.models()) {
@ -203,7 +203,7 @@ void print_verilog_submodule_templates(const ModuleManager& module_manager,
print_one_verilog_template_module(module_manager,
fp,
circuit_lib.model_name(model),
default_net_type);
options.default_net_type());
}
/* close file stream */

3
openfpga/src/fpga_verilog/verilog_submodule_utils.h
View File

@ -9,6 +9,7 @@
#include "module_manager.h"
#include "circuit_library.h"
#include "verilog_port_types.h"
#include "fabric_verilog_options.h"
/********************************************************************
* Function declaration
@ -27,7 +28,7 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager,
void print_verilog_submodule_templates(const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type);
const FabricVerilogOption& options);
} /* end namespace openfpga */

10
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
View File

@ -25,6 +25,7 @@ VerilogTestbenchOption::VerilogTestbenchOption() {
default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
time_unit_ = 1E-3;
time_stamp_ = true;
verbose_output_ = false;
}
@ -91,6 +92,10 @@ e_embedded_bitstream_hdl_type VerilogTestbenchOption::embedded_bitstream_hdl_typ
return embedded_bitstream_hdl_type_;
}
bool VerilogTestbenchOption::time_stamp() const {
return time_stamp_;
}
bool VerilogTestbenchOption::verbose_output() const {
return verbose_output_;
}
@ -186,6 +191,11 @@ void VerilogTestbenchOption::set_time_unit(const float& time_unit) {
time_unit_ = time_unit;
}
void VerilogTestbenchOption::set_time_stamp(const bool& enabled) {
time_stamp_ = enabled;
}
void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
verbose_output_ = enabled;
}

3
openfpga/src/fpga_verilog/verilog_testbench_options.h
View File

@ -47,6 +47,7 @@ class VerilogTestbenchOption {
e_verilog_default_net_type default_net_type() const;
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const;
float time_unit() const;
bool time_stamp() const;
bool verbose_output() const;
public: /* Public validator */
bool validate() const;
@ -73,6 +74,7 @@ class VerilogTestbenchOption {
void set_default_net_type(const std::string& default_net_type);
void set_time_unit(const float& time_unit);
void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type);
void set_time_stamp(const bool& enabled);
void set_verbose_output(const bool& enabled);
private: /* Internal Data */
std::string output_directory_;
@ -89,6 +91,7 @@ class VerilogTestbenchOption {
e_verilog_default_net_type default_net_type_;
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_;
float time_unit_;
bool time_stamp_;
bool verbose_output_;
};

4
openfpga/src/fpga_verilog/verilog_top_module.cpp
View File

@ -56,7 +56,9 @@ void print_verilog_top_module(NetlistManager& netlist_manager,
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Top-level Verilog module for FPGA"));
print_verilog_file_header(fp,
std::string("Top-level Verilog module for FPGA"),
options.time_stamp());
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp,

2
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -1928,7 +1928,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
/* Generate a brief description on the Verilog file*/
std::string title = std::string("FPGA Verilog full testbench for top-level netlist of design: ") + circuit_name;
print_verilog_file_header(fp, title);
print_verilog_file_header(fp, title, options.time_stamp());
/* Find the top_module */
ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name());

6
openfpga/src/fpga_verilog/verilog_wire.cpp
View File

@ -97,7 +97,7 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type) {
const FabricVerilogOption& options) {
std::string verilog_fname(submodule_dir + std::string(WIRES_VERILOG_FILE_NAME));
/* Create the file stream */
@ -110,7 +110,7 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
VTR_LOG("Writing Verilog netlist for wires '%s'...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Wires");
print_verilog_file_header(fp, "Wires", options.time_stamp());
/* Print Verilog models for regular wires*/
print_verilog_comment(fp, std::string("----- BEGIN Verilog modules for regular wires -----"));
@ -119,7 +119,7 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
if (!circuit_lib.model_verilog_netlist(model).empty()) {
continue;
}
print_verilog_wire_module(module_manager, circuit_lib, fp, model, default_net_type);
print_verilog_wire_module(module_manager, circuit_lib, fp, model, options.default_net_type());
}
print_verilog_comment(fp, std::string("----- END Verilog modules for regular wires -----"));

3
openfpga/src/fpga_verilog/verilog_wire.h
View File

@ -11,6 +11,7 @@
#include "module_manager.h"
#include "netlist_manager.h"
#include "verilog_port_types.h"
#include "fabric_verilog_options.h"
/********************************************************************
* Function declaration
@ -23,7 +24,7 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type);
const FabricVerilogOption& options);
} /* end namespace openfpga */

20
openfpga/src/fpga_verilog/verilog_writer_utils.cpp
View File

@ -43,19 +43,24 @@ void print_verilog_default_net_type_declaration(std::fstream& fp,
* include the description
***********************************************/
void print_verilog_file_header(std::fstream& fp,
const std::string& usage) {
const std::string& usage,
const bool& include_time_stamp) {
VTR_ASSERT(true == valid_file_stream(fp));
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "//-------------------------------------------" << std::endl;
fp << "//\tFPGA Synthesizable Verilog Netlist" << std::endl;
fp << "//\tDescription: " << usage << std::endl;
fp << "//\tAuthor: Xifan TANG" << std::endl;
fp << "//\tOrganization: University of Utah" << std::endl;
fp << "//\tDate: " << std::ctime(&end_time) ;
if (include_time_stamp) {
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "//\tDate: " << std::ctime(&end_time) ;
}
fp << "//-------------------------------------------" << std::endl;
fp << "//----- Time scale -----" << std::endl;
fp << "`timescale 1ns / 1ps" << std::endl;
fp << std::endl;
@ -1531,7 +1536,8 @@ void print_verilog_clock_stimuli(std::fstream& fp,
********************************************************************/
void print_verilog_netlist_include_header_file(const std::vector<std::string>& netlists_to_be_included,
const char* subckt_dir,
const char* header_file_name) {
const char* header_file_name,
const bool& include_time_stamp) {
std::string verilog_fname(std::string(subckt_dir) + std::string(header_file_name));
@ -1542,7 +1548,7 @@ void print_verilog_netlist_include_header_file(const std::vector<std::string>& n
VTR_ASSERT(true == valid_file_stream(fp));
/* Generate the descriptions*/
print_verilog_file_header(fp, "Header file to include other Verilog netlists");
print_verilog_file_header(fp, "Header file to include other Verilog netlists", include_time_stamp);
/* Output file names */
for (const std::string& netlist_name : netlists_to_be_included) {

6
openfpga/src/fpga_verilog/verilog_writer_utils.h
View File

@ -35,7 +35,8 @@ void print_verilog_default_net_type_declaration(std::fstream& fp,
const e_verilog_default_net_type& default_net_type);
void print_verilog_file_header(std::fstream& fp,
const std::string& usage);
const std::string& usage,
const bool& include_time_stamp);
void print_verilog_include_netlist(std::fstream& fp,
const std::string& netlist_name);
@ -201,7 +202,8 @@ void print_verilog_clock_stimuli(std::fstream& fp,
void print_verilog_netlist_include_header_file(const std::vector<std::string>& netlists_to_be_included,
const char* subckt_dir,
const char* header_file_name);
const char* header_file_name,
const bool& include_time_stamp);
} /* end namespace openfpga */

83
openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga Normal file
View File

@ -0,0 +1,83 @@
# !!! IMPRORTANT
# This script is designed to test the option --no_time_stamp in related commands
# It can NOT be used an example script to achieve other objectives
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file ${OPENFPGA_OUTPUT_DIR}/fabric_independent_bitstream.xml --no_time_stamp
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file ${OPENFPGA_OUTPUT_DIR}/fabric_bitstream.xml --format xml --no_time_stamp
write_fabric_bitstream --file ${OPENFPGA_OUTPUT_DIR}/fabric_bitstream.bit --format plain_text --no_time_stamp
write_io_mapping --file ${OPENFPGA_OUTPUT_DIR}/pin_mapping.xml --no_time_stamp
report_bitstream_distribution --file ${OPENFPGA_OUTPUT_DIR}/bitstream_distribution.xml --no_time_stamp
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --include_timing --print_user_defined_template --verbose --no_time_stamp
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --no_time_stamp
write_preconfigured_testbench --file ${OPENFPGA_OUTPUT_DIR} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --no_time_stamp
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ${OPENFPGA_OUTPUT_DIR} --no_time_stamp
# Write SDC to constrain timing of configuration chain
write_configuration_chain_sdc --file ${OPENFPGA_OUTPUT_DIR}/ccff_timing.sdc --time_unit ns --max_delay 5 --min_delay 2.5 --no_time_stamp
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ${OPENFPGA_OUTPUT_DIR}/disable_configure_ports.sdc --no_time_stamp
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ${OPENFPGA_OUTPUT_DIR} --no_time_stamp
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

75
openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_no_time_stamp_example_script.openfpga Normal file
View File

@ -0,0 +1,75 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
# Apply fix-up to clustering nets based on routing results
pb_pin_fixup --verbose
# Apply fix-up to Look-Up Table truth tables based on packing results
lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
write_fabric_hierarchy --file ./fabric_hierarchy.txt
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
# Strongly recommend it is done after all the fix-up have been applied
repack #--verbose
# Build the bitstream
# - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
# Build fabric-dependent bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose --no_time_stamp
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
# - Must specify the reference benchmark file if you want to output any testbenches
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --no_time_stamp
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --no_time_stamp
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit
# Note :
# To run verification at the end of the flow maintain source in ./SRC directory

14
openfpga_flow/regression_test_scripts/basic_reg_test.sh
View File

@ -10,6 +10,7 @@ echo -e "Basic regression tests";
echo -e "Testing configuration chain of a K4N4 FPGA";
run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
run-task basic_tests/full_testbench/configuration_chain_no_time_stamp --debug --show_thread_logs
run-task basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs
run-task basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs
run-task basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
@ -22,6 +23,7 @@ run-task basic_tests/full_testbench/fast_configuration_chain_use_set --debug --s
run-task basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs
run-task basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp --debug --show_thread_logs
echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
run-task basic_tests/full_testbench/configuration_frame --debug --show_thread_logs
@ -143,6 +145,18 @@ run-task basic_tests/verific_test --debug --show_thread_logs
echo -e "Testing explicit multi verilog files";
run-task basic_tests/explicit_multi_verilog_files --debug --show_thread_logs
echo -e "Testing output files without time stamp";
run-task basic_tests/no_time_stamp --debug --show_thread_logs
# Run git-diff to ensure no changes on the golden netlists
if git diff origin/main HEAD --name-status -- ':openfpga_flow/tasks/basic_tests/no_time_stamp/golden_output_no_time_stamp/**'; then
echo -e "Golden netlist remain unchanged"
else
echo -e "Detect changes in golden scripts"; exit 1;
fi
echo -e "Test the remove of runtime directories"
run-task basic_tests/explicit_multi_verilog_files --debug --show_thread_logs --remove_run_dir all
# Repgression test to test multi-user enviroment
cp -r */*/basic_tests/full_testbench/configuration_chain /tmp/
cd /tmp/ && run-task configuration_chain --debug --show_thread_logs

2
openfpga_flow/scripts/run_fpga_task.py
View File

@ -195,7 +195,6 @@ def generate_each_task_actions(taskname):
curr_run_dir = "run%03d" % (max(run_dirs+[0, ])+1)
if args.remove_run_dir:
remove_run_dir()
return
try:
os.mkdir(curr_run_dir)
if os.path.islink('latest') or os.path.exists('latest'):
@ -380,6 +379,7 @@ def generate_each_task_actions(taskname):
logger.info('Found %d Architectures %d Benchmarks & %d Script Parameters' %
(len(archfile_list), len(benchmark_list), len(ScriptSections)))
logger.info('Created total %d jobs' % len(flow_run_cmd_list))
return flow_run_cmd_list,GeneralSection
# Make the directory name unique by including the benchmark index in the list.

20
openfpga_flow/tasks/ci_tests/config/task.conf → openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_no_time_stamp/config/task.conf
View File

@ -14,27 +14,23 @@ spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
# Use a absolute path for the Verilog netlists to be generated
# This is designed to allow the test case 'basic_tests/generate_testbench'
# to use the Verilog netlists along with testbenches in HDL simulation
openfpga_verilog_output_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH
openfpga_vpr_device_layout=
openfpga_fast_configuration=--no_time_stamp
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:DESIGN_PATH}
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top =${PATH:DESIGN_TOP}
#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
bench0_top = and2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=

34
openfpga_flow/tasks/basic_tests/no_time_stamp/config/task.conf Normal file
View File

@ -0,0 +1,34 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

123
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v Normal file
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@ -0,0 +1,123 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: FPGA Verilog Testbench for Formal Top-level netlist of Design: and2
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
module and2_top_formal_verification_random_tb;
// ----- Default clock port is added here since benchmark does not contain one -------
reg [0:0] clk;
// ----- Shared inputs -------
reg [0:0] a;
reg [0:0] b;
// ----- FPGA fabric outputs -------
wire [0:0] out_c_gfpga;
// ----- Benchmark outputs -------
wire [0:0] out_c_bench;
// ----- Output vectors checking flags -------
reg [0:0] out_c_flag;
// ----- Error counter -------
integer nb_error= 0;
// ----- FPGA fabric instanciation -------
and2_top_formal_verification FPGA_DUT(
.a_fm(a),
.b_fm(b),
.out_c_fm(out_c_gfpga) );
// ----- End FPGA Fabric Instanication -------
// ----- Reference Benchmark Instanication -------
and2 REF_DUT(
.a(a),
.b(b),
.c(out_c_bench) );
// ----- End reference Benchmark Instanication -------
// ----- Clock 'clk' Initialization -------
initial begin
clk[0] <= 1'b0;
while(1) begin
#0.4537859857
clk[0] <= !clk[0];
end
end
// ----- Begin reset signal generation -----
// ----- End reset signal generation -----
// ----- Input Initialization -------
initial begin
a <= 1'b0;
b <= 1'b0;
out_c_flag[0] <= 1'b0;
end
// ----- Input Stimulus -------
always@(negedge clk[0]) begin
a <= $random;
b <= $random;
end
// ----- Begin checking output vectors -------
// ----- Skip the first falling edge of clock, it is for initialization -------
reg [0:0] sim_start;
always@(negedge clk[0]) begin
if (1'b1 == sim_start[0]) begin
sim_start[0] <= ~sim_start[0];
end else begin
if(!(out_c_gfpga === out_c_bench) && !(out_c_bench === 1'bx)) begin
out_c_flag <= 1'b1;
end else begin
out_c_flag<= 1'b0;
end
end
end
always@(posedge out_c_flag) begin
if(out_c_flag) begin
nb_error = nb_error + 1;
$display("Mismatch on out_c_gfpga at time = %t", $realtime);
end
end
// ----- Begin output waveform to VCD file-------
initial begin
$dumpfile("and2_formal.vcd");
$dumpvars(1, and2_top_formal_verification_random_tb);
end
// ----- END output waveform to VCD file -------
initial begin
sim_start[0] <= 1'b1;
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
#6.353003979
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
$display("Simulation Failed with %d error(s)", nb_error);
end
$finish;
end
endmodule
// ----- END Verilog module for and2_top_formal_verification_random_tb -----
//----- Default net type -----
`default_nettype none

1829
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc Normal file
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File diff suppressed because it is too large Load Diff

16
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_include_netlists.v Normal file
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@ -0,0 +1,16 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include fabric top-level netlists -----
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_netlists.v"
`include "and2_output_verilog.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_top_formal_verification.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v"

502
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_top_formal_verification.v Normal file
View File

@ -0,0 +1,502 @@
//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog netlist for pre-configured FPGA fabric by design: and2
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
module and2_top_formal_verification (
input [0:0] a_fm,
input [0:0] b_fm,
output [0:0] out_c_fm);
// ----- Local wires for FPGA fabric -----
wire [0:31] gfpga_pad_GPIO_PAD;
wire [0:0] ccff_head;
wire [0:0] ccff_tail;
wire [0:0] prog_clk;
wire [0:0] set;
wire [0:0] reset;
wire [0:0] clk;
// ----- FPGA top-level module to be capsulated -----
fpga_top U0_formal_verification (
.prog_clk(prog_clk[0]),
.set(set[0]),
.reset(reset[0]),
.clk(clk[0]),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0:31]),
.ccff_head(ccff_head[0]),
.ccff_tail(ccff_tail[0]));
// ----- Begin Connect Global ports of FPGA top module -----
assign set[0] = 1'b0;
assign reset[0] = 1'b0;
assign clk[0] = 1'b0;
assign prog_clk[0] = 1'b0;
// ----- End Connect Global ports of FPGA top module -----
// ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[6] -----
assign gfpga_pad_GPIO_PAD[6] = a_fm[0];
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[1] -----
assign gfpga_pad_GPIO_PAD[1] = b_fm[0];
// ----- Blif Benchmark output out_c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD[9] -----
assign out_c_fm[0] = gfpga_pad_GPIO_PAD[9];
// ----- Wire unused FPGA I/Os to constants -----
assign gfpga_pad_GPIO_PAD[0] = 1'b0;
assign gfpga_pad_GPIO_PAD[2] = 1'b0;
assign gfpga_pad_GPIO_PAD[3] = 1'b0;
assign gfpga_pad_GPIO_PAD[4] = 1'b0;
assign gfpga_pad_GPIO_PAD[5] = 1'b0;
assign gfpga_pad_GPIO_PAD[7] = 1'b0;
assign gfpga_pad_GPIO_PAD[8] = 1'b0;
assign gfpga_pad_GPIO_PAD[10] = 1'b0;
assign gfpga_pad_GPIO_PAD[11] = 1'b0;
assign gfpga_pad_GPIO_PAD[12] = 1'b0;
assign gfpga_pad_GPIO_PAD[13] = 1'b0;
assign gfpga_pad_GPIO_PAD[14] = 1'b0;
assign gfpga_pad_GPIO_PAD[15] = 1'b0;
assign gfpga_pad_GPIO_PAD[16] = 1'b0;
assign gfpga_pad_GPIO_PAD[17] = 1'b0;
assign gfpga_pad_GPIO_PAD[18] = 1'b0;
assign gfpga_pad_GPIO_PAD[19] = 1'b0;
assign gfpga_pad_GPIO_PAD[20] = 1'b0;
assign gfpga_pad_GPIO_PAD[21] = 1'b0;
assign gfpga_pad_GPIO_PAD[22] = 1'b0;
assign gfpga_pad_GPIO_PAD[23] = 1'b0;
assign gfpga_pad_GPIO_PAD[24] = 1'b0;
assign gfpga_pad_GPIO_PAD[25] = 1'b0;
assign gfpga_pad_GPIO_PAD[26] = 1'b0;
assign gfpga_pad_GPIO_PAD[27] = 1'b0;
assign gfpga_pad_GPIO_PAD[28] = 1'b0;
assign gfpga_pad_GPIO_PAD[29] = 1'b0;
assign gfpga_pad_GPIO_PAD[30] = 1'b0;
assign gfpga_pad_GPIO_PAD[31] = 1'b0;
// ----- Begin load bitstream to configuration memories -----
// ----- Begin assign bitstream to configuration memories -----
initial begin
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = {16{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = {16{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_out[0:15] = 16'b1010101000000000;
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0.lut4_DFF_mem.mem_outb[0:15] = 16'b0101010111111111;
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_out[0:1] = 2'b01;
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0.mem_ble4_out_0.mem_outb[0:1] = 2'b10;
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_0.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_1.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_2.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_3.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_0_in_3.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_0.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_0.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_1.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_2.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_3.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_1_in_3.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_0.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_0.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_1.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b0011;
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b1100;
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = {4{1'b0}};
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_bottom_1__0_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_12.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_12.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_22.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_24.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_13.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_13.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_15.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_15.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_19.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_21.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_23.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_7.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_7.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_13.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_13.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_13.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_13.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_15.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_15.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_19.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_21.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_23.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:1] = 2'b10;
force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:1] = 2'b01;
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_6.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_6.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__0_.mem_top_ipin_7.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_3.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_4.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_5.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = 3'b010;
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = 3'b101;
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_3.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_3.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_4.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_4.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_5.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_5.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_6.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_6.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_7.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_outb[0:2] = {3{1'b1}};
end
// ----- End assign bitstream to configuration memories -----
// ----- End load bitstream to configuration memories -----
endmodule
// ----- END Verilog module for and2_top_formal_verification -----
//----- Default net type -----
`default_nettype none

33
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/bitstream_distribution.xml Normal file
View File

@ -0,0 +1,33 @@
<!--
- Report Architecture Bitstream Distribution
- Version: 1.0.3764-dev+dd400579-dirty
-->
<block name="fpga_top" number_of_bits="527">
<block name="grid_clb_1__1_" number_of_bits="136">
</block>
<block name="grid_io_top_1__2_" number_of_bits="8">
</block>
<block name="grid_io_right_2__1_" number_of_bits="8">
</block>
<block name="grid_io_bottom_1__0_" number_of_bits="8">
</block>
<block name="grid_io_left_0__1_" number_of_bits="8">
</block>
<block name="sb_0__0_" number_of_bits="58">
</block>
<block name="sb_0__1_" number_of_bits="57">
</block>
<block name="sb_1__0_" number_of_bits="59">
</block>
<block name="sb_1__1_" number_of_bits="56">
</block>
<block name="cbx_1__0_" number_of_bits="33">
</block>
<block name="cbx_1__1_" number_of_bits="33">
</block>
<block name="cby_0__1_" number_of_bits="30">
</block>
<block name="cby_1__1_" number_of_bits="33">
</block>
</block>

105
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/cbx_1__0_.sdc Normal file
View File

@ -0,0 +1,105 @@
#############################################
# Synopsys Design Constraints (SDC)
# For FPGA fabric
# Description: Constrain timing of Connection Block cbx_1__0_ for PnR
# Author: Xifan TANG
# Organization: University of Utah
#############################################
#############################################
# Define time unit
#############################################
set_units -time s
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11

105
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/cbx_1__1_.sdc Normal file
View File

@ -0,0 +1,105 @@
#############################################
# Synopsys Design Constraints (SDC)
# For FPGA fabric
# Description: Constrain timing of Connection Block cbx_1__1_ for PnR
# Author: Xifan TANG
# Organization: University of Utah
#############################################
#############################################
# Define time unit
#############################################
set_units -time s
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11

99
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/cby_0__1_.sdc Normal file
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@ -0,0 +1,99 @@
#############################################
# Synopsys Design Constraints (SDC)
# For FPGA fabric
# Description: Constrain timing of Connection Block cby_0__1_ for PnR
# Author: Xifan TANG
# Organization: University of Utah
#############################################
#############################################
# Define time unit
#############################################
set_units -time s
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11

105
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/cby_1__1_.sdc Normal file
View File

@ -0,0 +1,105 @@
#############################################
# Synopsys Design Constraints (SDC)
# For FPGA fabric
# Description: Constrain timing of Connection Block cby_1__1_ for PnR
# Author: Xifan TANG
# Organization: University of Utah
#############################################
#############################################
# Define time unit
#############################################
set_units -time s
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11
set_max_delay -from fpga_top/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] 7.247000222e-11

1065
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/ccff_timing.sdc Normal file
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File diff suppressed because it is too large Load Diff

86
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc Normal file
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@ -0,0 +1,86 @@
#############################################
# Synopsys Design Constraints (SDC)
# For FPGA fabric
# Description: Disable configurable memory outputs for PnR
# Author: Xifan TANG
# Organization: University of Utah
#############################################
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mem_ble*_out_*/DFF_*_/Q
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mem_ble*_out_*/DFF_*_/QN
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/Q
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN

82
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/disable_configure_ports.sdc Normal file
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#############################################
# Synopsys Design Constraints (SDC)
# For FPGA fabric
# Description: Disable configuration outputs of all the programmable cells for PnR
# Author: Xifan TANG
# Organization: University of Utah
#############################################
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_*_/sram
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_mode_default__lut*_*/lut*_*_/sram_inv
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram_inv
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram_inv
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/sram_inv
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/sram_inv
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram_inv
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram_inv
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/sram_inv
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mux_ble*_out_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mux_ble*_out_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/sram_inv
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/sram_inv
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/sram
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/sram_inv
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_*_/DIR

42
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/disable_routing_multiplexer_outputs.sdc Normal file
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#############################################
# Synopsys Design Constraints (SDC)
# For FPGA fabric
# Description: Disable routing multiplexer outputs for PnR
# Author: Xifan TANG
# Organization: University of Utah
#############################################
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/out
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/out
set_disable_timing fpga_top/cbx_*__*_/mux_bottom_ipin_*/out
set_disable_timing fpga_top/cbx_*__*_/mux_top_ipin_*/out
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/out
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/out
set_disable_timing fpga_top/cby_*__*_/mux_left_ipin_*/out
set_disable_timing fpga_top/cby_*__*_/mux_right_ipin_*/out
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_n*_lut*__ble*_*/mux_ble*_out_*/out
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_right_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_top_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_bottom_track_*/out
set_disable_timing fpga_top/sb_*__*_/mux_left_track_*/out
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mux_fle_*_in_*/out

32
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/disable_sb_outputs.sdc Normal file
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#############################################
# Synopsys Design Constraints (SDC)
# For FPGA fabric
# Description: Disable Switch Block outputs for PnR
# Author: Xifan TANG
# Organization: University of Utah
#############################################
set_disable_timing fpga_top/sb_*__*_/chany_top_out
set_disable_timing fpga_top/sb_*__*_/chanx_right_out
set_disable_timing fpga_top/sb_*__*_/ccff_tail
set_disable_timing fpga_top/sb_*__*_/chanx_right_out
set_disable_timing fpga_top/sb_*__*_/chany_bottom_out
set_disable_timing fpga_top/sb_*__*_/ccff_tail
set_disable_timing fpga_top/sb_*__*_/chany_top_out
set_disable_timing fpga_top/sb_*__*_/chanx_left_out
set_disable_timing fpga_top/sb_*__*_/ccff_tail
set_disable_timing fpga_top/sb_*__*_/chany_bottom_out
set_disable_timing fpga_top/sb_*__*_/chanx_left_out
set_disable_timing fpga_top/sb_*__*_/ccff_tail

531
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_bitstream.bit Normal file
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// Fabric bitstream
// Version: 1.0.3764-dev+dd400579-dirty
// Bitstream length: 527
// Bitstream width (LSB -> MSB): 1
1
1
1
1
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openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_bitstream.xml Normal file
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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Fabric Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include defines: preproc flags -----
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fpga_defines.v"
// ------ Include user-defined netlists -----
`include "/home/tangxifan/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/gpio.v"
// ------ Include primitive module netlists -----
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/arch_encoder.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/local_encoder.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/mux_primitives.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/muxes.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/luts.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/wires.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/memories.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v"
// ------ Include logic block netlists -----
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_top.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_right.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_bottom.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_left.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_clb.v"
// ------ Include routing module netlists -----
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_0__0_.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_0__1_.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_1__0_.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_1__1_.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cbx_1__0_.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cbx_1__1_.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cby_0__1_.v"
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cby_1__1_.v"
// ------ Include fabric top-level netlists -----
`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fpga_top.v"

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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Preprocessing flags to enable/disable features in FPGA Verilog modules
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
`define ENABLE_TIMING 1

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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Top-level Verilog module for FPGA
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
// ----- Verilog module for fpga_top -----
module fpga_top(prog_clk,
set,
reset,
clk,
gfpga_pad_GPIO_PAD,
ccff_head,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- GPIO PORTS -----
inout [0:31] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_;
wire [0:0] cbx_1__0__0_ccff_tail;
wire [0:12] cbx_1__0__0_chanx_left_out;
wire [0:12] cbx_1__0__0_chanx_right_out;
wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_;
wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_;
wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_;
wire [0:0] cbx_1__1__0_ccff_tail;
wire [0:12] cbx_1__1__0_chanx_left_out;
wire [0:12] cbx_1__1__0_chanx_right_out;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_;
wire [0:0] cby_0__1__0_ccff_tail;
wire [0:12] cby_0__1__0_chany_bottom_out;
wire [0:12] cby_0__1__0_chany_top_out;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_;
wire [0:0] cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_;
wire [0:0] cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_;
wire [0:0] cby_1__1__0_ccff_tail;
wire [0:12] cby_1__1__0_chany_bottom_out;
wire [0:12] cby_1__1__0_chany_top_out;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_;
wire [0:0] grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_;
wire [0:0] grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_;
wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_;
wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_;
wire [0:0] grid_io_bottom_0_ccff_tail;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_;
wire [0:0] grid_io_left_0_ccff_tail;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_;
wire [0:0] grid_io_right_0_ccff_tail;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
wire [0:0] grid_io_top_0_ccff_tail;
wire [0:0] sb_0__0__0_ccff_tail;
wire [0:12] sb_0__0__0_chanx_right_out;
wire [0:12] sb_0__0__0_chany_top_out;
wire [0:0] sb_0__1__0_ccff_tail;
wire [0:12] sb_0__1__0_chanx_right_out;
wire [0:12] sb_0__1__0_chany_bottom_out;
wire [0:0] sb_1__0__0_ccff_tail;
wire [0:12] sb_1__0__0_chanx_left_out;
wire [0:12] sb_1__0__0_chany_top_out;
wire [0:0] sb_1__1__0_ccff_tail;
wire [0:12] sb_1__1__0_chanx_left_out;
wire [0:12] sb_1__1__0_chany_bottom_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
grid_clb grid_clb_1__1_ (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.top_width_0_height_0_subtile_0__pin_I_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_),
.top_width_0_height_0_subtile_0__pin_I_4_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_),
.top_width_0_height_0_subtile_0__pin_I_8_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_),
.right_width_0_height_0_subtile_0__pin_I_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_),
.right_width_0_height_0_subtile_0__pin_I_5_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_),
.right_width_0_height_0_subtile_0__pin_I_9_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_),
.bottom_width_0_height_0_subtile_0__pin_I_2_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_),
.bottom_width_0_height_0_subtile_0__pin_I_6_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_),
.bottom_width_0_height_0_subtile_0__pin_clk_0_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_),
.left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
.left_width_0_height_0_subtile_0__pin_I_7_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_),
.ccff_head(cby_1__1__0_ccff_tail),
.top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_),
.bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_),
.ccff_tail(ccff_tail));
grid_io_top grid_io_top_1__2_ (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0:7]),
.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_),
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__1__0_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
.bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(grid_io_top_0_ccff_tail));
grid_io_right grid_io_right_2__1_ (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[8:15]),
.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
.left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
.left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_),
.left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_),
.left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_),
.left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(grid_io_bottom_0_ccff_tail),
.left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
.left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
.left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
.left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
.left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
.left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
.left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
.left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(grid_io_right_0_ccff_tail));
grid_io_bottom grid_io_bottom_1__0_ (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[16:23]),
.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
.top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
.top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_),
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(ccff_head),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
.top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
.top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
.top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(grid_io_bottom_0_ccff_tail));
grid_io_left grid_io_left_0__1_ (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[24:31]),
.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
.right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
.right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
.right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_),
.right_width_0_height_0_subtile_4__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_),
.right_width_0_height_0_subtile_5__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_),
.right_width_0_height_0_subtile_6__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_),
.right_width_0_height_0_subtile_7__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cby_0__1__0_ccff_tail),
.right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
.right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_),
.right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_),
.right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_),
.right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_),
.right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_),
.right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_),
.right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(grid_io_left_0_ccff_tail));
sb_0__0_ sb_0__0_ (
.prog_clk(prog_clk),
.chany_top_in(cby_0__1__0_chany_bottom_out[0:12]),
.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_),
.chanx_right_in(cbx_1__0__0_chanx_left_out[0:12]),
.right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(sb_0__1__0_ccff_tail),
.chany_top_out(sb_0__0__0_chany_top_out[0:12]),
.chanx_right_out(sb_0__0__0_chanx_right_out[0:12]),
.ccff_tail(sb_0__0__0_ccff_tail));
sb_0__1_ sb_0__1_ (
.prog_clk(prog_clk),
.chanx_right_in(cbx_1__1__0_chanx_left_out[0:12]),
.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.chany_bottom_in(cby_0__1__0_chany_top_out[0:12]),
.bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_top_0_ccff_tail),
.chanx_right_out(sb_0__1__0_chanx_right_out[0:12]),
.chany_bottom_out(sb_0__1__0_chany_bottom_out[0:12]),
.ccff_tail(sb_0__1__0_ccff_tail));
sb_1__0_ sb_1__0_ (
.prog_clk(prog_clk),
.chany_top_in(cby_1__1__0_chany_bottom_out[0:12]),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_),
.top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
.chanx_left_in(cbx_1__0__0_chanx_right_out[0:12]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_0_ccff_tail),
.chany_top_out(sb_1__0__0_chany_top_out[0:12]),
.chanx_left_out(sb_1__0__0_chanx_left_out[0:12]),
.ccff_tail(sb_1__0__0_ccff_tail));
sb_1__1_ sb_1__1_ (
.prog_clk(prog_clk),
.chany_bottom_in(cby_1__1__0_chany_top_out[0:12]),
.bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_),
.chanx_left_in(cbx_1__1__0_chanx_right_out[0:12]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_right_0_ccff_tail),
.chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]),
.chanx_left_out(sb_1__1__0_chanx_left_out[0:12]),
.ccff_tail(sb_1__1__0_ccff_tail));
cbx_1__0_ cbx_1__0_ (
.prog_clk(prog_clk),
.chanx_left_in(sb_0__0__0_chanx_right_out[0:12]),
.chanx_right_in(sb_1__0__0_chanx_left_out[0:12]),
.ccff_head(sb_1__0__0_ccff_tail),
.chanx_left_out(cbx_1__0__0_chanx_left_out[0:12]),
.chanx_right_out(cbx_1__0__0_chanx_right_out[0:12]),
.top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_),
.top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_),
.top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_tail(cbx_1__0__0_ccff_tail));
cbx_1__1_ cbx_1__1_ (
.prog_clk(prog_clk),
.chanx_left_in(sb_0__1__0_chanx_right_out[0:12]),
.chanx_right_in(sb_1__1__0_chanx_left_out[0:12]),
.ccff_head(sb_1__1__0_ccff_tail),
.chanx_left_out(cbx_1__1__0_chanx_left_out[0:12]),
.chanx_right_out(cbx_1__1__0_chanx_right_out[0:12]),
.top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_),
.ccff_tail(cbx_1__1__0_ccff_tail));
cby_0__1_ cby_0__1_ (
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__0__0_chany_top_out[0:12]),
.chany_top_in(sb_0__1__0_chany_bottom_out[0:12]),
.ccff_head(sb_0__0__0_ccff_tail),
.chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]),
.chany_top_out(cby_0__1__0_chany_top_out[0:12]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
.right_grid_left_width_0_height_0_subtile_0__pin_I_7_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_),
.left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_tail(cby_0__1__0_ccff_tail));
cby_1__1_ cby_1__1_ (
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__0_chany_top_out[0:12]),
.chany_top_in(sb_1__1__0_chany_bottom_out[0:12]),
.ccff_head(cbx_1__0__0_ccff_tail),
.chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]),
.chany_top_out(cby_1__1__0_chany_top_out[0:12]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I_5_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_),
.left_grid_right_width_0_height_0_subtile_0__pin_I_9_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_),
.ccff_tail(cby_1__1__0_ccff_tail));
endmodule
// ----- END Verilog module for fpga_top -----
//----- Default net type -----
`default_nettype none

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#############################################
# Synopsys Design Constraints (SDC)
# For FPGA fabric
# Description: Clock contraints for PnR
# Author: Xifan TANG
# Organization: University of Utah
#############################################
#############################################
# Define time unit
#############################################
set_units -time s
##################################################
# Create clock
##################################################
create_clock -name clk[0] -period 9.07571962e-10 -waveform {0 4.53785981e-10} [get_ports {clk[0]}]
##################################################
# Create programmable clock
##################################################
create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}]

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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for physical tile: clb]
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_clb -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for grid_clb -----
module grid_clb(prog_clk,
set,
reset,
clk,
top_width_0_height_0_subtile_0__pin_I_0_,
top_width_0_height_0_subtile_0__pin_I_4_,
top_width_0_height_0_subtile_0__pin_I_8_,
right_width_0_height_0_subtile_0__pin_I_1_,
right_width_0_height_0_subtile_0__pin_I_5_,
right_width_0_height_0_subtile_0__pin_I_9_,
bottom_width_0_height_0_subtile_0__pin_I_2_,
bottom_width_0_height_0_subtile_0__pin_I_6_,
bottom_width_0_height_0_subtile_0__pin_clk_0_,
left_width_0_height_0_subtile_0__pin_I_3_,
left_width_0_height_0_subtile_0__pin_I_7_,
ccff_head,
top_width_0_height_0_subtile_0__pin_O_2_,
right_width_0_height_0_subtile_0__pin_O_3_,
bottom_width_0_height_0_subtile_0__pin_O_0_,
left_width_0_height_0_subtile_0__pin_O_1_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I_4_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I_8_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I_1_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I_5_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I_9_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_2_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_6_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_clk_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_0__pin_I_3_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_0__pin_I_7_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_O_2_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_3_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_O_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_0__pin_O_1_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.clb_I({top_width_0_height_0_subtile_0__pin_I_0_, right_width_0_height_0_subtile_0__pin_I_1_, bottom_width_0_height_0_subtile_0__pin_I_2_, left_width_0_height_0_subtile_0__pin_I_3_, top_width_0_height_0_subtile_0__pin_I_4_, right_width_0_height_0_subtile_0__pin_I_5_, bottom_width_0_height_0_subtile_0__pin_I_6_, left_width_0_height_0_subtile_0__pin_I_7_, top_width_0_height_0_subtile_0__pin_I_8_, right_width_0_height_0_subtile_0__pin_I_9_}),
.clb_clk(bottom_width_0_height_0_subtile_0__pin_clk_0_),
.ccff_head(ccff_head),
.clb_O({bottom_width_0_height_0_subtile_0__pin_O_0_, left_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, right_width_0_height_0_subtile_0__pin_O_3_}),
.ccff_tail(ccff_tail));
endmodule
// ----- END Verilog module for grid_clb -----
//----- Default net type -----
`default_nettype none
// ----- END Grid Verilog module: grid_clb -----

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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for physical tile: io]
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_bottom -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for grid_io_bottom -----
module grid_io_bottom(prog_clk,
gfpga_pad_GPIO_PAD,
top_width_0_height_0_subtile_0__pin_outpad_0_,
top_width_0_height_0_subtile_1__pin_outpad_0_,
top_width_0_height_0_subtile_2__pin_outpad_0_,
top_width_0_height_0_subtile_3__pin_outpad_0_,
top_width_0_height_0_subtile_4__pin_outpad_0_,
top_width_0_height_0_subtile_5__pin_outpad_0_,
top_width_0_height_0_subtile_6__pin_outpad_0_,
top_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_head,
top_width_0_height_0_subtile_0__pin_inpad_0_,
top_width_0_height_0_subtile_1__pin_inpad_0_,
top_width_0_height_0_subtile_2__pin_inpad_0_,
top_width_0_height_0_subtile_3__pin_inpad_0_,
top_width_0_height_0_subtile_4__pin_inpad_0_,
top_width_0_height_0_subtile_5__pin_inpad_0_,
top_width_0_height_0_subtile_6__pin_inpad_0_,
top_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIO PORTS -----
inout [0:7] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_4__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_5__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_6__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_7__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
.io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
.io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
.io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
.io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
.io_outpad(top_width_0_height_0_subtile_4__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_4__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
.io_outpad(top_width_0_height_0_subtile_5__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_5__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
.io_outpad(top_width_0_height_0_subtile_6__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_6__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
.io_outpad(top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule
// ----- END Verilog module for grid_io_bottom -----
//----- Default net type -----
`default_nettype none
// ----- END Grid Verilog module: grid_io_bottom -----

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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for physical tile: io]
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_left -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for grid_io_left -----
module grid_io_left(prog_clk,
gfpga_pad_GPIO_PAD,
right_width_0_height_0_subtile_0__pin_outpad_0_,
right_width_0_height_0_subtile_1__pin_outpad_0_,
right_width_0_height_0_subtile_2__pin_outpad_0_,
right_width_0_height_0_subtile_3__pin_outpad_0_,
right_width_0_height_0_subtile_4__pin_outpad_0_,
right_width_0_height_0_subtile_5__pin_outpad_0_,
right_width_0_height_0_subtile_6__pin_outpad_0_,
right_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_head,
right_width_0_height_0_subtile_0__pin_inpad_0_,
right_width_0_height_0_subtile_1__pin_inpad_0_,
right_width_0_height_0_subtile_2__pin_inpad_0_,
right_width_0_height_0_subtile_3__pin_inpad_0_,
right_width_0_height_0_subtile_4__pin_inpad_0_,
right_width_0_height_0_subtile_5__pin_inpad_0_,
right_width_0_height_0_subtile_6__pin_inpad_0_,
right_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIO PORTS -----
inout [0:7] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_4__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_5__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_6__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_7__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_4__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_5__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_6__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_7__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
.io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
.io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
.io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
.io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
.io_outpad(right_width_0_height_0_subtile_4__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_4__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
.io_outpad(right_width_0_height_0_subtile_5__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_5__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
.io_outpad(right_width_0_height_0_subtile_6__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_6__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
.io_outpad(right_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule
// ----- END Verilog module for grid_io_left -----
//----- Default net type -----
`default_nettype none
// ----- END Grid Verilog module: grid_io_left -----

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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for physical tile: io]
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_right -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for grid_io_right -----
module grid_io_right(prog_clk,
gfpga_pad_GPIO_PAD,
left_width_0_height_0_subtile_0__pin_outpad_0_,
left_width_0_height_0_subtile_1__pin_outpad_0_,
left_width_0_height_0_subtile_2__pin_outpad_0_,
left_width_0_height_0_subtile_3__pin_outpad_0_,
left_width_0_height_0_subtile_4__pin_outpad_0_,
left_width_0_height_0_subtile_5__pin_outpad_0_,
left_width_0_height_0_subtile_6__pin_outpad_0_,
left_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_head,
left_width_0_height_0_subtile_0__pin_inpad_0_,
left_width_0_height_0_subtile_1__pin_inpad_0_,
left_width_0_height_0_subtile_2__pin_inpad_0_,
left_width_0_height_0_subtile_3__pin_inpad_0_,
left_width_0_height_0_subtile_4__pin_inpad_0_,
left_width_0_height_0_subtile_5__pin_inpad_0_,
left_width_0_height_0_subtile_6__pin_inpad_0_,
left_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIO PORTS -----
inout [0:7] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_4__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_5__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_6__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_7__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
.io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
.io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
.io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
.io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
.io_outpad(left_width_0_height_0_subtile_4__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_4__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
.io_outpad(left_width_0_height_0_subtile_5__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_5__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
.io_outpad(left_width_0_height_0_subtile_6__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_6__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
.io_outpad(left_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule
// ----- END Verilog module for grid_io_right -----
//----- Default net type -----
`default_nettype none
// ----- END Grid Verilog module: grid_io_right -----

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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for physical tile: io]
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_top -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for grid_io_top -----
module grid_io_top(prog_clk,
gfpga_pad_GPIO_PAD,
bottom_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_width_0_height_0_subtile_2__pin_outpad_0_,
bottom_width_0_height_0_subtile_3__pin_outpad_0_,
bottom_width_0_height_0_subtile_4__pin_outpad_0_,
bottom_width_0_height_0_subtile_5__pin_outpad_0_,
bottom_width_0_height_0_subtile_6__pin_outpad_0_,
bottom_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_head,
bottom_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIO PORTS -----
inout [0:7] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_4__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_5__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_6__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_7__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
.io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
.io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
.io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
.io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
.io_outpad(bottom_width_0_height_0_subtile_4__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_4__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
.io_outpad(bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
.io_outpad(bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
.io_outpad(bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule
// ----- END Verilog module for grid_io_top -----
//----- Default net type -----
`default_nettype none
// ----- END Grid Verilog module: grid_io_top -----

427
openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v Normal file
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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Verilog modules for pb_type: clb
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: clb -----
//----- Default net type -----
`default_nettype none
// ----- Verilog module for logical_tile_clb_mode_clb_ -----
module logical_tile_clb_mode_clb_(prog_clk,
set,
reset,
clk,
clb_I,
clb_clk,
ccff_head,
clb_O,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- INPUT PORTS -----
input [0:9] clb_I;
//----- INPUT PORTS -----
input [0:0] clb_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:3] clb_O;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:9] clb_I;
wire [0:0] clb_clk;
wire [0:3] clb_O;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_out;
wire [0:0] mux_tree_size14_0_out;
wire [0:3] mux_tree_size14_0_sram;
wire [0:3] mux_tree_size14_0_sram_inv;
wire [0:0] mux_tree_size14_10_out;
wire [0:3] mux_tree_size14_10_sram;
wire [0:3] mux_tree_size14_10_sram_inv;
wire [0:0] mux_tree_size14_11_out;
wire [0:3] mux_tree_size14_11_sram;
wire [0:3] mux_tree_size14_11_sram_inv;
wire [0:0] mux_tree_size14_12_out;
wire [0:3] mux_tree_size14_12_sram;
wire [0:3] mux_tree_size14_12_sram_inv;
wire [0:0] mux_tree_size14_13_out;
wire [0:3] mux_tree_size14_13_sram;
wire [0:3] mux_tree_size14_13_sram_inv;
wire [0:0] mux_tree_size14_14_out;
wire [0:3] mux_tree_size14_14_sram;
wire [0:3] mux_tree_size14_14_sram_inv;
wire [0:0] mux_tree_size14_15_out;
wire [0:3] mux_tree_size14_15_sram;
wire [0:3] mux_tree_size14_15_sram_inv;
wire [0:0] mux_tree_size14_1_out;
wire [0:3] mux_tree_size14_1_sram;
wire [0:3] mux_tree_size14_1_sram_inv;
wire [0:0] mux_tree_size14_2_out;
wire [0:3] mux_tree_size14_2_sram;
wire [0:3] mux_tree_size14_2_sram_inv;
wire [0:0] mux_tree_size14_3_out;
wire [0:3] mux_tree_size14_3_sram;
wire [0:3] mux_tree_size14_3_sram_inv;
wire [0:0] mux_tree_size14_4_out;
wire [0:3] mux_tree_size14_4_sram;
wire [0:3] mux_tree_size14_4_sram_inv;
wire [0:0] mux_tree_size14_5_out;
wire [0:3] mux_tree_size14_5_sram;
wire [0:3] mux_tree_size14_5_sram_inv;
wire [0:0] mux_tree_size14_6_out;
wire [0:3] mux_tree_size14_6_sram;
wire [0:3] mux_tree_size14_6_sram_inv;
wire [0:0] mux_tree_size14_7_out;
wire [0:3] mux_tree_size14_7_sram;
wire [0:3] mux_tree_size14_7_sram_inv;
wire [0:0] mux_tree_size14_8_out;
wire [0:3] mux_tree_size14_8_sram;
wire [0:3] mux_tree_size14_8_sram_inv;
wire [0:0] mux_tree_size14_9_out;
wire [0:3] mux_tree_size14_9_sram;
wire [0:3] mux_tree_size14_9_sram_inv;
wire [0:0] mux_tree_size14_mem_0_ccff_tail;
wire [0:0] mux_tree_size14_mem_10_ccff_tail;
wire [0:0] mux_tree_size14_mem_11_ccff_tail;
wire [0:0] mux_tree_size14_mem_12_ccff_tail;
wire [0:0] mux_tree_size14_mem_13_ccff_tail;
wire [0:0] mux_tree_size14_mem_14_ccff_tail;
wire [0:0] mux_tree_size14_mem_1_ccff_tail;
wire [0:0] mux_tree_size14_mem_2_ccff_tail;
wire [0:0] mux_tree_size14_mem_3_ccff_tail;
wire [0:0] mux_tree_size14_mem_4_ccff_tail;
wire [0:0] mux_tree_size14_mem_5_ccff_tail;
wire [0:0] mux_tree_size14_mem_6_ccff_tail;
wire [0:0] mux_tree_size14_mem_7_ccff_tail;
wire [0:0] mux_tree_size14_mem_8_ccff_tail;
wire [0:0] mux_tree_size14_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fle_in({mux_tree_size14_0_out, mux_tree_size14_1_out, mux_tree_size14_2_out, mux_tree_size14_3_out}),
.fle_clk(direct_interc_4_out),
.ccff_head(ccff_head),
.fle_out(logical_tile_clb_mode_default__fle_0_fle_out),
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fle_in({mux_tree_size14_4_out, mux_tree_size14_5_out, mux_tree_size14_6_out, mux_tree_size14_7_out}),
.fle_clk(direct_interc_5_out),
.ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_1_fle_out),
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fle_in({mux_tree_size14_8_out, mux_tree_size14_9_out, mux_tree_size14_10_out, mux_tree_size14_11_out}),
.fle_clk(direct_interc_6_out),
.ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_2_fle_out),
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fle_in({mux_tree_size14_12_out, mux_tree_size14_13_out, mux_tree_size14_14_out, mux_tree_size14_15_out}),
.fle_clk(direct_interc_7_out),
.ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_3_fle_out),
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_0_fle_out),
.out(clb_O[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_1_fle_out),
.out(clb_O[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_2_fle_out),
.out(clb_O[2]));
direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_3_fle_out),
.out(clb_O[3]));
direct_interc direct_interc_4_ (
.in(clb_clk),
.out(direct_interc_4_out));
direct_interc direct_interc_5_ (
.in(clb_clk),
.out(direct_interc_5_out));
direct_interc direct_interc_6_ (
.in(clb_clk),
.out(direct_interc_6_out));
direct_interc direct_interc_7_ (
.in(clb_clk),
.out(direct_interc_7_out));
mux_tree_size14 mux_fle_0_in_0 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_0_sram[0:3]),
.sram_inv(mux_tree_size14_0_sram_inv[0:3]),
.out(mux_tree_size14_0_out));
mux_tree_size14 mux_fle_0_in_1 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_1_sram[0:3]),
.sram_inv(mux_tree_size14_1_sram_inv[0:3]),
.out(mux_tree_size14_1_out));
mux_tree_size14 mux_fle_0_in_2 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_2_sram[0:3]),
.sram_inv(mux_tree_size14_2_sram_inv[0:3]),
.out(mux_tree_size14_2_out));
mux_tree_size14 mux_fle_0_in_3 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_3_sram[0:3]),
.sram_inv(mux_tree_size14_3_sram_inv[0:3]),
.out(mux_tree_size14_3_out));
mux_tree_size14 mux_fle_1_in_0 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_4_sram[0:3]),
.sram_inv(mux_tree_size14_4_sram_inv[0:3]),
.out(mux_tree_size14_4_out));
mux_tree_size14 mux_fle_1_in_1 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_5_sram[0:3]),
.sram_inv(mux_tree_size14_5_sram_inv[0:3]),
.out(mux_tree_size14_5_out));
mux_tree_size14 mux_fle_1_in_2 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_6_sram[0:3]),
.sram_inv(mux_tree_size14_6_sram_inv[0:3]),
.out(mux_tree_size14_6_out));
mux_tree_size14 mux_fle_1_in_3 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_7_sram[0:3]),
.sram_inv(mux_tree_size14_7_sram_inv[0:3]),
.out(mux_tree_size14_7_out));
mux_tree_size14 mux_fle_2_in_0 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_8_sram[0:3]),
.sram_inv(mux_tree_size14_8_sram_inv[0:3]),
.out(mux_tree_size14_8_out));
mux_tree_size14 mux_fle_2_in_1 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_9_sram[0:3]),
.sram_inv(mux_tree_size14_9_sram_inv[0:3]),
.out(mux_tree_size14_9_out));
mux_tree_size14 mux_fle_2_in_2 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_10_sram[0:3]),
.sram_inv(mux_tree_size14_10_sram_inv[0:3]),
.out(mux_tree_size14_10_out));
mux_tree_size14 mux_fle_2_in_3 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_11_sram[0:3]),
.sram_inv(mux_tree_size14_11_sram_inv[0:3]),
.out(mux_tree_size14_11_out));
mux_tree_size14 mux_fle_3_in_0 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_12_sram[0:3]),
.sram_inv(mux_tree_size14_12_sram_inv[0:3]),
.out(mux_tree_size14_12_out));
mux_tree_size14 mux_fle_3_in_1 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_13_sram[0:3]),
.sram_inv(mux_tree_size14_13_sram_inv[0:3]),
.out(mux_tree_size14_13_out));
mux_tree_size14 mux_fle_3_in_2 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_14_sram[0:3]),
.sram_inv(mux_tree_size14_14_sram_inv[0:3]),
.out(mux_tree_size14_14_out));
mux_tree_size14 mux_fle_3_in_3 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_15_sram[0:3]),
.sram_inv(mux_tree_size14_15_sram_inv[0:3]),
.out(mux_tree_size14_15_out));
mux_tree_size14_mem mem_fle_0_in_0 (
.prog_clk(prog_clk),
.ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail),
.ccff_tail(mux_tree_size14_mem_0_ccff_tail),
.mem_out(mux_tree_size14_0_sram[0:3]),
.mem_outb(mux_tree_size14_0_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_0_in_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_0_ccff_tail),
.ccff_tail(mux_tree_size14_mem_1_ccff_tail),
.mem_out(mux_tree_size14_1_sram[0:3]),
.mem_outb(mux_tree_size14_1_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_0_in_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_1_ccff_tail),
.ccff_tail(mux_tree_size14_mem_2_ccff_tail),
.mem_out(mux_tree_size14_2_sram[0:3]),
.mem_outb(mux_tree_size14_2_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_0_in_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_2_ccff_tail),
.ccff_tail(mux_tree_size14_mem_3_ccff_tail),
.mem_out(mux_tree_size14_3_sram[0:3]),
.mem_outb(mux_tree_size14_3_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_1_in_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_3_ccff_tail),
.ccff_tail(mux_tree_size14_mem_4_ccff_tail),
.mem_out(mux_tree_size14_4_sram[0:3]),
.mem_outb(mux_tree_size14_4_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_1_in_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_4_ccff_tail),
.ccff_tail(mux_tree_size14_mem_5_ccff_tail),
.mem_out(mux_tree_size14_5_sram[0:3]),
.mem_outb(mux_tree_size14_5_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_1_in_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_5_ccff_tail),
.ccff_tail(mux_tree_size14_mem_6_ccff_tail),
.mem_out(mux_tree_size14_6_sram[0:3]),
.mem_outb(mux_tree_size14_6_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_1_in_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_6_ccff_tail),
.ccff_tail(mux_tree_size14_mem_7_ccff_tail),
.mem_out(mux_tree_size14_7_sram[0:3]),
.mem_outb(mux_tree_size14_7_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_2_in_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_7_ccff_tail),
.ccff_tail(mux_tree_size14_mem_8_ccff_tail),
.mem_out(mux_tree_size14_8_sram[0:3]),
.mem_outb(mux_tree_size14_8_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_2_in_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_8_ccff_tail),
.ccff_tail(mux_tree_size14_mem_9_ccff_tail),
.mem_out(mux_tree_size14_9_sram[0:3]),
.mem_outb(mux_tree_size14_9_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_2_in_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_9_ccff_tail),
.ccff_tail(mux_tree_size14_mem_10_ccff_tail),
.mem_out(mux_tree_size14_10_sram[0:3]),
.mem_outb(mux_tree_size14_10_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_2_in_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_10_ccff_tail),
.ccff_tail(mux_tree_size14_mem_11_ccff_tail),
.mem_out(mux_tree_size14_11_sram[0:3]),
.mem_outb(mux_tree_size14_11_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_3_in_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_11_ccff_tail),
.ccff_tail(mux_tree_size14_mem_12_ccff_tail),
.mem_out(mux_tree_size14_12_sram[0:3]),
.mem_outb(mux_tree_size14_12_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_3_in_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_12_ccff_tail),
.ccff_tail(mux_tree_size14_mem_13_ccff_tail),
.mem_out(mux_tree_size14_13_sram[0:3]),
.mem_outb(mux_tree_size14_13_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_3_in_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_13_ccff_tail),
.ccff_tail(mux_tree_size14_mem_14_ccff_tail),
.mem_out(mux_tree_size14_14_sram[0:3]),
.mem_outb(mux_tree_size14_14_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_3_in_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_14_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_size14_15_sram[0:3]),
.mem_outb(mux_tree_size14_15_sram_inv[0:3]));
endmodule
// ----- END Verilog module for logical_tile_clb_mode_clb_ -----
//----- Default net type -----
`default_nettype none
// ----- END Physical programmable logic block Verilog module: clb -----

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