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3807 Commits

Author SHA1 Message Date
tangxifan 8b8096f3a8 [HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block 2021-04-24 14:57:09 -06:00
tangxifan a3a98fa21d [Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition 2021-04-24 14:56:10 -06:00
tangxifan 148da80869 [Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes 2021-04-24 14:53:29 -06:00
tangxifan 4f454abfde [Arch] Add a new architecture using fracturable 16-bit DSP blocks 2021-04-24 14:01:42 -06:00
tangxifan 272d1fffb7 [HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks 2021-04-24 13:30:46 -06:00
tangxifan ddcdb35b28 [Arch] Bug fix in single-mode 8-bit DSP architectures 2021-04-24 13:30:03 -06:00
tangxifan 1c6b9a23d7 [Test] Add new test for multi-mode 16-bit DSP blocks 2021-04-24 13:29:29 -06:00
tangxifan 0709e5bb81 [Tool] Fixed a bug in the routing trace finder for direct connections inside repacker 2021-04-24 13:27:44 -06:00
Parnabrita Mondal cc92c27fde
Update compile.rst 2021-04-24 14:01:52 +05:30
tangxifan c44688739d [HDL] Add verilog netlist for the fracturable 16-bit multiplier blocks 2021-04-23 22:12:26 -06:00
tangxifan 09cc7f0007 [Script] Enable constant net routing for heterogeneous FPGAs 2021-04-23 20:44:36 -06:00
tangxifan 189c94ff19 [Test] Deploy new mac benchmarks to tests 2021-04-23 20:44:14 -06:00
tangxifan 200b6d39a6 [Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit 2021-04-23 20:36:28 -06:00
tangxifan 671394ec2c [Benchmark] Add microbenchmarks for mac with different sizes for DSP testing 2021-04-23 20:33:43 -06:00
tangxifan 5ce28158bd
Merge pull request #297 from lnis-uofu/iwls2005 
Enable constant net routing for VTR benchmarks
 2021-04-23 16:52:35 -06:00
tangxifan 1db7719045
Merge branch 'master' into iwls2005 2021-04-23 15:11:14 -06:00
tangxifan cbb7d41b6e [Script] Enable constant net routing for VTR benchmarks 2021-04-23 14:15:13 -06:00
tangxifan f01b43c0fd
Merge pull request #296 from lnis-uofu/iwls2005 
Unlock flexible FF mapping and enable IWLS'2005 benchmark
 2021-04-22 20:31:40 -06:00
tangxifan 784713e88a [Test] Add golden results for IWLS2005 as a simple QoR check 2021-04-22 19:27:31 -06:00
tangxifan a16896054d [Script] Enable constant net routing for iwls benchmarks 2021-04-22 19:16:32 -06:00
tangxifan 56948244bc [Tool] Patch a critical bug in pb pin fixup 2021-04-22 16:19:54 -06:00
tangxifan 1dcb8e39a9 [Test] Unlock more IWLS'2005 benchmarks in testing 2021-04-22 09:23:33 -06:00
tangxifan 61a473e479 [Test] Unlock more IWLS'2005 benchmarks under testing thanks to flexible FF mapping support 2021-04-21 22:56:19 -06:00
tangxifan 5a519390ff [HDL] Enriched DFF model in yosys technology library 2021-04-21 22:49:05 -06:00
tangxifan ce6018e123 [Arch] Enriched DFF model to support active-low/high FFs 2021-04-21 22:48:31 -06:00
tangxifan adfea88be2 [HDL] Rename multi-mode DFF module 2021-04-21 20:06:03 -06:00
tangxifan 62497549b6 [HDL] Add multi-mode DFF module 2021-04-21 20:04:40 -06:00
tangxifan 3a5c26c6a1 [Test] Update IWLS test by using new architecture and customize DFF techmap 2021-04-21 19:51:25 -06:00
tangxifan 8cbea6a268 [HDL] Add technology library for customizable DFF synthesis 2021-04-21 19:50:51 -06:00
tangxifan 3d615e1516 [Script] Add yosys script supporting customize DFF/BRAM/DSP mapping 2021-04-21 19:50:07 -06:00
tangxifan 9d9840d9b7 [Arch] Add architecture using multi-mode DFFs 2021-04-21 19:49:48 -06:00
tangxifan c198273378
Merge pull request #295 from lnis-uofu/multi_clock 
Patches on multi-clock support in repacking stage
 2021-04-21 15:22:53 -06:00
tangxifan 2e1cc5499d [Doc] Add disclaimer for limitations when using repack pin constraints 2021-04-21 14:14:54 -06:00
tangxifan 8046b16c15 [Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing 2021-04-21 14:04:34 -06:00
tangxifan b203ef7bc2 [Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs 2021-04-21 14:03:51 -06:00
tangxifan 96ce6b545f [Tool] Patch repack to consider design constraints for pins that are not equivalent 2021-04-21 13:53:08 -06:00
tangxifan 12f27cf117
Merge pull request #294 from lnis-uofu/mux_default_path 
Support customizable default path in bitstream generation for any interconnect inside pb_type
 2021-04-19 18:29:03 -06:00
tangxifan 2fa370d7d5 [Test] Patch regression tests for fpga bitstream 2021-04-19 17:15:14 -06:00
tangxifan 9b3dcc65bd [Doc] Add new bitstream setting syntex 'interconnect' to documentation 2021-04-19 16:37:21 -06:00
tangxifan 17fb532ffa
Merge branch 'master' into mux_default_path 2021-04-19 16:23:44 -06:00
tangxifan 64163edbe6 [Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting 2021-04-19 16:15:25 -06:00
tangxifan 578d81b67a [Test] Patch task configuration file 2021-04-19 16:15:00 -06:00
tangxifan f7767ff4df
Merge pull request #284 from lnis-uofu/tutorials 
Tutorials
 2021-04-19 16:00:16 -06:00
tangxifan 18eb5c9de9 [Test] Deploy new test to CI 2021-04-19 15:56:41 -06:00
tangxifan 5976cc0a1c [Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection 2021-04-19 15:54:18 -06:00
tangxifan 0aec30bac6 [Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file 2021-04-19 15:53:33 -06:00
bbleaptrot 986ea492f6
Fix grammar line 38: lookup table ->Look-Up Table 2021-04-19 14:16:40 -06:00
tangxifan 5364b94cf8 [Tool] Update bitstream setting parser/writer to support interconnect-related syntax 2021-04-19 13:42:12 -06:00
tangxifan 2ff3dc0a0f
Merge branch 'master' into tutorials 2021-04-19 11:35:18 -06:00
bbleaptrot bc6e9746c2
Fix more grammar mistakes 2021-04-19 09:48:42 -06:00