tangxifan
|
cca9fb4756
|
[core] fixed a bug on bottom left tile organization
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2024-07-05 17:55:19 -07:00 |
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tangxifan
|
46d916f0a0
|
[core] fixed the bugs in fabric tile build-up
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2024-07-05 16:59:08 -07:00 |
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tangxifan
|
a41f437109
|
[core] now netlist look ok
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2024-07-05 12:36:47 -07:00 |
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tangxifan
|
283aa3a1c9
|
[core] debug
|
2024-07-05 12:21:17 -07:00 |
|
tangxifan
|
46e3b4b071
|
[core] debug
|
2024-07-05 11:50:41 -07:00 |
|
tangxifan
|
fdbc427f70
|
[core] debug
|
2024-07-05 11:17:05 -07:00 |
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tangxifan
|
f6adca1545
|
[core] fixed a bug
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2024-07-05 11:02:01 -07:00 |
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tangxifan
|
1dc602a849
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[core] syntax
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2024-07-05 10:38:26 -07:00 |
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tangxifan
|
266c2686d4
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[core] adapt new gsb coordinate system
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2024-07-05 10:32:33 -07:00 |
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tangxifan
|
1f8c2436ef
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[core] now constant_undriven_inputs are force to enable when perimeter_cb is selected
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2024-07-04 20:46:38 -07:00 |
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tangxifan
|
72ee39f178
|
[core] add new command line option 'constant_undriven_inputs'
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2024-07-04 20:39:02 -07:00 |
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tangxifan
|
4e21bbb3f1
|
[core] now support constant undriven local wires in verilog writer
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2024-07-04 20:32:56 -07:00 |
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tangxifan
|
1dd03d0fdd
|
[core] on a new feature to connect undriven pins to ground
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2024-07-04 18:34:39 -07:00 |
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tangxifan
|
6d798897fd
|
[lib] update vtr
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2024-07-04 14:46:57 -07:00 |
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tangxifan
|
f560fb8381
|
[core] more verbose
|
2024-07-04 14:27:17 -07:00 |
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tangxifan
|
a8850d4f0f
|
[core] now verbose mode is applicable to more build top module cb instances
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2024-07-04 14:22:30 -07:00 |
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tangxifan
|
4b53e57c92
|
[core] fixed a bug
|
2024-07-04 13:33:04 -07:00 |
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tangxifan
|
d2a68ff9c5
|
[core] now corner tile are considered as config child
|
2024-07-04 13:25:57 -07:00 |
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tangxifan
|
b80ed8d15c
|
[core] fixed a bug
|
2024-07-04 12:58:16 -07:00 |
|
tangxifan
|
a3723b33b3
|
[core] fixed a minor bug
|
2024-07-04 12:52:29 -07:00 |
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tangxifan
|
a717882304
|
[core] now when perimeter_cb is on, I/O pins can access three sides of routing tracks
|
2024-07-04 12:44:48 -07:00 |
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tangxifan
|
724c14d1f7
|
[core] fixed a bug on build top module connections on perimeter gsb when cbs occur
|
2024-07-04 11:09:01 -07:00 |
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tangxifan
|
550ce0c390
|
[core] fixed the bug on build gsb when cbs are on perimeters
|
2024-07-04 10:58:44 -07:00 |
|
tangxifan
|
bc94e08c77
|
[lib] update vtr and fixing some bugs in annotate gsb when perimeter_cb is enabled
|
2024-07-03 22:28:22 -07:00 |
|
tangxifan
|
a27325d987
|
[core] code format
|
2024-07-03 17:05:27 -07:00 |
|
tangxifan
|
f681c6a903
|
[core] update API call due to vtr upgrade
|
2024-07-03 17:04:06 -07:00 |
|
tangxifan
|
a85a6f1674
|
[core] code format
|
2024-07-01 17:57:10 -07:00 |
|
tangxifan
|
70428fd969
|
[lib] add sanity checks on global port name and clock network's global port name
|
2024-07-01 17:56:29 -07:00 |
|
tangxifan
|
3afb92d6a5
|
[core] code format
|
2024-06-30 22:48:15 -07:00 |
|
tangxifan
|
1fd974d544
|
[core] fixed a bug where clock network size cannot impact global port on top module
|
2024-06-29 17:35:47 -07:00 |
|
tangxifan
|
4f787a5cfc
|
[core] add more debugging message
|
2024-06-29 10:54:08 -07:00 |
|
tangxifan
|
5fa674be24
|
[core] fixed the bug on matching global net from pcf
|
2024-06-29 10:51:45 -07:00 |
|
tangxifan
|
8bc37080fa
|
[core] debuggging
|
2024-06-28 23:06:21 -07:00 |
|
tangxifan
|
1c69365938
|
[core] debugging
|
2024-06-28 18:17:38 -07:00 |
|
tangxifan
|
0de3ff3eb8
|
[core] debugging
|
2024-06-28 17:16:33 -07:00 |
|
tangxifan
|
e0b9f7860b
|
[core] fixed a bug where counter for gnets are not activated
|
2024-06-28 14:10:14 -07:00 |
|
tangxifan
|
5cfd23747b
|
[core] code format
|
2024-06-28 13:47:03 -07:00 |
|
tangxifan
|
f5b6774eb0
|
[core] add code comments and fixed some bugs
|
2024-06-28 12:21:33 -07:00 |
|
tangxifan
|
53ba2f0c29
|
[core] fixed a critical bug where some switching points are missing
|
2024-06-27 15:53:17 -07:00 |
|
tangxifan
|
5a7f618f29
|
[core] debugging
|
2024-06-27 15:44:17 -07:00 |
|
tangxifan
|
f4f487099d
|
[core] syntax
|
2024-06-27 15:07:48 -07:00 |
|
tangxifan
|
4185235a69
|
[core] now clock routing is based on tree expansion. Unused part can be disconnected
|
2024-06-27 15:02:20 -07:00 |
|
tangxifan
|
e75fd57af2
|
[core] refactor codes
|
2024-06-27 12:39:18 -07:00 |
|
tangxifan
|
7892c2340c
|
[core] add a new option 'disable_unused_trees' to route clock rr graph
|
2024-06-27 12:01:54 -07:00 |
|
tangxifan
|
6fceb81110
|
[core] code format
|
2024-06-27 10:19:40 -07:00 |
|
tangxifan
|
64a7a4ce26
|
[core] syntax
|
2024-06-27 10:19:14 -07:00 |
|
tangxifan
|
9ce552495a
|
[core] now internal drivers can be routed in dedicated clock network
|
2024-06-27 10:17:08 -07:00 |
|
tangxifan
|
ac1ad52795
|
[core] code format
|
2024-06-26 22:47:29 -07:00 |
|
tangxifan
|
5d0b0b9a8c
|
[core] now global nets mapping are applied to clock routing
|
2024-06-26 22:46:12 -07:00 |
|
tangxifan
|
d5d9531eec
|
[core] comment out buggy codes where global net mapping is not annotated in OpenFPGA
|
2024-06-26 21:52:45 -07:00 |