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OpenFPGA
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80 Commits

Author SHA1 Message Date
AurelienUoU 905293820f Draft2 2019-07-10 10:37:05 -06:00
AurelienUoU 20ce020eb6 Tutorial rewrite draft 1 2019-07-10 10:03:30 -06:00
AurelienUoU 8366f9e7b7 Update tutorial 2019-07-08 16:18:08 -06:00
AurelienUoU b4a78abc04 Update doc 
Merge remote-tracking branch 'origin/heterogeneous' into dev
 2019-07-05 12:25:37 -06:00
tangxifan c8ceb8f7d5 update fpga_flow.pl 2019-07-04 12:23:11 -06:00
tangxifan 5a50fa84d1 keep updating fpga_flow.pl to use system call 2019-07-03 22:57:43 -06:00
tangxifan 6b894640c7 bug fixing in fpga_flow.pl 2019-07-03 14:59:05 -06:00
tangxifan d5137eb424 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing 2019-07-03 14:31:18 -06:00
tangxifan 5195faab8b Merge branch 'dev' into tileable_routing 2019-07-03 14:30:39 -06:00
tangxifan 4f3cb0bdf3 added tileable routing chanW adaption to fixed W router 2019-07-03 14:29:50 -06:00
Ganesh Gore 443a73954f Removed all local files 
+ Removed local configurations and scripts from previous commit
 2019-07-03 14:26:06 -06:00
tangxifan c9743e84da Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-03 14:12:47 -06:00
tangxifan a539c6a2a7 bug fixing in fpga_flow.pl 2019-07-03 14:11:14 -06:00
Ganesh Gore 57ad71438b Merging ganesh_dev to dev 
- Added spice_tool option in fpga_flow
- Some local customization
 2019-07-03 13:39:52 -06:00
AurelienUoU e13c703709 Upload recent commit 
Merge remote-tracking branch 'origin/dev' into heterogeneous
 2019-07-03 13:09:34 -06:00
AurelienUoU 43e9d8afd1 Add compact routing hierarchy option in fpga_flow 2019-07-03 13:08:49 -06:00
Ganesh Gore 3c36a51011 Added 'rewrite_path_in_file' back to repository 2019-07-03 12:49:25 -06:00
Ganesh Gore 53486b8a89 Added 'spice_simulator_path' in fpga_flow 
added vpr_fpga_spice_simulator_path in fpga-flow script
 2019-07-03 12:30:56 -06:00
tangxifan 0c3e8bb70a add a new option to the router to enable conversion of route_chan_width to be tileable 2019-07-03 12:11:48 -06:00
tangxifan 02398818a9 update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area 2019-07-03 10:33:02 -06:00
tangxifan 4392c6bc3a bug fixing in fpga_flow scripts and add more print-out message for VPR 2019-07-02 15:34:59 -06:00
AurelienUoU 60f7ab0465 Start heterogeneous dev 2019-07-02 10:16:10 -06:00
Ganesh Gore 54f6ca2687 Added lattice benchmark settings 2019-07-01 11:07:23 -06:00
tangxifan c54f3905d5 fixed broken fpga flow 2019-06-28 13:07:04 -06:00
tangxifan 1332ba62e8 update tileable rr_graph generator to improve routability and also enable assoicated testing 2019-06-27 17:52:25 -06:00
tangxifan 4d3b5f12b4 fixed bugs for UNIVERSAL and WILTON switch blocks 2019-06-25 14:15:29 -06:00
AurelienUoU c76dbaac33 Update regression test avoiding overwritting files 2019-06-14 11:44:44 -06:00
tangxifan 0902d1e75a c++ string is not working, use char which is stable 2019-06-13 18:38:46 -06:00
AurelienUoU bf13c1f731 Add a script to create a new file with correct path rather than overwrite the existing 2019-06-11 14:28:58 -06:00
tangxifan d737c4ff46 fix path in regression test! TODO: must keep a duplicated copy for template.xml 2019-06-07 23:31:42 -06:00
tangxifan 0f1ed19ad0 Revert to the use of sprintf instead std::string. Have no idea why string is not working 2019-06-07 18:54:57 -06:00
AurelienUoU fcc10d8acf Correct fpga_flow/arch/template files 2019-06-04 16:45:04 -06:00
AurelienUoU a2f6ded2a2 Add path modification in file changing a keyword into OpenFPGA full path 2019-06-04 15:21:15 -06:00
AurelienUoU ba05a08ef0 Path correction in tech debugging + correction of yosys rewrite file in fpga_flow 2019-05-30 09:52:19 -06:00
AurelienUoU f934f6f0a3 Debug step 2019-05-28 15:01:16 -06:00
AurelienUoU e0717369e1 Re-insert power option in regression test 2019-05-28 09:48:03 -06:00
AurelienUoU d3f0ab59c2 Remove -power token until option is fixed 2019-05-23 19:26:25 -06:00
AurelienUoU 3811c18953 Correct syntax error in tokens of regression_fpga_flow.sh 2019-05-23 18:33:47 -06:00
AurelienUoU 1018134726 Update yosys to latest version + add simulation in fpga_flow 2019-05-23 17:55:49 -06:00
AurelienUoU 2b04376209 Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
AurelienUoU b4c97f86a3 Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
tangxifan d10e05f5cc Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-21 12:16:33 -06:00
tangxifan ec3b4c86c4 update file organization and be ready for SB/CB class 2019-05-21 12:15:38 -06:00
AurelienUoU 199cd99b23 Add dummy clock name in ace2 commands 2019-05-21 10:35:12 -06:00
AurelienUoU 2392d11790 Add debug command to understandn travis issue with ace 2019-05-20 16:06:37 -06:00
AurelienUoU becb90cd16 Correct syntax error in ace2 log file generation 2019-05-20 13:56:50 -06:00
AurelienUoU fbebb45bf2 Path correction in config file 2019-05-20 11:13:30 -06:00
AurelienUoU 82c76a2c39 Test removing the shell specification in fpga_flow.pl 2019-05-20 10:35:33 -06:00
AurelienUoU 43a64c26e8 Change tcsh to csh in fpga_flow.pl -> tcsh not found by travis 2019-05-20 09:44:38 -06:00
AurelienUoU 17ad905b14 Update flow and allow netlist generation 2019-05-17 17:00:38 -06:00