Aur??Lien ALACCHI
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eebdf7cb10
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Add possibility to choose default value for initialization
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2018-12-06 15:34:14 -07:00 |
Baudouin Chauviere
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0b6fcc8875
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Added the aliases for Yosys-ABC
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2018-12-06 15:06:01 -07:00 |
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Baudouin Chauviere
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0b1ccf7722
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and in the config path as well
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2018-12-06 14:57:32 -07:00 |
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Baudouin Chauviere
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6a54592a7b
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removed abc and added yosys in the flow
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2018-12-06 14:55:36 -07:00 |
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Baudouin Chauviere
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b6bb419e1d
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add a ModelSim option
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2018-12-06 14:13:37 -07:00 |
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Baudouin Chauviere
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fe47b3d21f
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Changing arch from memory dec to scff. Get the bitstream from go.sh
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2018-12-06 14:03:17 -07:00 |
BaudouinChauviere
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88af64c606
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Update eda_flow.rst
Distributions compilable added
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2018-12-05 16:29:07 -07:00 |
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BaudouinChauviere
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d0ac931daa
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Update README.md
Small correction
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2018-12-05 16:27:37 -07:00 |
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BaudouinChauviere
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576feb600f
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Update eda_flow.rst
Completed with FPGA-Verilog/Bitstream and corrected few errors
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2018-12-05 16:24:03 -07:00 |
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Aur??Lien ALACCHI
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8281b7346b
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Edit auto-generated modelsim script
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2018-12-05 16:15:29 -07:00 |
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Aur??Lien ALACCHI
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44b7f7f3d4
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Correct sub_modules.v generation to include decoders.v when necessary
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2018-12-05 13:52:25 -07:00 |
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Aur??Lien ALACCHI
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dc4accedd9
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Add forgottent files + add parameter transmission from verilog_api.c
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2018-12-05 11:33:14 -07:00 |
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Aur??Lien ALACCHI
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9a8c7b391a
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Add process for modelsim script autogeneration
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2018-12-05 09:20:47 -07:00 |
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Aur??Lien ALACCHI
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75d64db0f9
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Add verilog header sub_module.v file generation
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2018-12-04 18:42:47 -07:00 |
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Aur??Lien ALACCHI
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8ac566ecc0
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Add timing and initialization for simulation
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2018-12-04 17:32:09 -07:00 |
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BaudouinChauviere
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0f87fb9c3f
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Update file_organization.rst
Correction on the routing
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2018-12-03 14:21:40 -07:00 |
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BaudouinChauviere
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e541834bd0
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Update file_organization.rst
Made similar to the SPICE one
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2018-12-03 14:20:34 -07:00 |
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BaudouinChauviere
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cd301a5bb8
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Update file_organization.rst
Correction of the hierarchy
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2018-12-03 14:09:11 -07:00 |
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BaudouinChauviere
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9c97125b0d
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Update spice_simulation.rst
typo
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2018-12-03 13:42:45 -07:00 |
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BaudouinChauviere
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b8f702e16d
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Update file_organization.rst
Creation of the table for better understanding
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2018-12-03 13:40:42 -07:00 |
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BaudouinChauviere
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10cbd2efef
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Update index.rst
Commenting the multi mode out until more mature
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2018-12-03 11:50:13 -07:00 |
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BaudouinChauviere
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8e7def7f88
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Update link_circuit_modules.rst
Correction of typos
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2018-12-03 11:39:44 -07:00 |
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BaudouinChauviere
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f8e801b9d1
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Merge pull request #1 from LNIS-Projects/Documentation-Update
Update index.rst
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2018-12-03 11:27:05 -07:00 |
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BaudouinChauviere
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a4d29aeb1b
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Update circuit_model_examples.rst
Typo correction
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2018-12-03 11:26:04 -07:00 |
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BaudouinChauviere
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e39e0219e9
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Update circuit_modules.rst
Move the examples from this part to their own
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2018-12-03 10:59:20 -07:00 |
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BaudouinChauviere
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7a49ca8ce2
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Update index.rst
New section in the doc
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2018-12-03 10:58:50 -07:00 |
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BaudouinChauviere
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99769c1510
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Create circuit_model_examples.rst
Better architecture of the doc
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2018-12-03 10:58:11 -07:00 |
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BaudouinChauviere
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47a214520f
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Update index.rst
Skip lines
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2018-12-03 10:32:15 -07:00 |
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BaudouinChauviere
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6827549be2
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Update index.rst
Include the links for the external documentation
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2018-12-03 10:31:02 -07:00 |
tangxifan
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70751551b5
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fix a bug in wired LUT support
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2018-11-30 21:33:31 -07:00 |
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tangxifan
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4f5f8de46f
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Add Yosys and update flow_flow Perl Script
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2018-11-30 21:14:43 -07:00 |
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tangxifan
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e223868df8
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fix bugs for wired LUTs
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2018-11-27 12:46:30 -07:00 |
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Aur??Lien ALACCHI
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de2bc18bbb
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bugs fixed for shift register benchmark
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2018-11-26 16:58:45 -07:00 |
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Baudouin Chauviere
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d55ecd154b
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Add the PTM to the benchmark flow
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2018-11-21 11:32:34 -07:00 |
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Baudouin Chauviere
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8ce0a84bc1
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Correction of the global make, the fpga_flow and the doc
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2018-11-20 14:47:15 -07:00 |
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Baudouin Chauviere
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03e902023a
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Perl script integrated to flow. rm shell one
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2018-11-20 13:32:11 -07:00 |
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Baudouin Chauviere
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15d69e2bb1
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Generation script finished TODO: integration in flow
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2018-11-20 13:24:31 -07:00 |
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Baudouin Chauviere
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e74f05a161
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Switching from sh to pl
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2018-11-20 10:15:31 -07:00 |
Baudouin Chauviere
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9611576d6a
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Update on the examples to respect the new syntax
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2018-11-19 15:50:29 -07:00 |
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tangxifan
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861c449606
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support wired LUT in FPGA-SPICE and FPGA-Verilog
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2018-11-15 15:57:49 -07:00 |
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Baudouin Chauviere
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f7d7a056da
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Modification of the fpga_spice_utils
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2018-11-15 14:11:55 -07:00 |
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Baudouin Chauviere
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c81d00bb51
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Correction of the double free bug
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2018-11-15 13:55:16 -07:00 |
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Baudouin Chauviere
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e93c96801b
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Adding abc without bb support in the project
Needed for fpga_flow in standard mode (vtr_standard uses abc with bb support)
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2018-11-15 13:51:25 -07:00 |
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Baudouin Chauviere
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ea9cb91cad
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Update of the examples to correspond to the new syntax
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2018-11-14 14:01:39 -07:00 |
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Baudouin Chauviere
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ebc4629946
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Correction of the compilation to automatically get the submodules
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2018-11-08 15:56:22 -07:00 |
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Baudouin Chauviere
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fbaa52544c
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Implementation of OpenSTA in the project
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2018-11-08 13:13:45 -07:00 |
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Baudouin Chauviere
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dddca8acbb
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Global Makefile and typo correction
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2018-10-24 17:34:51 -06:00 |
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Baudouin Chauviere
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9538dbd644
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Config script written and changed some rights for some files
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2018-10-24 15:59:32 -06:00 |
Aurelien Alacchi
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4a950c6857
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Flatten_hierarchy_doc
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2018-10-18 16:28:12 -06:00 |
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Aurelien Alacchi
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aa5449c37d
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Verif_modif_doc_title_2
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2018-10-17 16:49:55 -06:00 |