ganeshgore
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f6b3c5854a
|
Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
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2020-04-11 16:45:22 -06:00 |
|
ganeshgore
|
8ea272dc2c
|
Patched the OpenFPGA shell execution bug
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2020-04-08 21:28:14 -06:00 |
|
ganeshgore
|
583a4d8767
|
Fixed bug in openfpga_flow script
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2020-04-08 12:04:08 -06:00 |
|
ganeshgore
|
e1db4df744
|
Created task for FPGA shell run
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2020-04-06 00:35:07 -06:00 |
|
ganeshgore
|
ea4122a8a4
|
Updated openfpga_flow and task file to support sheel run
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2020-04-06 00:34:36 -06:00 |
|
ganeshgore
|
7f98ecc8a6
|
OpenFPGA shell run test script template
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2020-04-06 00:32:43 -06:00 |
|
ganeshgore
|
eb3b02277a
|
Added XML and benchmarks for testing
|
2020-04-06 00:32:06 -06:00 |
|
ganeshgore
|
77f7e13ba7
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-05 20:59:10 -06:00 |
|
ganeshgore
|
d1d3446568
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backedup partial upgrade for fpga_flow script
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2020-04-05 11:36:24 -06:00 |
tangxifan
|
2f38b5cbc2
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Merge branch 'refactoring' into dev
|
2020-03-08 16:23:20 -06:00 |
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tangxifan
|
b219b096ee
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hotfix on removing dangling inputs from GSB, which are CLB direct output
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2020-03-08 13:54:49 -06:00 |
AurelienUoU
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c51001c853
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Add compilation verification task in openfpga_flow
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2020-01-23 13:13:23 -07:00 |
|
ganeshgore
|
cd69f1870d
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2020-01-23 10:07:36 -07:00 |
|
ganeshgore
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46bb5ef9d0
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Added disp option in openfpga_flow, Default is --nodisp
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2020-01-23 10:04:38 -07:00 |
|
AurelienUoU
|
85c9f26a9f
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Update documentation about cmake version and graphical interface
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2020-01-22 20:46:49 -07:00 |
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ganeshgore
|
f0bed1244c
|
Added blif file folding before VPR run
|
2020-01-09 16:50:34 -07:00 |
|
ganeshgore
|
74b650e9e1
|
Added fpga_x2p_duplicate_grid_pin option
|
2019-12-30 12:25:28 -07:00 |
|
ganeshgore
|
d1e260f54f
|
Spice related option added
|
2019-12-30 12:16:04 -07:00 |
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tangxifan
|
ef9ed2ccbc
|
added duplicate_grid_pin test case
|
2019-12-26 15:08:31 -07:00 |
|
AurelienUoU
|
09fd2afa9c
|
Adding heterogeneous synthesis requirements
|
2019-12-03 16:09:26 -07:00 |
|
AurelienUoU
|
32176eb352
|
Adding EPFL benchmark task for openfpga_flow
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2019-12-03 14:31:53 -07:00 |
|
AurelienUoU
|
2f14716f13
|
Adding DPRAM behavioural Verilog netlist and its TB
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2019-12-03 13:58:20 -07:00 |
|
tangxifan
|
96733f9ea8
|
add minor comments in task file for modelsim regression tests
|
2019-11-16 22:34:03 -07:00 |
|
Ganesh Gore
|
3f235a16f9
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-11-16 19:14:34 -07:00 |
|
Ganesh Gore
|
6bb11918dc
|
Updated modelsim and collected result
|
2019-11-16 19:10:04 -07:00 |
|
tangxifan
|
a13f406918
|
tweaking mcnc_big20 task run for modelsim
|
2019-11-16 18:00:55 -07:00 |
|
Ganesh Gore
|
00ec36c1af
|
Added Modelsim error check in log
|
2019-11-16 13:18:13 -07:00 |
|
Ganesh Gore
|
373dbe0718
|
First draft for multithreaded Modelsim simulation
|
2019-11-16 01:06:09 -07:00 |
|
Ganesh Gore
|
f05aede868
|
Added task support for modelsim script
|
2019-11-15 23:23:15 -07:00 |
|
Ganesh Gore
|
f52eaef622
|
Updated flow script and skipped travis upload on failure test setup.
|
2019-11-15 14:35:15 -07:00 |
|
tangxifan
|
4df6402241
|
add python script for batch simulations
|
2019-11-15 14:23:03 -07:00 |
|
tangxifan
|
d391983e8c
|
passing regression test on dpram benchmarks
|
2019-11-07 14:57:46 -07:00 |
|
tangxifan
|
56b4ee008e
|
add test for heterogeneous FPGA and fix bugs
|
2019-11-06 17:45:11 -07:00 |
|
tangxifan
|
4ea5756be6
|
bug fixed for std cell MUX2 architecture and add the case to regression tests
|
2019-11-06 16:06:47 -07:00 |
|
tangxifan
|
09eb373a6e
|
bug fixing for autocheck top testbench where clock port is not default names
|
2019-11-06 12:21:20 -07:00 |
|
tangxifan
|
00280b835e
|
reorganize regression tests
|
2019-11-05 16:31:42 -07:00 |
|
tangxifan
|
7952d134b9
|
add tree-like mux test case to regression test
|
2019-11-05 16:24:39 -07:00 |
|
tangxifan
|
a308a13d7c
|
use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
|
2019-11-05 15:41:59 -07:00 |
|
tangxifan
|
0ec465d4e1
|
refactoring auto-check top Verilog testbench
|
2019-11-03 17:41:29 -07:00 |
|
tangxifan
|
dc241e6c03
|
add explicit port mapping support in testbenches; remove dangling ports in benchmarks
|
2019-11-02 23:03:47 -06:00 |
|
Ganesh Gore
|
a880802803
|
Bug Fix: Corrected read VPR stat filename
|
2019-11-01 20:51:05 -06:00 |
|
tangxifan
|
e2b042c61c
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-11-01 18:27:27 -06:00 |
|
Ganesh Gore
|
370a5ed408
|
Bug Fix: shifter ff.v include path to tcl script
|
2019-11-01 18:22:40 -06:00 |
|
Ganesh Gore
|
595d2d3070
|
Simple argument shuffle
|
2019-11-01 18:21:26 -06:00 |
|
Ganesh Gore
|
27005d6640
|
Added Modelsim Python Script
|
2019-11-01 18:20:40 -06:00 |
|
tangxifan
|
49bfb3223c
|
add compact routing to regression test
|
2019-11-01 10:53:47 -06:00 |
|
tangxifan
|
531cc064fc
|
bug fixing for formal top-level testbench
|
2019-11-01 10:47:40 -06:00 |
|
Ganesh Gore
|
da0778e813
|
Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev
|
2019-11-01 00:46:34 -06:00 |
|
tangxifan
|
d709868463
|
adding more regression tests which is quick run but very helpful for debugging
|
2019-10-31 20:17:40 -06:00 |
|
tangxifan
|
a6a3e7c36b
|
adding mcnc_big20 to regression test
|
2019-10-31 19:31:27 -06:00 |