tangxifan
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8b17bf1b1c
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[test] add a new test case to validate that .act file is not required when power analysis flow is off
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2022-08-01 18:44:47 -07:00 |
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tangxifan
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35fe858035
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[test] fixed a few bugs
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2022-07-28 12:06:16 -07:00 |
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tangxifan
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ca9122ddb9
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[test] fixed a bug
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2022-07-28 11:57:47 -07:00 |
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tangxifan
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ec31e124b7
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[test] reworked test case on pcf2place
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2022-07-28 11:51:56 -07:00 |
taoli4rs
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cfc0d08060
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Add constrain_pin_location command in openfpga; add full flow test.
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2022-07-20 11:51:00 -07:00 |
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tangxifan
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9832722056
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[test] now add QuickLogic memory bank to fpga bitstream regression tests
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2022-05-25 11:42:32 +08:00 |
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tangxifan
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86347a9d49
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[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
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2022-05-25 11:19:49 +08:00 |
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tangxifan
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6719a9aa26
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[test] update golden netlists/testbenches etc.
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2022-05-22 13:03:01 +08:00 |
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tangxifan
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22c4d72358
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[test] add a test case to validate negative edge-triggered ff
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2022-05-09 16:57:42 +08:00 |
Ganesh Gore
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522982c9ba
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Adde vtr_benchmarks_template for demo
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2022-05-06 22:40:36 -06:00 |
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Ganesh Gore
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275cda081e
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[Bugfix] Typo
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2022-05-05 08:40:21 -06:00 |
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Ganesh Gore
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e845b62322
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Update regession tasks
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2022-05-05 01:46:19 -06:00 |
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Ganesh Gore
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21c3dbf611
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Added regression for template project
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2022-05-02 23:23:45 -06:00 |
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Ganesh Gore
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9891e42f7a
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Added template task
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2022-05-02 11:49:16 -06:00 |
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tangxifan
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efc25aa66e
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[Script] Fixed a bug in wrong paths
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2022-04-13 16:04:33 +08:00 |
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tangxifan
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5beefda3bd
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[Test] Add a new test case to validate the fix_pins option
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2022-04-13 15:55:21 +08:00 |
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tangxifan
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f8845f7d3a
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[Test] Add a test case to validate separated clock pins in global port
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2022-03-20 11:02:07 +08:00 |
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tangxifan
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fdaf97e60d
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[Test] Update test case by using GPIO with config_done signals
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2022-02-24 09:49:34 -08:00 |
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tangxifan
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a615c9d4e3
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[Test] Rename test cases
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2022-02-24 09:43:41 -08:00 |
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tangxifan
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b27a04eb24
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[Test] Now test case has a config done CCFF
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2022-02-23 22:07:11 -08:00 |
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tangxifan
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245c7b1e45
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[Test] Add a new test case to validate config enable signal in preconfigured testbenches
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2022-02-23 16:02:00 -08:00 |
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tangxifan
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e33ba667e4
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[Test] Add missing file
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2022-02-20 10:59:44 -08:00 |
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tangxifan
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f30de1085c
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[Test] Cover all the related testcase about bus group
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2022-02-19 23:33:16 -08:00 |
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tangxifan
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b4202f52b4
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[Test] debugging
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2022-02-19 23:26:29 -08:00 |
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tangxifan
|
785bb1633d
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[Test] trying to see if we support busgroup per benchmark in task configuration file
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2022-02-19 23:23:36 -08:00 |
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tangxifan
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7645d5332d
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[Test] Update bug group examples on the big endian support
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2022-02-18 23:09:03 -08:00 |
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tangxifan
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f0ce1e79a3
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[Test] Added a new test to validate bus group in full testbench
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2022-02-18 15:43:21 -08:00 |
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tangxifan
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223575cf3e
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[Test] Added a new test for bus group on full testbenches
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2022-02-18 15:33:29 -08:00 |
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tangxifan
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5ab84e1861
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[Test] Add a new test for bus group
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2022-02-18 15:29:33 -08:00 |
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tangxifan
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b4d59fdd1e
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[Test] Update bus group file due to little and big endian conversion during yosys/vpr
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2022-02-18 15:02:08 -08:00 |
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tangxifan
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36543f7f2f
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[Script] Support simplified rewriting for Yosys on output verilog
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2022-02-18 14:54:39 -08:00 |
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tangxifan
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8ba3d06392
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[Test] Fixed bugs in simulation settings
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2022-02-18 12:36:22 -08:00 |
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tangxifan
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a4d5172b7c
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[Test] Fixed bugs that causes VPR failed
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2022-02-18 12:31:29 -08:00 |
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tangxifan
|
7176037bc4
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[Test] Added a new test about bus group
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2022-02-18 12:26:00 -08:00 |
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tangxifan
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f02f3c10d4
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[Test] Fix bugs on the remaining implicit verilog test cases
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2022-02-15 16:49:15 -08:00 |
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tangxifan
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1370be0817
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[Script] Fixing bugs
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2022-02-15 16:44:51 -08:00 |
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tangxifan
|
8be0868a3b
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[Test] Update test case which uses counter benchmarks: adding pin constraints
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2022-02-15 16:29:06 -08:00 |
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tangxifan
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f002c79a61
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[Test] Adapt pin constraints due to changes in pin names
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2022-02-15 16:06:46 -08:00 |
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tangxifan
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b533fd17d5
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[Test] Rework pin constraints that cause problems
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2022-02-15 15:41:16 -08:00 |
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tangxifan
|
9ef7ad64d8
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[Test] Simplify paths
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2022-02-15 15:35:21 -08:00 |
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tangxifan
|
d0fe8d96fa
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[Test] Update template scripts and assoicated test cases by offering more options
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2022-02-14 16:03:48 -08:00 |
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tangxifan
|
70363effa4
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[Test] Add a new test to validate 8-bit counters using full testbenches
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2022-02-14 15:57:55 -08:00 |
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tangxifan
|
7ef808cbe4
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[Test] Update pin constraints for different counter benchmarks
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2022-02-14 15:28:03 -08:00 |
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tangxifan
|
570c1b10dc
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[Test] Add dedicated pin constraints for counter designs
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2022-02-14 13:54:48 -08:00 |
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tangxifan
|
85011824e2
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[Test] Enable Verilog-to-Verification flow for counter8 benchmarks
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2022-02-14 13:15:55 -08:00 |
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tangxifan
|
6630c17c23
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[Test] Use preconfigured testbench template to run counter8 tests
|
2022-02-14 13:07:31 -08:00 |
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tangxifan
|
da3f9ccb80
|
[Test] Truncating counter designs in each task
|
2022-02-14 12:22:19 -08:00 |
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tangxifan
|
0268814fc6
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[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
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2022-02-14 12:20:56 -08:00 |
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tangxifan
|
532af96243
|
[Test] Add a new testcase to validate ``--use_relative_path`` in preconfigured testbench
|
2022-02-01 13:44:47 -08:00 |
|
tangxifan
|
da8fc0f5d4
|
[Test] Add a new test case to validate ``--use_relative_path``
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2022-01-31 13:02:19 -08:00 |