tangxifan
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07994d424c
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add XML parser and writer for direct connection
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2020-01-19 15:00:19 -07:00 |
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tangxifan
|
10336cbe67
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add XML parser and writer for routing circuit definition for OpenFPGA architecture
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2020-01-19 14:44:27 -07:00 |
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tangxifan
|
ebe46d15a9
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add XML parser, writer and linker for configuration protocol data structure
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2020-01-18 21:19:20 -07:00 |
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tangxifan
|
9693c3a12d
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add XML writer for simulation setting object
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2020-01-18 16:41:42 -07:00 |
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tangxifan
|
bc3130d196
|
add XML parser for simulation setting
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2020-01-18 15:40:20 -07:00 |
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tangxifan
|
2a902c7e55
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add mutators to simulation setting data structure
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2020-01-18 14:07:37 -07:00 |
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tangxifan
|
0de9908d52
|
add accessors to simulation setting data structure
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2020-01-18 12:51:25 -07:00 |
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tangxifan
|
7a46c85cb0
|
reorganize and clean-up sample architecture
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2020-01-18 10:50:15 -07:00 |
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tangxifan
|
c9da3d5207
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-01-17 20:05:33 -07:00 |
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tangxifan
|
ab1b1b7e02
|
add XML writer for technology library
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2020-01-17 20:02:56 -07:00 |
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tangxifan
|
df68dddb2a
|
Merge branch 'refactoring' into dev
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2020-01-17 19:03:57 -07:00 |
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tangxifan
|
8f2936af54
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finish XML parser for technology library
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2020-01-17 17:43:55 -07:00 |
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tangxifan
|
e54760c677
|
add XML parsing for transistors and RRAM parameters in technology library
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2020-01-17 17:32:42 -07:00 |
|
tangxifan
|
d48a888804
|
add XML parsing for design parameters in technology library
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2020-01-17 17:22:09 -07:00 |
|
tangxifan
|
de0bcc96fb
|
add missing file about XML parsers for technology library
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2020-01-17 17:16:32 -07:00 |
|
tangxifan
|
d58186507c
|
add XML parsing for device model library settings
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2020-01-17 17:15:58 -07:00 |
|
tangxifan
|
88a96673e3
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rename some methods in technology library and start building associated XML parser
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2020-01-17 16:44:57 -07:00 |
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tangxifan
|
6a17abf257
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-01-17 15:36:22 -07:00 |
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tangxifan
|
b1501223cc
|
bug fixed in SDC for CBs and SBs: remove useless module names
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2020-01-17 15:33:50 -07:00 |
|
tangxifan
|
4bb0da5a69
|
bug fixing for direct connection when pin duplication is applied
|
2020-01-17 15:33:50 -07:00 |
|
tangxifan
|
d4b5171fa2
|
add comments to technology library
|
2020-01-17 15:31:44 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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c68f373917
|
Merge pull request #41 from LNIS-Projects/dev
bug fixed in SDC for CBs and SBs: remove useless module names
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2020-01-17 15:29:00 -07:00 |
|
tangxifan
|
313922f03f
|
add internal linker to technology library
|
2020-01-17 15:04:00 -07:00 |
|
tangxifan
|
edaaa00c1d
|
added mutators for technology library
|
2020-01-17 14:46:09 -07:00 |
|
tangxifan
|
6b703a4fc5
|
add accessors to technology library data structure
|
2020-01-17 13:34:32 -07:00 |
|
tangxifan
|
622ba9bb8c
|
bug fixed in SDC for CBs and SBs: remove useless module names
|
2020-01-17 11:24:33 -07:00 |
|
tangxifan
|
771f2d9c37
|
developing data structure TechnologyLibrary to store technology-related information
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2020-01-17 10:17:15 -07:00 |
|
tangxifan
|
aa070b2a41
|
further clean-up sample arch.xml
|
2020-01-17 09:38:35 -07:00 |
|
tangxifan
|
910c69d7e5
|
clean up and reorganize XML about technology library
|
2020-01-17 09:24:58 -07:00 |
|
tangxifan
|
5c69f57559
|
sample_arch:move cmos/rram variation to technology library XML nodes
|
2020-01-16 20:58:45 -07:00 |
|
tangxifan
|
95edd3c091
|
clean up the sample arch
|
2020-01-16 20:52:47 -07:00 |
|
tangxifan
|
a598929fe7
|
add circuit library checker in the test
|
2020-01-16 20:25:00 -07:00 |
|
tangxifan
|
f7a7c56366
|
move OpenFPGAArch to openfpga namespace
|
2020-01-16 20:22:56 -07:00 |
|
tangxifan
|
d6adfa0821
|
add XML parsing for delay matrix and wire parasitics for circuit library
|
2020-01-16 20:14:39 -07:00 |
|
tangxifan
|
2e0ce78054
|
add XML writing for buffers in circuit library
|
2020-01-16 17:21:41 -07:00 |
|
tangxifan
|
9ba42cd540
|
add XML writer for circuit ports
|
2020-01-16 16:05:11 -07:00 |
|
tangxifan
|
0304d723c0
|
add XML writer for design technology of a circuit model
|
2020-01-16 14:45:41 -07:00 |
|
tangxifan
|
3ace7f8ef7
|
move generic data structures to openfpgautil library
|
2020-01-16 13:26:55 -07:00 |
|
tangxifan
|
d232391250
|
developed XML writer for circuit library and start porting functions to openfpgautil library
|
2020-01-16 12:32:29 -07:00 |
|
tangxifan
|
e282f813bc
|
rename circuit settings to openfpga arch and update sample architecture
|
2020-01-15 20:28:04 -07:00 |
|
tangxifan
|
264dc8458d
|
add XML parsing for delay matrix in circuit model
|
2020-01-15 20:21:53 -07:00 |
|
tangxifan
|
602d0bde4c
|
add XML parsing for wire parasitics in circuit model
|
2020-01-15 19:54:57 -07:00 |
|
tangxifan
|
999c364b25
|
added XML parsing for circuit model ports
|
2020-01-15 17:29:49 -07:00 |
|
tangxifan
|
c20e1d48d2
|
added XML parsing for pass-gate-logic in circuit models
|
2020-01-15 15:49:02 -07:00 |
|
tangxifan
|
a9b122d584
|
add XML parsing for buffer models in circuit library
|
2020-01-15 15:27:49 -07:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
d0da5ade52
|
Pushing duplicate pin fix for direct list to master branch
Dev
|
2020-01-15 09:29:51 -07:00 |
|
tangxifan
|
35d6c9661b
|
Finish the first version of XML parser for design technology of circuit models
|
2020-01-14 16:24:27 -07:00 |
|
tangxifan
|
5937ffc809
|
add XML parsing for buffer/pass-gate-logic -related properties
|
2020-01-14 15:44:24 -07:00 |
|
tangxifan
|
9e911cd288
|
bug fixing for direct connection when pin duplication is applied
|
2020-01-14 15:04:47 -07:00 |
|
tangxifan
|
56113e1aab
|
adding XML parsing for design tech of circuit model
|
2020-01-14 14:10:00 -07:00 |