tangxifan
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b72d4bd807
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[Test] Update test case for 1kbit DPRAM architectures
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2021-04-28 11:28:53 -06:00 |
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tangxifan
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117cea295d
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[Arch] Patch architecture to be compatible with pin names of DPRAM cell
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2021-04-28 11:28:23 -06:00 |
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tangxifan
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a571b063b6
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[Benchmark] Add 1k DPRAM benchmark which can fit new arch
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2021-04-28 11:26:31 -06:00 |
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tangxifan
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c24edbd674
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[Script] Update yosys script due to arch changes in DPRAM sizes
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2021-04-28 10:55:59 -06:00 |
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tangxifan
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ec4b60f3cc
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[Arch] Add example arch using 1-kbit DPRAM
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2021-04-28 10:47:17 -06:00 |
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tangxifan
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be98775ae5
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[Arch] Reduce the size of DPRAM in example architecture to accelerate testing
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2021-04-28 10:45:10 -06:00 |
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tangxifan
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5c729657ef
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[Test] Bug fix in test case for DPRAM whose width = 2
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2021-04-28 10:31:22 -06:00 |
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tangxifan
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79b27a6329
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[Arch] Patch arch using DPRAM block with wide = 2
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2021-04-28 10:29:09 -06:00 |
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tangxifan
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63309ba72b
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[HDL] Patch dpram cell
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2021-04-27 23:42:31 -06:00 |
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tangxifan
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411af10933
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[Script] Patch yosys script for 16kbit dual port RAM
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2021-04-27 23:41:47 -06:00 |
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tangxifan
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834657f2da
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[Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes
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2021-04-27 23:41:14 -06:00 |
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tangxifan
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0bec4b3f32
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[Test] Update task configuration to use proper openfpgashell script
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2021-04-27 23:34:42 -06:00 |
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tangxifan
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7d059f7407
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[Benchmark] Bug fix in dual port ram 16k benchmark
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2021-04-27 23:33:20 -06:00 |
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tangxifan
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3c1c33bf1e
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[Benchmark] Add a microbenchmark just fit 16k dual port ram
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2021-04-27 22:51:43 -06:00 |
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tangxifan
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7e2368158e
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[Benchmark] move benchmarks to microbenchmark category
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2021-04-27 22:12:30 -06:00 |
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tangxifan
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5a85ec9fa0
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[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised
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2021-04-27 22:09:10 -06:00 |
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tangxifan
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dd46780865
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[Script] Update yosys script using BRAMs
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2021-04-27 21:44:27 -06:00 |
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tangxifan
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fdfbdc4613
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[Test] Update task configuration files to use dedicated yosys script
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2021-04-27 20:05:04 -06:00 |
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tangxifan
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2802b0895c
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[HDL] Add yosys technology library for reworked architecture using 16k-bit DPRAM
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2021-04-27 19:55:46 -06:00 |
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tangxifan
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e67095edd2
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[HDL] Add 16k-bit dual port ram verilog
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2021-04-27 19:55:16 -06:00 |
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tangxifan
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0f8aaae2bc
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[Arch] Patch architecture using 16kbit dual port RAM
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2021-04-27 19:54:34 -06:00 |
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tangxifan
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1d498bb296
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[Benchmark] Add a scalable micro benchmark fifo
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2021-04-27 15:26:52 -06:00 |
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tangxifan
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1d5e926d9e
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[Test] Deploy new test to CI
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2021-04-26 16:29:54 -06:00 |
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tangxifan
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6291871faf
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[Test] Added a test for the example architecture with 2x2 DSP blocks
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2021-04-26 16:28:43 -06:00 |
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tangxifan
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8c007c7c49
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[Arch] Add a new example architecture where a DSP block occupies a 2x2 grid
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2021-04-26 16:28:10 -06:00 |
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tangxifan
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64704f52eb
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Merge pull request #304 from lnis-uofu/tileable_rr_graph
Tileable rr graph
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2021-04-26 14:11:16 -06:00 |
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tangxifan
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3b50d00b30
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Merge branch 'master' into tileable_rr_graph
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2021-04-26 12:12:57 -06:00 |
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tangxifan
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9a8d109d85
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Merge pull request #303 from lnis-uofu/tangxifan-patch-1
Update PULL_REQUEST_TEMPLATE.md
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2021-04-26 12:06:23 -06:00 |
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tangxifan
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05f08c2f25
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Update PULL_REQUEST_TEMPLATE.md
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2021-04-26 12:05:37 -06:00 |
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tangxifan
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7d4c5e3cd1
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[Arch] Patch pin location of dsp8 to be evenly placed on the right side of a height=2 block
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2021-04-26 12:00:57 -06:00 |
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tangxifan
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6e87b8875b
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[Arch] Patch the pin location of frac dsp16 to appear on the top side of a height=2 block
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2021-04-26 11:59:25 -06:00 |
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tangxifan
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cbd7105083
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[Tool] Add illustrative comments to tileable rr_graph generator
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2021-04-26 11:57:17 -06:00 |
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tangxifan
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880624e699
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[Tool] Update comments in tileable rr_graph generator to be easier to be understood
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2021-04-26 11:48:02 -06:00 |
ganeshgore
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d7426808ba
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Merge pull request #299 from hitblunders/master
Updated compile.rst
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2021-04-26 00:26:07 -06:00 |
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ganeshgore
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ab34ebecef
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Merge pull request #301 from lnis-uofu/tangxifan-patch-1
Update bug_report.md
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2021-04-26 00:25:26 -06:00 |
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ganeshgore
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cb38455a52
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Merge pull request #302 from lnis-uofu/tangxifan-patch-2
Update pull_request_template.md
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2021-04-26 00:25:14 -06:00 |
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tangxifan
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deb9f4a9f7
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Update pull_request_template.md
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2021-04-25 22:11:34 -06:00 |
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tangxifan
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a8b2966709
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Update bug_report.md
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2021-04-25 22:08:17 -06:00 |
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tangxifan
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83167b6b61
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Update bug_report.md
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2021-04-25 22:06:13 -06:00 |
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tangxifan
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4b8dab0913
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Update bug_report.md
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2021-04-25 20:51:29 -06:00 |
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tangxifan
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386dbf8c1a
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Update pull_request_template.md
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2021-04-25 18:30:48 -06:00 |
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tangxifan
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94c575fa74
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Update bug_report.md
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2021-04-25 18:12:12 -06:00 |
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tangxifan
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1baee10e61
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Merge pull request #298 from lnis-uofu/micro_benchmarks
Micro benchmarks addition and testing for FPGAs with DSP blocks
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2021-04-24 17:55:38 -06:00 |
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tangxifan
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62dc5a3856
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[Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes
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2021-04-24 16:02:24 -06:00 |
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tangxifan
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b7da22501c
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[Test] Deply new test to regression test
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2021-04-24 15:55:05 -06:00 |
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tangxifan
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5adffad602
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[Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!!
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2021-04-24 15:49:53 -06:00 |
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tangxifan
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80f98328df
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[Test] Update test settings for architecture with fracturable DSP blocks
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2021-04-24 15:16:50 -06:00 |
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tangxifan
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8b8096f3a8
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[HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block
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2021-04-24 14:57:09 -06:00 |
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tangxifan
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a3a98fa21d
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[Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition
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2021-04-24 14:56:10 -06:00 |
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tangxifan
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148da80869
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[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes
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2021-04-24 14:53:29 -06:00 |