sample_arch:move cmos/rram variation to technology library XML nodes
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@ -13,13 +13,18 @@
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<logic_transistors pn_ratio="2" model_ref="M" vdd="0.9">
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<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
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<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
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<variation abs_variation="0.1" num_sigma="3"/>
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</logic_transistors>
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<io_transistors pn_ratio="2" model_ref="M" vdd="2.5">
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<nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
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<pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
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</io_transistors>
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<rram model_name="rram_mem" rlrs="1e4" rhrs="1e5"/>
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<rram model_name="rram_logic" rlrs="5e3" rhrs="20e6"/>
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<rram model_name="rram_mem" rlrs="1e4" rhrs="1e5">
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<variation abs_variation="0.1" num_sigma="3"/>
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</rram>
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<rram model_name="rram_logic" rlrs="5e3" rhrs="20e6">
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<variation abs_variation="0.1" num_sigma="3"/>
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</rram>
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</technology>
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<circuit_library>
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<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
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@ -239,10 +244,7 @@
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</openfpga_architecture>
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<openfpga_simulation_setting>
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<general sim_temp="25" post="false" captab="false" fast="true"/>
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<monte_carlo mc_sim="false" num_mc_points="2" cmos_variation="false" rram_variation="false">
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<cmos abs_variation="0.1" num_sigma="3"/>
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<rram abs_variation="0.1" num_sigma="3"/>
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</monte_carlo>
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<monte_carlo mc_sim="false" num_mc_points="2"/>
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<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
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<slew>
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<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
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