tangxifan
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43e78585ba
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add routing track naming function for unique modules
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2019-12-24 14:55:17 -07:00 |
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tangxifan
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a36cb676c2
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minor fix in ctags to include library source files
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2019-12-18 22:24:58 +08:00 |
Laboratory for Nano Integrated Systems (LNIS)
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ffe90b1da6
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Merge pull request #34 from LNIS-Projects/dev
Dev
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2019-12-04 19:26:14 -07:00 |
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tangxifan
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a04631305c
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remove legacy verilog utils functions
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2019-12-04 18:02:26 -07:00 |
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tangxifan
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73386dd1a9
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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c091b5ea99
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Merge pull request #33 from LNIS-Projects/dev
Remove legacy codes in FPGA-Verilog
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2019-12-04 16:57:19 -07:00 |
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tangxifan
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a176c253ee
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remove legacy codes in FPGA-Verilog: routing block generation
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2019-12-04 16:15:50 -07:00 |
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tangxifan
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95ea513339
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move refactored Verilog routing block generation functions to cpp files
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2019-12-04 16:09:27 -07:00 |
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tangxifan
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322228de43
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remove legacy codes in FPGA-Verilog
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2019-12-04 16:02:43 -07:00 |
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tangxifan
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0dd72999d5
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deleting legacy codes: fpga_verilog top-level function
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2019-12-04 15:55:16 -07:00 |
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tangxifan
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0daf170e45
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refactored all the new functions to new source files, ready to delete legacy codes
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2019-12-04 15:38:42 -07:00 |
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tangxifan
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13f964ea72
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add bitstream file format introduction
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2019-12-04 13:41:31 -07:00 |
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tangxifan
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40bddd4ed7
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add FPL'19 paper to documentation reference
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2019-12-04 12:05:30 -07:00 |
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tangxifan
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323c4fdc9a
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clean up documentation build warnings and add guidelines for port naming
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2019-12-04 11:59:10 -07:00 |
AurelienUoU
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09fd2afa9c
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Adding heterogeneous synthesis requirements
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2019-12-03 16:09:26 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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c14dd5e392
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Merge pull request #32 from LNIS-Projects/dev
Misc Updates on regression tests and clean-up flow run
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2019-12-03 15:41:47 -07:00 |
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AurelienUoU
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32176eb352
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Adding EPFL benchmark task for openfpga_flow
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2019-12-03 14:31:53 -07:00 |
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AurelienUoU
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4b4b38d4e8
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Update openfpga.sh to allow run-flow and simulation at the same time
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2019-12-03 14:07:10 -07:00 |
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AurelienUoU
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2f14716f13
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Adding DPRAM behavioural Verilog netlist and its TB
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2019-12-03 13:58:20 -07:00 |
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tangxifan
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099863a956
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make FPGA-X2P to be run conditionally
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2019-12-03 13:50:39 -07:00 |
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tangxifan
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eec64bb63f
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Merge pull request #31 from LNIS-Projects/dev
Update master with latest development version
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2019-12-02 17:52:03 -07:00 |
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tangxifan
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5b4ddfb3ce
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use adapt yosys Makefile for OpenFPGA framework
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2019-11-27 14:42:47 -07:00 |
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tangxifan
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1c7fdac3f2
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add CMakefile for yosys
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2019-11-27 14:42:18 -07:00 |
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tangxifan
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4d62dc1c3e
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Upgrade to yosys-0.9
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2019-11-27 14:40:39 -07:00 |
Ganesh Gore
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2b465cf153
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-11-22 16:03:04 -07:00 |
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tangxifan
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8cc72536d1
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minor bug fixing
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2019-11-22 15:54:14 -07:00 |
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tangxifan
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96733f9ea8
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add minor comments in task file for modelsim regression tests
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2019-11-16 22:34:03 -07:00 |
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Ganesh Gore
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e6d14c8bf5
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-11-16 19:20:51 -07:00 |
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Ganesh Gore
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3f235a16f9
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-11-16 19:14:34 -07:00 |
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Ganesh Gore
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6bb11918dc
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Updated modelsim and collected result
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2019-11-16 19:10:04 -07:00 |
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tangxifan
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a13f406918
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tweaking mcnc_big20 task run for modelsim
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2019-11-16 18:00:55 -07:00 |
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Ganesh Gore
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3c2055156a
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-11-16 16:12:30 -07:00 |
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Ganesh Gore
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bfb03af2c8
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Added run-task and run-flow functions
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2019-11-16 15:52:32 -07:00 |
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Ganesh Gore
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cb1c7a8030
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Added OpenFPGA bash function utility
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2019-11-16 13:19:00 -07:00 |
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Ganesh Gore
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00ec36c1af
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Added Modelsim error check in log
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2019-11-16 13:18:13 -07:00 |
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Ganesh Gore
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373dbe0718
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First draft for multithreaded Modelsim simulation
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2019-11-16 01:06:09 -07:00 |
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Ganesh Gore
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f05aede868
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Added task support for modelsim script
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2019-11-15 23:23:15 -07:00 |
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Ganesh Gore
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1c4acff79b
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-11-15 14:54:13 -07:00 |
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Ganesh Gore
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f52eaef622
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Updated flow script and skipped travis upload on failure test setup.
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2019-11-15 14:35:15 -07:00 |
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Ganesh Gore
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333d10c94c
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Added vpr_fpga_verilog_print_simulation_ini option
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2019-11-15 14:26:57 -07:00 |
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tangxifan
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4df6402241
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add python script for batch simulations
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2019-11-15 14:23:03 -07:00 |
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tangxifan
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0c2ad5ab5e
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critical bug fixed for some corner cases
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2019-11-13 20:45:41 -07:00 |
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tangxifan
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1291b99d66
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now make ini file generation more flexible: user can specify a name or use the default name
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2019-11-13 12:55:57 -07:00 |
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tangxifan
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d84cd66287
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refactored analysis SDC generator for grids
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2019-11-12 22:18:13 -07:00 |
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tangxifan
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6c58a4dd92
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refactored unused grid block SDC analysis generation
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2019-11-12 10:01:17 -07:00 |
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tangxifan
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8a57a29d2d
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refactoring analysis SDC generation for grids
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2019-11-11 22:38:11 -07:00 |
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tangxifan
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5f219b428c
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refactored analysis SDC generation for switch blocks
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2019-11-11 19:24:39 -07:00 |
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tangxifan
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876733f052
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now we use module manager to generate analysis SDC, being independent from VPR structures
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2019-11-10 21:15:34 -07:00 |
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tangxifan
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a849522be9
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refactored CB SDC analysis generation
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2019-11-10 20:15:16 -07:00 |
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tangxifan
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8e8e59b0ca
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give specific name to mux so that we can bind it to SDC generator
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2019-11-10 19:42:30 -07:00 |