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Merge pull request #31 from LNIS-Projects/dev 

Update master with latest development version
This commit is contained in:
tangxifan 2019-12-02 17:52:03 -07:00 committed by GitHub
parent 49a8273482 5b4ddfb3ce
commit eec64bb63f
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GPG Key ID: 4AEE18F83AFDEB23
596 changed files with 313148 additions and 4611 deletions
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2
.dockerignore Normal file
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@ -0,0 +1,2 @@
# Ignore everything
*

12
.gitignore vendored
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@ -32,7 +32,17 @@ vpr7_x2p/vpr/vpr
vpr7_x2p/printhandler/printhandlerdemo
vpr7_x2p/libarchfpga/read_arch
vpr7_x2p/pcre/pcredemo
ace2/ace
vpr7_x2p/libpcre/pcredemo
vpr7_x2p/libprinthandler/printhandlerdemo
vpr7_x2p/vpr/vpr_shell
# Some local temporary files
.vscode
*_local.bat
*_local.bat
fpga_flow/csv_rpts
tmp/
build/
message.txt
deploy_key

66
.travis.yml
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@ -1,6 +1,17 @@
language: cpp
# Currently sudo is not required, NO ENV is used
# cache results
cache:
directories:
- $TRAVIS_BUILD_DIR/abc
- $TRAVIS_BUILD_DIR/yosys
- $TRAVIS_BUILD_DIR/ace2
- $TRAVIS_BUILD_DIR/libs
- $HOME/.ccache
# - $HOME/deps
# Currently sudo is not required, NO ENV is used
# Supported Operating systems
#os:
@ -8,13 +19,11 @@ language: cpp
# - osx
# Create a matrix to branch the building environment
matrix:
allow_failures:
- os: osx
#dist: trusty
include:
- os: linux
# Compiler is specified in ./travis/common.sh
sudo: false
dist: bionic
compiler: g++-8
addons:
apt:
@ -35,8 +44,6 @@ matrix:
- fontconfig
- g++-8
- gcc-8
- g++-4.9
- gcc-4.9
- gdb
- git
- gperf
@ -56,25 +63,25 @@ matrix:
- valgrind
- zip
- qt5-default
- os: osx
osx_image: xcode10.2 # we target latest MacOS Mojave
sudo: true
compiler: gcc-4.9 # Use clang instead of gcc in MacOS
addons:
homebrew:
packages:
- bison
- cmake
- ctags
- flex
- fontconfig
- git
- gcc@6
- gcc@4.9
- gawk
- icarus-verilog
- libxml++
- qt5
# - os: osx
# osx_image: xcode10.2 # we target latest MacOS Mojave
# sudo: true
# compiler: gcc-4.9 # Use clang instead of gcc in MacOS
# addons:
# homebrew:
# packages:
# - bison
# - cmake
# - ctags
# - flex
# - fontconfig
# - git
# - gcc@6
# - gcc@4.9
# - gawk
# - icarus-verilog
# - libxml++
# - qt5
before_install:
- source .travis/common.sh
@ -84,8 +91,8 @@ install:
- mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
- |
if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz"
mkdir cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake
CMAKE_URL="https://cmake.org/files/v3.12/cmake-3.12.4-Linux-x86_64.tar.gz"
mkdir -p cmake && travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake
export PATH=${DEPS_DIR}/cmake/bin:${PATH}
echo ${PATH}
else
@ -93,7 +100,7 @@ install:
fi
- cmake --version
- cd -
- .travis/install.sh
- source .travis/install.sh
script:
- .travis/script.sh
@ -104,3 +111,6 @@ after_failure:
after_success:
- .travis/after_success.sh
notifications:
slack:
secure: L8tzicFh+EKcK21GBA2m3rQ3jmnDdqiRXIZcb0iqYlhT0V5asYvCqwlpPDUDV1wmBXqPgRJBI/jitAJlKFWu74pLTVc6FscUIDYM7S0DJfHEcufLknZx88lMmmV0IsYLQe3/s89tWoudMf1bNBo/8YWzLDffqUQ7s/rTPD9SWLppb01X0Xm158oDlA0rWETs35nuNFgJxWcSyIyIvnRNE3dHjzmBETUR9mYDsUSYlcOI44FMD8rE6emicdkqdn1zVxScobrl4Dt2bPsMfKopgIKK1x+38AuaqQa7t5F5ICnF0WfxmQ6/TcRNwIij0fDu68w/fcU8SyV+Ex5aZBKYUU7PG7ELTOq+q1geDoTlbguvFSIT4EzqErc4hbJmcUn79BKLhdjshZtGihKatntJx2faXYNYGFjwmnPFRYpqsozydztgMjzv4prZ5yoh7jhoDiGj44QcpXlQ9otM17JdfqveowMLHBYzATsxIRG93irZfXG/E3S8FvXg8mYOIEn8UK7H6i8VWL3JHlw8RbpLdNLswZOUlpEaDAeTm5tvYcw7FGH2nlZ2e5aXLxN6dTovSSRztQHbWdJTGG0N+xldBXcCiChmok4nXGReIkMc+99nZjRsiCB0R16tCNb25/p7NAVkItfVe1qRTzdnhi1hdE7LPURK4kxoFRJ6sFVuYjw=

3
.travis/after_failure.sh
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@ -9,4 +9,7 @@ travis_fold end after_failure.1
start_section "failure.tail" "${RED}Failure output...${NC}"
tail -n 1000 output.log
echo "Failed uploading files to LNIS Server"
scp -qCr $TRAVIS_BUILD_DIR/openfpga_flow/tasks/ u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/$TRAVIS_JOB_ID/
scp output.log u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/$TRAVIS_JOB_ID/
end_section "failure.tail"

7
.travis/common.sh
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@ -15,6 +15,7 @@ export -f travis_time_start
export -f travis_time_finish
function start_section() {
$SPACER
travis_fold start "$1"
travis_time_start
echo -e "${PURPLE}OpenFPGA${NC}: - $2${NC}"
@ -25,6 +26,7 @@ function end_section() {
echo -e "${GRAY}-------------------------------------------------------------------${NC}"
travis_time_finish
travis_fold end "$1"
$SPACER
}
# For Mac OS, we use g++ and gcc as default compilers
@ -34,10 +36,11 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
# export PATH="/usr/local/opt/bison/bin:/usr/local/bin:$PATH"
# export PATH="/usr/local/opt/qt/bin:$PATH"
# Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h
sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target /
else
sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted
else
# For linux, we use g++-8 and gcc-8 as default compilers
export CC=gcc-8
export CXX=g++-8
fi

33
.travis/install.sh
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@ -3,6 +3,39 @@
source .travis/common.sh
set -e
## Install necessary package which is not available on Travis CI
#export DEPS_DIR="${HOME}/deps"
#mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
## Install CMake
#if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
# export CMAKE_URL="https://cmake.org/files/v3.13/cmake-3.13.0-rc3-Linux-x86_64.tar.gz"
# mkdir -p cmake && travis_retry wget --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake
# export PATH=${DEPS_DIR}/cmake/bin:${PATH}
# echo ${PATH}
#else
# brew install cmake || brew upgrade cmake
#fi
# cmake --version
#
## Install latest iVerilog. Since no deb is provided, compile from source codes
#if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
# export IVERILOG_URL="https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz"
# travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${IVERILOG_URL}
# mkdir -p iverilog-10_3
# tar -xz v10_3.tar.gz
# cd iverlog-10_3
# sh autoconf.sh --prefix=${DEPS_DIR}/iverilog-10_3/bin
# ./configure --prefix=${DEPS_DIR}/iverilog-10_3/bin
# make -j4
# make check
# make install --prefix=${HOME}/iverilog-10_3/bin
# export PATH=${DEPS_DIR}/iverilog-10_3/bin:${PATH}
# echo ${PATH}
#fi
#iverilog -V
#cd -
# Git repo fixup
#start_section "environment.git" "Setting up ${YELLOW}git checkout${NC}"
#set -x

50
.travis/regression.sh
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@ -1,50 +0,0 @@
#!/bin/bash
# Regression test version 1.0
# Set variables
my_pwd=$PWD
fpga_flow_scripts=${my_pwd}/fpga_flow/scripts
vpr_path=${my_pwd}/vpr7_x2p/vpr
benchmark="test_modes"
include_netlists="_include_netlists.v"
compiled_file="compiled_$benchmark"
tb_formal_postfix="_top_formal_verification_random_tb"
verilog_output_dirname="${benchmark}_Verilog"
log_file="${benchmark}_sim.log"
new_reg_sh="my_regression.sh"
cd $fpga_flow_scripts
perl rewrite_path_in_file.pl -i $vpr_path/regression_verilog.sh -o $vpr_path/$new_reg_sh
cd $my_pwd
# Move to vpr folder
cd $vpr_path
# Remove former log file
rm -f $log_file
rm -f $compiled_file
# Start the script -> run the fpga generation -> run the simulation -> check the log file
source $new_reg_sh
iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
vvp $compiled_file -j 16 >> $log_file
result=`grep "Succeed" $log_file`
if ["$result" = ""]; then
result=`grep "Failed" $log_file`
if ["$result" = ""]; then
echo "Unexpected error, Verification didn't run"
cd $my_pwd
exit 1
else
echo "Verification failed"
cd $my_pwd
exit 2
fi
else
echo "Verification succeed"
cd $my_pwd
fi

42
.travis/script.sh
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@ -3,31 +3,35 @@
source .travis/common.sh
set -e
$SPACER
start_section "OpenFPGA.build" "${GREEN}Building..${NC}"
mkdir build
cd build
if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
#make
mkdir build
cd build
cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
make -j2
else
# For linux, we enable full package compilation
#make
mkdir build
cd build
cmake --version
cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
else
cmake .. -DCMAKE_BUILD_TYPE=debug
make -j16
fi
make -j16
end_section "OpenFPGA.build"
$SPACER
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd -
./.travis/regression.sh
echo -e "Testing single-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
#python3 openfpga_flow/scripts/run_fpga_task.py s298
#cd fpga_flow
#./regression_fpga_flow.sh
#cd -
echo -e "Testing multi-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py multi_mode --maxthreads 4 --debug --show_thread_logs
echo -e "Testing compact routing techniques";
python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs
echo -e "Testing tileable architectures";
python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --debug --show_thread_logs
echo -e "Testing Verilog generation with explicit port mapping ";
python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_thread_logs
end_section "OpenFPGA.TaskTun"

13
CMakeLists.txt
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@ -1,5 +1,11 @@
cmake_minimum_required(VERSION 2.8.12)
find_program(CCACHE_FOUND ccache)
if(CCACHE_FOUND)
set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE ccache)
set_property(GLOBAL PROPERTY RULE_LAUNCH_LINK ccache)
endif(CCACHE_FOUND)
if (${CMAKE_VERSION} VERSION_GREATER "3.8")
#For cmake >= 3.9 INTERPROCEDURAL_OPTIMIZATION behaviour we need to explicitly
#set the cmake policy version number
@ -176,6 +182,13 @@ set_target_properties(libace ace
LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/ace2"
RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/ace2")
# Set output locations to be in the main source tree under the relevant folder
set_target_properties(libini
PROPERTIES
ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/libs/external/libini"
LIBRARY_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/libs/external/libini"
RUNTIME_OUTPUT_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}/libs/external/libini")
# Set output locations to be in the main source tree under the relevant folder
set_target_properties(libvtrutil
PROPERTIES

20
Dockerfile
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@ -1,16 +1,16 @@
FROM ubuntu:16.04
RUN apt-get update -qq -y
RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev
RUN apt-get update -qq -y
RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev
RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gtkwave gperf iverilog libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default
RUN echo "git clone https://github.com/LNIS-Projects/OpenFPGA.git" >> build.sh
RUN echo "cd OpenFPGA" >> build.sh
RUN echo "mkdir -p build && cd build" >> build.sh
RUN echo "cmake .. -DCMAKE_BUILD_TYPE=debug" >> build.sh
RUN echo "make" >> build.sh
RUN chmod +x build.sh
RUN ./build.sh
RUN mkdir -p /release /dev
VOLUME /OpenFPGA
RUN cd release && git clone --single-branch --branch master https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA
RUN cd /release/OpenFPGA && mkdir build && cd build && cmake .. -DCMAKE_BUILD_TYPE=debug -DCMAKE_NO_GRAPHICS=on && make -j
RUN rm -rf /var/lib/apt/lists/*
WORKDIR /release/OpenFPGA

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1
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@ -0,0 +1 @@
_build/

11
docs/Makefile
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@ -3,11 +3,11 @@
# You can set these variables from the command line.
SPHINXOPTS =
SPHINXBUILD = sphinx-build-3.6
SPHINXBUILD = sphinx-build
SOURCEDIR = source
BUILDDIR = build
PAPER =
PAPER =
PAPEROPT_a4 = -D latex_paper_size=a4
PAPEROPT_letter = -D latex_paper_size=letter
ALL_SPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) $(SOURCEDIR)
@ -16,7 +16,10 @@ ALL_SPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) $(SO
help:
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
clean:
livehtml:
sphinx-autobuild -b html $(ALL_SPHINXOPTS) $(BUILDDIR)/html
clean:
rm -rf $(BUILDDIR)/*
.PHONY: help clean Makefile
@ -27,4 +30,4 @@ clean:
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
#html:
# $(SPHINXBUILD) -b html $@ "$(SOURCEDIR)" "$(BUILDDIR)/html" $(SPHINXOPTS)

125
docs/source/arch_lang/circuit_model_examples.rst
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@ -1,6 +1,6 @@
Circuit model examples
======================
The next subsections are dedicated to detailed examples of each circuit model type. Through these examples awe give a global overview of the different implementations which are available for the user.
The next subsections are dedicated to detailed examples of each circuit model type. Through these examples, we give a global overview of the different implementations which are available for the user.
Inverters and Buffers
---------------------
@ -13,15 +13,15 @@ Inverters and Buffers
<port type="output" prefix="string" size="int"/>
</circuit_model>
.. note:: customized SPICE netlists are not currently supported for inverters and buffers.
.. note:: customized Verilog/SPICE netlists are not currently supported for inverters and buffers.
* design_technology:
* **topology:** [inverter|buffer]. Specify the type of this component, can be either an inverter or a buffer.
* **topology:** [``inverter`` | ``buffer``]. Specify the type of this component, can be either an inverter or a buffer.
* **size:** Specify the driving strength of inverter/buffer. For a buffer, the size is the driving strength of the inverter at the second level. We consider a two-level structure for a buffer here. The support for multi-level structure of a buffer will be introduced in the tapered options.
* **tapered:** [on|off]. Define if the buffer is a tapered (multi-level) buffer. *If "on" the following parameter are required.*
* **tapered:** [``on`` | ``off``]. Define if the buffer is a tapered (multi-level) buffer. When ``on`` is defined, the following parameter are required.*
* **tap_drive_level:** Define the number of levels of a tapered buffer. This parameter is valid only when tapered is turned on.
@ -54,6 +54,21 @@ This example shows:
* Size of 1 for the output strength
* The tapered parameter is not declared and is off by default
**Power-gated Inverter x1 example**
The XML code describing an inverter which can be power-gated by the control signals ``EN`` and ``ENB`` :
.. code-block:: xml
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1">
<design_technology type="cmos" topology="inverter" size="3" tapered="off" power_gated="true"/>
<port type="input" prefix="in" size="1" lib_name="I"/>
<port type="input" prefix="EN" size="1" lib_name="EN" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="ENB" size="1" lib_name="ENB" is_global="true" default_val="1" is_config_enable="true"/>
<port type="output" prefix="out" size="1" lib_name="Z"/>
</circuit_model>
.. note:: For power-gated inverters: all the control signals must be set as ``config_enable`` so that the testbench generation will generate testing waveforms. If the power-gated inverters are auto-generated , all the ``config_enable`` signals must be ``global`` signals as well. If the pwoer-gated inverters come from user-defined netlists, restrictions on ``global`` signals are free.
**Buffer x2 example**
@ -128,11 +143,11 @@ Pass-gate Logic
<port type="output" prefix="string" size="int"/>
</circuit_model>
.. note:: customized SPICE netlists are not currently supported for pass-gate logics.
.. note:: customized Verilog/SPICE netlists are not currently supported for pass-gate logics.
* design_technology:
* **topology:** [transmission_gate|pass_transistor]. The transmission gate consists of a NMOS transistor and a PMOS transistor. The pass transistor consists of a NMOS transistor.
* **topology:** [``transmission_gate`` | ``pass_transistor``]. The transmission gate consists of a NMOS transistor and a PMOS transistor. The pass transistor consists of a NMOS transistor.
* **nmos_size:** the size of NMOS transistor in a transmission gate or pass_transistor, expressed in terms of the min_width defined in XML node <transistors>.
@ -163,7 +178,7 @@ The XML code describing this pass-gate is:
</circuit_model>
This example shows:
* Topology is **transmission_gate**, which means the component need entries for each transistor gate (pmos and nmos)
* Topology is ``transmission_gate``, which means the component need entries for each transistor gate (pmos and nmos)
* 3 inputs considered, 1 for signal and 2 to control the transistors gates
* No input or output buffer used, these parameters can be uninitialized
@ -191,7 +206,7 @@ The XML code describing this pass-gate is:
</circuit_model>
This example shows:
* Topology is **pass_transistor**, which means the component need an entry for the transistor gate (nmos)
* Topology is ``pass_transistor``, which means the component need an entry for the transistor gate (nmos)
* 2 inputs considered, 1 for signal and 1 to control the transistor gate
* No input or output buffer used, these parameters can be uninitialized
@ -209,9 +224,9 @@ SRAMs
<port type="output" prefix="string" size="int"/>
</circuit_model>
.. note:: The circuit designs of SRAMs are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-SPICE requires users to provide their customized SRAM SPICE/Verilog netlists. A sample SPICE netlist of SRAM can be found in the directory SpiceNetlists in the released package. FPGA-SPICE assumes that all the LUTs and MUXes employ the SRAM circuit design. Therefore, currently only one SRAM type is allowed to be defined.
.. note:: The circuit designs of SRAMs are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-Verilog/SPICE requires users to provide their customized SRAM Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of SRAM can be found in the directory SpiceNetlists in the released package. FPGA-Verilog/SPICE assumes that all the LUTs and MUXes employ the SRAM circuit design. Therefore, currently only one SRAM type is allowed to be defined.
.. note:: The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
.. note:: The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
.. note:: The support SRAM modules should have a BL and a WL when the memory-bank-style configuration circuit is declared. Note that the WL should be the write/read enable signal, while BL is the data input.
@ -230,9 +245,9 @@ Logic gates
.. note:: The circuit model in the type of gate aims to support direct mapping to standard cells or customized cells provided by technology vendors or users.
.. note:: The logic functionality of a gate can be defined through the XML keyword topology. Currently, OpenFPGA supports AND, OR and MUX2 gates. As for standard cells, the size of each port is limited to 1. Currently, only 2-input and single-output logic gates are supported.
.. note:: The logic functionality of a gate can be defined through the XML keyword ``topology``. Currently, OpenFPGA supports AND, OR and MUX2 gates. As for standard cells, the size of each port is limited to 1. Currently, only 2-input and single-output logic gates are supported.
.. note:: It may happen that the port sequence in generated Verilog netlists has conflicts with the port sequence in standard and customized cells. To avoid this, users can set the XML keyword dump_explicit_port_map to be true, which enables explicit port mapping are dumped. Users can specify the pin/port name in the standard cell library using the XML keyword lib_name.
.. note:: It may happen that the port sequence in generated Verilog netlists has conflicts with the port sequence in standard and customized cells. To avoid this, users can set the XML keyword ``dump_explicit_port_map`` to be true, which enables explicit port mapping are dumped. Users can specify the pin/port name in the standard cell library using the XML keyword ``lib_name``.
Multiplexers
------------
@ -240,8 +255,7 @@ Multiplexers
.. code-block:: xml
<circuit_model type="mux" name="string" prefix="string" is_default="int">
<design_technology type="string" structure="string" num_level="int" ron="float" roff="float"
prog_transistor_size="float"/>
<design_technology type="string" structure="string" num_level="int" add_const_input="string" const_input_val="int" local_encoder="string" ron="float" roff="float" prog_transistor_size="float"/>
<input_buffer exist="string" circuit_model_name="string"/>
<output_buffer exist="string" circuit_model_name="string"/>
<pass_gate_logic type="string" circuit_model_name="string"/>
@ -250,24 +264,31 @@ Multiplexers
<port type="sram" prefix="string" size="int"/>
</circuit_model>
.. note:: customized SPICE netlists are not currently supported for multiplexers.
.. note:: customized Verilog/SPICE netlists are not currently supported for multiplexers.
* design_technology:
* **structure:** can be [tree|multi-level|one-level]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5]. If *multi-level* the following parameter is required:
* **structure:** can be [``tree`` \| ``multi-level`` \| ``one-level``]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5]. If ``multi-level`` the following parameter is required:
* **num_level:** specify the number of levels when multi-level structure is selected, only.
* **add_const_input:** can be [``true`` \| ``false``]. When enabled, an extra input will be added to the multiplexer circuits defined in this ``circuit_model``. For example, an 4-input multiplexer will be turned to a 5-input multiplexer. The extra input will be wired to a constant value, which can be specified through the XML syntax ``const_input_val``. The constant value can be either 0 or 1 (By default it is 0). Note that adding such input will help reducing the leakage power of FPGA and parasitic signal activities, with a limited area overhead.
* **const_input_val:** specify the constant value, to which the extra input will be connected. This syntax is only valid when the ``add_const_input`` is set to true.
* **local_encoder:** can be [``true`` \| ``false``]. When enabled, an local encoder will be added to the multiplexer circuits defined in this ``circuit_model``. The local encoder will be interface the SRAM inputs of multiplexing structure and SRAMs. It can encode the one-hot codes (that drive the select port of multiplexing structure) to a binary code. For example, 8-bit ``00000001`` will be encoded to 3-bit ``000``. This will help reduce the number of SRAM cells used in FPGAs as well as configuration time (especially for scan-chain configuration protocols). But it may cost an area overhead.
* **prog_transistor_size:** valid only when the type of design technology is rram. Specify the size of programming transistors used in the RRAM-based multiplexer, we use only n-type transistor and the size should be expressed in terms of the min_width defined in XML node <transistors>.
.. note:: Local encoders are only applicable for one-level and multi-level multiplexers. Tree-like multiplexers are already encoded in their nature.
* If type of design technology is **rram**, then the following parameters are required:
* **prog_transistor_size:** valid only when the type of design technology is ``rram``. Specify the size of programming transistors used in the RRAM-based multiplexer, we use only n-type transistor and the size should be expressed in terms of the min_width defined in XML node ``transistors``. If type of design technology is ``rram``, then the following parameters are required:
* **ron:** valid only when the type of design technology is rram. Specify the on-resistance of the RRAM device used in the RRAM-based multiplexer.
* **roff:** valid only when the type of design technology is rram. Specify the off-resistance of the RRAM device used in the RRAM-based multiplexer.
* port: for a multiplexer, the three types of ports, input, output and sram should be defined.
* port: for a multiplexer, the three types of ports, ``input``, ``output`` and ``sram`` should be defined.
.. note:: For tree-like multiplexers, they can be built with standard cell MUX2. To enable this, users should define a ``circuit_model``, which describes a 2-input multiplexer (See details and examples in how to define a logic gate using ``circuit_model``. In this case, the ``circuit_model_name`` in the ``pass_gate_logic`` should be the name of MUX2 ``circuit_model``.
**Mux 1 level example**
@ -329,7 +350,7 @@ If we arbitrarily fix the number of Mux entries at 4, the following code could i
**This example shows:**
* The tree topology, 4 entries split in 2 2-to-1 Muxes then another one make the final selection.
* The possibility to select the input or output buffers
* The number of entries parametrized by *size* in input port-type.
* The number of entries parametrized by ``size`` in input port-type.
Look-Up Tables
--------------
@ -349,9 +370,9 @@ Look-Up Tables
<port type="sram" prefix="string" size="int" mode_select="true|false" circuit_model_name="string" default_val="0|1"/>
</circuit_model>
.. note:: The SPICE netlists of LUT can be auto-generated or customized.
.. note:: The Verilog/SPICE netlists of LUT can be auto-generated or customized.
The auto-generated LUTs are based on a tree-like multiplexer, whose gates of the transistors are used as the inputs of LUTs and the drains/sources of the transistors are used for configurable memories (SRAMs).
The LUT provided in customized SPICE netlist should have the same decoding methodology as the traditional LUT.
The LUT provided in customized Verilog/SPICE netlist should have the same decoding methodology as the traditional LUT.
Additional design parameters for LUTs:
@ -369,9 +390,9 @@ Instructions of defining design parameters:
* **pass_gate_logic:** Specify the pass-gates of the internal multiplexer, the same as the multiplexers.
* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist. To support customizable LUTs, each type of port contain special keywords. For input ports, the keyword tri_state_map aims to customize which inputs are fixed to constant values when the LUT is in fracturable modes. For example, tri_state_map="----11" indicates that the last two inputs will be fixed to be logic '1' when a 6-input LUT is in fracturable modes. The circuit_model_name of input port is used to specify which logic gates will be used to tri-state the inputs in fracturable LUT modes. It is required to use an AND gate to force logic '0' or an OR gate to force logic '1' for the input ports. For output ports, the keyword lut_frac_level is used to specify the level in LUT multiplexer tree where the output port are wired to. For example, lut_frac_level="4" in a fracturable LUT6 means that the output are potentially wired to the 4th stage of a LUT multiplexer and it is an output of a LUT4. The keyword lut_output_mask describes which fracturable outputs are used. For instance, in a 6-LUT, there are potentially four LUT4 outputs can be wired out. lut_output_mask="0,2" indicates that only the first and the thrid LUT4 outputs will be used in fracturable mode. Note that the size of the output port should be consistent to the length of lut_output_mask.
* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. To support customizable LUTs, each type of port contain special keywords. For input ports, the keyword tri_state_map aims to customize which inputs are fixed to constant values when the LUT is in fracturable modes. For example, ``tri_state_map`` ="----11" indicates that the last two inputs will be fixed to be logic '1' when a 6-input LUT is in fracturable modes. The circuit_model_name of input port is used to specify which logic gates will be used to tri-state the inputs in fracturable LUT modes. It is required to use an AND gate to force logic '0' or an OR gate to force logic '1' for the input ports. For output ports, the keyword lut_frac_level is used to specify the level in LUT multiplexer tree where the output port are wired to. For example, lut_frac_level="4" in a fracturable LUT6 means that the output are potentially wired to the 4th stage of a LUT multiplexer and it is an output of a LUT4. The keyword lut_output_mask describes which fracturable outputs are used. For instance, in a 6-LUT, there are potentially four LUT4 outputs can be wired out. lut_output_mask="0,2" indicates that only the first and the thrid LUT4 outputs will be used in fracturable mode. Note that the size of the output port should be consistent to the length of lut_output_mask.
* **SRAM port for mode selection:** To enable switch between different operating modes, the SRAM bits of a fracturable LUT consists of two parts: configuration memory and mode selecting. The SRAM port for mode selection is specified through the XML keyword mode_select. Note that the size of such SRAM port should be consistent to the number of 1s or 0s in the tri_state_map.
* **SRAM port for mode selection:** To enable switch between different operating modes, the SRAM bits of a fracturable LUT consists of two parts: configuration memory and mode selecting. The SRAM port for mode selection is specified through the XML keyword mode_select. Note that the size of such SRAM port should be consistent to the number of 1s or 0s in the ``tri_state_map``.
**LUT example**
@ -400,7 +421,7 @@ The code describing this LUT is:
</circuit_model>
**This example shows:**
* The difference between *input_buffer* and *lut_input_buffer* and that they are independent.
* The difference between ``input_buffer`` and ``lut_input_buffer`` and that they are independent.
* How each blocks is defined
Flip-Flops
@ -417,17 +438,19 @@ Flip-Flops
<port type="clock" prefix="string" size="int"/>
</circuit_model>
.. note:: The circuit designs of flip-flops are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-SPICE requires users to provide their customized FF SPICE/Verilog netlists. A sample SPICE netlist of FF can be found in the directory SpiceNetlists in the released package.
.. note:: The circuit designs of flip-flops are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-Verilog/SPICE requires users to provide their customized FF Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of FF can be found in the directory SpiceNetlists in the released package.
The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
FPGA-SPICE currently support only one clock domain in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1.
FPGA-Verilog/SPICE currently support only one clock domain in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1.
Instructions of defining design parameters:
* **circuit_model type:** can be ff or scff. FF is typical Flip-Flop, SCFF is Scan-Chain Flip-Flop
* **circuit_model type:** can be ``ff`` or ``scff``. FF is typical Flip-Flop, SCFF is Scan-Chain Flip-Flop
* **port:** three types of ports (input, output and clock) should be defined. If the user provides a customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
* **port:** three types of ports (``input``, ``output`` and ``clock``) should be defined. If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
.. note:: In a valid FPGA architecture, users should provide at least either a SCFF or a SRAM, so that the configurations can loaded to core logic.
**FF example**
@ -454,9 +477,9 @@ The code describing this FF is:
</circuit_model>
**This example shows:**
* Circuit model type as ff
* The verilog netlist file associated to this component *ff.v*
* 3 ports, *Set*, *Reset* and *clk*, defined as global
* Circuit model type as ``ff``
* The verilog netlist file associated to this component ``ff.v``
* 3 ports, ``Set``, ``Reset`` and ``clk``, defined as global
**SCFF example**
@ -481,9 +504,9 @@ The code describing this FF is:
</circuit_model>
**This example shows:**
* Circuit model type as scff
* The verilog netlist file associated to this component *scff.v*
* 1 port, *clk*, defined as global
* Circuit model type as ``scff``
* The verilog netlist file associated to this component ``scff.v``
* 1 port, ``clk``, defined as global
Hard Logics
-----------
@ -501,21 +524,21 @@ Hard Logics
.. note:: Hard logics are defined for non-configurable resources in FPGA architectures, such as adders, multipliers and RAM blocks.
Their circuit designs are highly dependent on the technology node and well optimized by engineers.
As more functional units are included in FPGA architecture, it is impossible to auto-generate these functional units [3].
Therefore, FPGA-SPICE requires users to provide their customized SPICE netlists. A sample SPICE netlist of a 1-bit adder can be found in the directory SpiceNetlists in the released package.
Therefore, FPGA-Verilog/SPICE requires users to provide their customized Verilog/SPICE netlists. A sample Verilog/SPICE netlist of a 1-bit adder can be found in the directory SpiceNetlists in the released package.
The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
Instructions of defining design parameters:
* **port:** two types of ports (input and output) should be defined. If the user provides a user-defined SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
* **port:** two types of ports (``input`` and ``output``) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
Routing Wire Segments
---------------------
FPGA-SPICE provides two types of SPICE models for the wire segments in FPGA architecture:
FPGA-Verilog/SPICE provides two types of Verilog/SPICE models for the wire segments in FPGA architecture:
* One type is called **wire**, which targets the local wires inside the logic blocks. The wire has one input and one output, directly connecting the output of a driver and the input of the downstream unit, respectively
* The other type is called **chan_wire**, especially targeting the channel wires. The channel wires have one input and two outputs, one of which is connected to the inputs of Connection Boxes while the other is connected to the inputs of Switch Boxes. Two outputs are created because from the view of layout, the inputs of Connection Boxes are typically connected to the middle point of channel wires, which has less parasitic resistances and capacitances than connected to the ending point.
* One type is called ``wire``, which targets the local wires inside the logic blocks. The wire has one input and one output, directly connecting the output of a driver and the input of the downstream unit, respectively
* The other type is called ``chan_wire``, especially targeting the channel wires. The channel wires have one input and two outputs, one of which is connected to the inputs of Connection Boxes while the other is connected to the inputs of Switch Boxes. Two outputs are created because from the view of layout, the inputs of Connection Boxes are typically connected to the middle point of channel wires, which has less parasitic resistances and capacitances than connected to the ending point.
.. code-block:: xml
@ -528,19 +551,19 @@ FPGA-SPICE provides two types of SPICE models for the wire segments in FPGA arch
<wire_param model_type="string" res_val="float" cap_val="float" level="int"/>
</circuit_model>
.. note:: FPGA-SPICE can auto-generate the SPICE model for wires while also allows users to provide their customized SPICE netlists.
.. note:: FPGA-Verilog/SPICE can auto-generate the Verilog/SPICE model for wires while also allows users to provide their customized Verilog/SPICE netlists.
The information of input and output buffer should be clearly specified according to the customized netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
Instructions of defining design parameters:
* **type:** can be [wire|chan_wire]. The SPICE model wire targets the local wire inside the logic block while the chan_wire targets the channel wires in global routing.
* **type:** can be [``wire`` | ``chan_wire``]. The Verilog/SPICE model wire targets the local wire inside the logic block while the chan_wire targets the channel wires in global routing.
* **port:** two types of ports (input and output) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
* **port:** two types of ports (``input`` and ``output``) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
* **wire_param:**
* **model_type:** can be [pi|T], corresponding to the π-type and T-type RC wire models.
* **model_type:** can be [``pi`` | ``T``], corresponding to the π-type and T-type RC wire models.
* **res_val:** specify the total resistance of the wire
* **cap_val:** specify the total capacitance of the wire.
* **level:** specify the number of levels of the RC wire model.
@ -569,8 +592,8 @@ The code describing this wire is:
</circuit_model>
**This example shows**
* How to use the *wire_param* for a π-type RC wire model
* How to use this circuit_model to auto-generate the SPICE netlist
* How to use the ``wire_param`` for a π-type RC wire model
* How to use this circuit_model to auto-generate the Verilog/SPICE netlist
I/O pads
--------
@ -588,13 +611,13 @@ I/O pads
</circuit_model>
.. note:: The circuit designs of I/O pads are highly dependent on the technology node and well optimized by engineers.
Therefore, FPGA-SPICE requires users to provide their customized SPICE/Verilog netlists. A sample SPICE netlist of an I/O pad can be found in the directory SpiceNetlists in the released package.
Therefore, FPGA-Verilog/SPICE requires users to provide their customized Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of an I/O pad can be found in the directory SpiceNetlists in the released package.
The information of input and output buffer should be clearly specified according to the customized netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
Instructions of defining design parameters:
* **port:** two types of ports (input and output) should be defined. If the user provides a user-defined SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
* **port:** four types of ports (``input``, ``output``, ``inout`` and ``sram``) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
**IO-pad example**
@ -622,6 +645,6 @@ The code describing this IO-Pad is:
**This example shows**
* The association of the verilog netlist file *io.v*
* The association of the verilog netlist file ``io.v``
* The inout pad port_type, which means as inout as output.
* The instantiation of a SCFF as sram

42
docs/source/arch_lang/circuit_modules.rst
View File

@ -1,10 +1,10 @@
Define Circuit-level Modules
============================
To support FPGA SPICE, Verily and Bitstream Generator, physical modules containing gate-level and transistor-level features are required for FPGA primitive blocks.
To support FPGA Verilog/SPICE, Verily and Bitstream Generator, physical modules containing gate-level and transistor-level features are required for FPGA primitive blocks.
The physical modules are defined in XML syntax, similar to the original VPR FPGA architecture description language.
For each module that appears in the FPGA architecture, a circuit model should be defined. In the definition of a circuit model, the user can specify if the SPICE netlist of the module is either auto-generated or user-defined.
For each module that appears in the FPGA architecture, a circuit model should be defined. In the definition of a circuit model, the user can specify if the Verilog/SPICE netlist of the module is either auto-generated or user-defined.
Define circuit_models
---------------------
@ -13,34 +13,34 @@ Define circuit_models
<module_circuit_models>
<circuit_model type="string" name="string" prefix="string" is_default="int"
spice_netlist="string" verilog_netlist="string" dump_structural_verilog="string">
circuit_netlist="string" verilog_netlist="string" dump_structural_verilog="string">
<transistor-level circuit_design_features="developped_further" />
</circuit_model>
</module_circuit_models>
* **module_circuit_models**: the father node for all the spice models. All the spice models should be defined under this XML node.
* **module_circuit_models**: the father node for all the circuit models. All the circuit models should be defined under this XML node.
* **circuit_model**: the child node defining transistor-level modeling parameters.
* **type**: can be [ inv_buf | pass_gate | mux | wire | chan_wire | sram | lut | ff | scff | hard_logic | iopad ]. Specify the type of circuit model. The provided types cover all the modules in FPGAs. For the circuit models in the type of mux/wire/chan_wire/lut, FPGA-SPICE can auto-generate SPICE netlists. For the rest, FPGA-SPICE requires a user-defined SPICE netlist.
* **type**: can be [ ``inv_buf`` | ``pass_gate`` | ``gate`` | ``mux`` | ``wire`` | ``chan_wire`` | ``sram`` | ``lut`` | ``ff`` | ``scff`` | ``hard_logic`` | ``iopad`` ]. Specify the type of circuit model. The provided types cover all the modules in FPGAs. For the circuit models in the type of mux/wire/chan_wire/lut, FPGA-Verilog/SPICE can auto-generate Verilog/SPICE netlists. For the rest, FPGA-Verilog/SPICE requires a user-defined Verilog/SPICE netlist.
* **name**: define the name of this circuit model. The name should be unique and will be used to create the sub-circuit of the circuit model in SPICE netlists. Note that for a customized SPICE netlist, the name defined here should be the name of the top-level sub-circuit in the customized SPICE netlist. FPGA-SPICE will check if the given name is conflicted with any reserved words.
* **name**: define the name of this circuit model. The name should be unique and will be used to create the sub-circuit of the circuit model in Verilog/SPICE netlists. Note that for a customized Verilog/SPICE netlist, the name defined here should be the name of the top-level sub-circuit in the customized Verilog/SPICE netlist. FPGA-Verilog/SPICE will check if the given name is conflicted with any reserved words.
* **prefix**: specify the name of the circuit_model to shown in the auto-generated SPICE netlists. The prefix can be the same as the name defined above. And again, the prefix should be unique.
* **prefix**: specify the name of the circuit_model to shown in the auto-generated Verilog/SPICE netlists. The prefix can be the same as the name defined above. And again, the prefix should be unique.
* **is_default**: can be [1|0], corresponding to [true|false] respectively. Specify this circuit model is the default one for some modules, such as multiplexers. If a module is not linked to any spice model by users, FPGA-SPICE will find the default spice model defined in the same type and link. For a spice model type, only one spice model can be set as default.
* **is_default**: can be [``1`` | ``0``], corresponding to [``true`` | ``false``] respectively. Specify this circuit model is the default one for some modules, such as multiplexers. If a module is not linked to any circuit model by users, FPGA-Verilog/SPICE will find the default circuit model defined in the same type and link. For a circuit model type, only one circuit model can be set as default.
* **spice_netlist**: specify the path and file name of a customized SPICE netlist. For some modules such as SRAMs, FFs, inpads, and outpads, FPGA-SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined.
* **circuit_netlist**: specify the path and file name of a customized Verilog/SPICE netlist. For some modules such as SRAMs, FFs, inpads, and outpads, FPGA-Verilog/SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-Verilog/SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined.
* **verilog_netlist**: specify the path and file name of a customized Verilog netlist. For some modules such as SRAMs, FFs, inpad and outpads, FPGA-SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined.
* **verilog_netlist**: specify the path and file name of a customized Verilog netlist. For some modules such as SRAMs, FFs, inpad and outpads, FPGA-Verilog/SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-Verilog/SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined.
* **dump_structural_verilog**: when the value of this keyword is set to be true, Verilog generator will output gate-level netlists of this module, instead of behavior-level. Gate-level netlists bring more opportunities in layout-level optimization while behavior-level is more suitable for high-speed formal verification and easier in debugging with HDL simulators.
.. note:: If netlist is not specified, FPGA-SPICE auto-generates the SPICE netlists for multiplexers, wires, and LUTs.
.. note:: If netlist is not specified, FPGA-Verilog/SPICE auto-generates the Verilog/SPICE netlists for multiplexers, wires, and LUTs.
.. note:: The user-defined netlists, such as LUTs, the decoding methodology should comply with the auto-generated LUTs (See Section 4.5)
.. note:: Under the XML node circuit_model, the features of transistor-level designs can be defined. In the following table, we show the common features supported for all the modules. Then, we will introduce unique features supported only for some spice models types.
.. note:: Under the XML node circuit_model, the features of transistor-level designs can be defined. In the following table, we show the common features supported for all the modules. Then, we will introduce unique features supported only for some circuit models types.
Transistor level
@ -67,19 +67,19 @@ Transistor level
* input_buffer and output_buffer:
* **exist:** [on|off]. Define the existence of the input_buffer or output_buffer. Note that the existence is valid for all the inputs and outputs. Note that if users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined SPICE netlist.
* **exist:** [on|off]. Define the existence of the input_buffer or output_buffer. Note that the existence is valid for all the inputs and outputs. Note that if users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined Verilog/SPICE netlist.
* **circuit_model_name:** Specify the name of circuit model which is used to implement input/output buffer, the type of specified circuit model should be inv_buf.
* pass_gate_logic: defined the parameters in pass-gates, which are used in building multiplexers and LUTs.
* **circuit_model_name:** Specify the name of the circuit model which is used to implement transmission gate, the type of specified spice model should be pass_gate.
* **circuit_model_name:** Specify the name of the circuit model which is used to implement transmission gate, the type of specified circuit model should be pass_gate.
* port: define the port list of a circuit model.
* **type:** can be [input|output|sram|clock]. For programmable modules, such as multiplexers and LUTs, SRAM ports should be defined. For registers, such as FFs and memory banks, clock ports should be defined.
* **prefix:** the name of the port. Each port will be shown as <prefix>[i], 0≤i<size in SPICE netlists.
* **prefix:** the name of the port. Each port will be shown as ``<prefix>[i]`` in Verilog/SPICE netlists.
* **size:** bandwidth of the port.
@ -87,12 +87,14 @@ Transistor level
* **circuit_model_name:** only valid when the type of port is sram. Specify the name of the circuit model which is connected to this port.
* **mode_select:** can be either true or false. Specify if this port controls the mode switching in a configurable logic block. Only valid when the type of this port is sram. (A configurable logic block can operate in different modes, which is controlled by SRAM bits.)
* **mode_select:** can be either ``true`` or ``false``. Specify if this port controls the mode switching in a configurable logic block. Only valid when the type of this port is sram. (A configurable logic block can operate in different modes, which is controlled by SRAM bits.)
* **is_global:** can be either true or false. Specify if this port is a global port, which will be routed globally. Note that when multiple global ports are defined with the same name, these global ports will be short-wired together.
* **is_global:** can be either ``true`` or ``false``. Specify if this port is a global port, which will be routed globally. Note that when multiple global ports are defined with the same name, these global ports will be short-wired together.
* **is_set:** can be either true or false. Specify if this port controls a set signal. Only valid when is_global is true. All the set ports are connected to global set voltage stimuli in testbenches.
* **is_set:** can be either ``true`` or ``false``. Specify if this port controls a set signal. Only valid when ``is_global`` is true. All the set ports are connected to global set voltage stimuli in testbenches.
* **is_reset:** can be either true or false. Specify if this port controls a reset signal. Only valid when is_global is true. All the reset ports are connected to a global reset voltage stimuli in testbenches.
* **is_reset:** can be either ``true`` or ``false``. Specify if this port controls a reset signal. Only valid when ``is_global`` is true. All the reset ports are connected to a global reset voltage stimuli in testbenches.
* **is_config_enable:** can be either true or false. Only valid when is_global is true. Specify if this port controls a configuration-enable signal. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the config_enable ports are connected to global configuration-enable voltage stimuli in testbenches.
* **is_config_enable:** can be either ``true`` or ``false``. Only valid when ``is_global`` is true. Specify if this port controls a configuration-enable signal. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches.
.. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of ``circuit_model`` for more details.

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@ -8,6 +8,8 @@ Extended Architecture Description Language
:maxdepth: 2
generality
interconnect
spice_sim_setting
@ -19,6 +21,4 @@ Extended Architecture Description Language
link_circuit_modules
.. multimode_support

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@ -0,0 +1,94 @@
Interconnection extensions
==========================
This section introduces extensions on the architecture description file about existing interconnection description.
Directlist
----------
The original direct connections in the directlist section are documented here_. Its description is given below:
.. _here: http://docs.verilogtorouting.org/en/latest/arch/reference/?highlight=directlist#direct-inter-block-connections
.. code-block:: xml
<directlist>
<direct name="string" from_pin="string" to_pin="string" x_offset="int" y_offset="int" z_offset="int" switch_name="string"/>
</directlist>
.. note:: These options are required
Our extension include three more options:
.. code-block:: xml
<directlist>
<direct name="string" from_pin="string" to_pin="string" x_offset="int" y_offset="int" z_offset="int" switch_name="string" interconnection_type="string" x_dir="string" y_dir="string"/>
</directlist>
.. note:: these options are optional. However, if *interconnection_type* is set *x_dir* and *y_dir* are required.
* **interconnection_type**: [``NONE`` | ``column`` | ``row``], specifies if it applies on a column or a row ot if it doesn't apply.
* **x_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives:
* x_dir="positive":
* interconnection_type="column": a column will be connected to a column on the **right**, if it exists.
* interconnection_type="row": the most on the **right** cell from a row connection will connect the most on the **left** cell of next row, if it exists.
* x_dir="negative":
* interconnection_type="column": a column will be connected to a column on the **left**, if it exists.
* interconnection_type="row": the most on the **left** cell from a row connection will connect the most on the **right** cell of next row, if it exists.
* **y_dir**: [``positive`` | ``negative``], specifies if the next cell to connect has a bigger or lower x value. Considering a coordinate system where (0,0) is the origin at the bottom left and *x* and *y* are positives:
* y_dir="positive":
* interconnection_type="column": the **bottom** cell of a column will be connected to the next column **top** cell, if it exists.
* interconnection_type="row": a row will be connected on an **above** row, if it exists.
* y_dir="negative":
* interconnection_type="column": the **top** cell of a column will be connected to the next column **bottom** cell, if it exists.
* interconnection_type="row": a row will be connected on a row **below**, if it exists.
Example
-------
For this example, we will study a scan-chain implementation. The description could be:
.. code-block:: xml
<directlist>
<direct name="scff_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0" interconnection_type="column" x_dir="positive" y_dir="positive"/>
</directlist>
:numref:`fig_p2p_exple` is the graphical representation of the above scan-chain description on a 4x4 FPGA.
.. _fig_p2p_exple:
.. figure:: ./figures/point2point_example.png
An example of scan-chain implementation
In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB.
Truth table
-----------
A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his point to point connection, a truth table with our new parameters id provided below.
:numref:`fig_p2p_trtable` provides all possible variable combination and the connection it will generate.
.. _fig_p2p_trtable:
.. figure:: ./figures/point2point_truthtable.png
Point to point truth table

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@ -1,6 +1,6 @@
Link circuit modules
--------------------
Each defined SPICE model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-SPICE creating the SPICE netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models.
Each defined circuit model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-circuit creating the circuit netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models.
SRAM
====
@ -30,7 +30,7 @@ To link the defined circuit model of SRAM into the FPGA architecture description
Example of a memory organization using memory decoders
.. note:: Currently SPICE only supports standalone memory organization.
.. note:: Currently circuit only supports standalone memory organization.
.. note:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator.
@ -45,7 +45,7 @@ Switch Boxes
=============
Original VPR architecture description contains an XML node called switchlist under which all the multiplexers of switch blocks are described.
To link a defined SPICE model to a multiplexer in the switch blocks, a new XML property circuit_model_name should be added to the descriptions.
To link a defined circuit model to a multiplexer in the switch blocks, a new XML property circuit_model_name should be added to the descriptions.
Here is an example:
@ -59,10 +59,10 @@ Here is an example:
Connection Blocks
================
==================
To link the defined SPICE model of the multiplexer to the Connection Blocks, a circuit_model_name should be added to the definition of Connection Blocks switches. However, the original architecture descriptions do not offer a switch description for connection boxes as they do for the switch blocks.
Therefore, FPGA-SPICE requires a new XML node called **cblock** under the root XML node architecture, where a switch for connection blocks can be defined.
To link the defined circuit model of the multiplexer to the Connection Blocks, a circuit_model_name should be added to the definition of Connection Blocks switches. However, the original architecture descriptions do not offer a switch description for connection boxes as they do for the switch blocks.
Therefore, FPGA-circuit requires a new XML node called **cblock** under the root XML node architecture, where a switch for connection blocks can be defined.
Here is the example:
@ -87,30 +87,98 @@ Similar to the Switch Boxes and Connection Blocks, the channel wire segments in
* circuit_model_name: should match a circuit model whose type is chan_wire defined under module_circuit_models.
Primitive Blocks inside Configurable Logic Blocks
=================================================
Primitive Blocks inside Multi-mode Configurable Logic Blocks
=============================================================
The architecture description employs a hierarchy of pb_types to depict the sub-modules and complex interconnections inside logic blocks. Each leaf node and interconnection in the pb_type hierarchy should be linked to a circuit model.
The architecture description employs a hierarchy of ``pb_types`` to depict the sub-modules and complex interconnections inside logic blocks. Each leaf node and interconnection in the pb_type hierarchy should be linked to a circuit model.
Each primitive block, i.e., the leaf ``pb_types``, should be linked to a valid circuit model, using the XML syntax ``circuit_model_name``.
The ``circuit_model_name`` should match the given name of a ``circuit_model`` defined by users.
.. code-block:: xml
<pb_type name="clb" idle_mode_name="ble" physical_mode_name="ble">
<pb_type name="ble">
<pb_type name="lut" circuit_model_name="lut6">
<pb_type name="ff" circuit_model_name="dff">
<!-- Multi-mode BLE -->
<pb_type name="ble" num_pb="10" physical_mode_name="ble_phy"/>
<!-- Physical implementation of BLE shown in Fig. :ref:`` -->
<mode name="ble_phy" disabled_in_packing="true"/>
<!-- Define a 6-input LUT in BLE and link it to circuit model -->
<pb_type name="flut6_phy" circuit_model_name="frac_lut6">
<input name="in" num_pins="6"/>
<output name="lut4_out" num_pins="4"/>
<output name="lut5_out" num_pins="2"/>
<output name="lut6_out" num_pins="1"/>
</pb_type>
<pb_type name="lut4_phy" circuit_model_name="lut4">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
</pb_type>
<pb_type name="adder_phy" num_pb="2" circuit_model_name="adder">
<input name="a" num_pins="1"/>
<input name="b" num_pins="1"/>
<input name="cin" num_pins="1"/>
<output name="cout" num_pins="1"/>
<output name="sumout" num_pins="1"/>
</pb_type>
<pb_type name="ff_phy" num_pb="2" circuit_model_name="dff">
<input name="D" num_pins="1"/>
<output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/>
</pb_type>
<interconnect>
<mux input="lut.out ff.Q" output="ble.out" circuit_model_name="mux_1level">
<!-- Routing multiplexers are omitted in this example. -->
</interconnect>
</pb_type>
<interconnect>
<mux input="ble.out clb.in" output="ble.in" circuit_model_name="mux_2level">
</interconnect>
</mode>
<!-- Arithmetic mode of BLE shown in Fig. 2(b)-->
<mode name="flut4_arithmetic"/>
<pb_type name="flut4_arith" num_pb="4"/>
<!-- Define a virtual 4-input LUT in BLE and link it to physical 6-input LUT defined at LINE 6 -->
<pb_type name="lut4" mode_bits="01" physical_pb_type_name="flut6_phy">
<!-- Define an input port and link it to its physical port defined at LINE 7 -->
<input name="in" num_pins="4" physical_mode_pin="in[3:0]"/>
<!-- Define an output port and link it to its physical port defined at LINE 8 -->
<output name="out" num_pins="1" physical_mode_pin="lut4_out"/>
</pb_type>
<pb_type name="adder" num_pb="2" physical_pb_type_name="adder_phy">
<input name="a" num_pins="1" physical_mode_pin="a"/>
<input name="b" num_pins="1" physical_mode_pin="b"/>
<input name="cin" num_pins="1" physical_mode_pin="cin"/>
<output name="cout" num_pins="1" physical_mode_pin="cout"/>
<output name="sumout" num_pins="1" physical_mode_pin="sumout"/>
</pb_type>
<pb_type name="ff" num_pb="2" physical_pb_type_name="ff_phy">
<input name="D" num_pins="1" physical_mode_pin="D"/>
<output name="Q" num_pins="1" physical_mode_pin="Q"/>
<clock name="clk" num_pins="1" physical_mode_pin="clk"/>
</pb_type>
<interconnect>
<!-- Routing multiplexers are omitted in this example. Full details can be found in [21] -->
</interconnect>
</pb_type>
</mode>
<!-- More operating modes can be defined -->
</pb_type>
* **circuit_model_name:** should match a SPICE model defined under module_circuit_models. For the interconnection type direct, the type of the linked SPICE model should be wire. For mux, the type of linked SPICE model should be mux. For complete, the type of the linked SPICE model can be either mux or wire, depending on the case.
* **physical_mode_name:** tell the name of the mode that describes the physical implementation of the configurable block. This is critical in modeling actual circuit designs and architecture of an FPGA. Typically, only one physical_mode should be specified for each multi-mode ``pb_type``.
* **idle_mode_name:** tell the name of the mode that the pb_type is configured to be by default. This is critical in building SPICE netlists for unused logic blocks.
* **idle_mode_name:** tell the name of the mode that the ``pb_type`` is configured to be by default. This is critical in building circuit netlists for unused logic blocks.
* **physical_mode_name:** tell the name of the mode that describes the physical implementation of the block. This is critical in modeling actual circuit designs and architecture of an FPGA.
* **circuit_model_name:** should match a circuit model defined under ``module_circuit_models``. The ``circuit_model_name`` is mandatory for every leaf ``pb_type`` in a physical_mode ``pb_type``. For the interconnection type direct, the type of the linked circuit model should be wire. For multiplexers, the type of linked circuit model should be ``mux``. For complete, the type of the linked circuit model can be either ``mux`` or ``wire``, depending on the case.
* **mode_bits** specifies the configuration bits for the ``circuit_model`` when operating at an operating mode. The length of ``mode_bits`` should match the ``port`` size defined in ``circuit_model``. The ``mode_bits`` should be derived from circuit designs while users are responsible for its correctness. FPGA-Bitstreamm will add the ``mode_bits`` during bitstream generation.
* **physical_pb_type_name** creates the link on ``pb_type`` between operating and physical modes. This syntax is mandatory for every leaf ``pb_type`` in an operating mode ``pb_type``. It should be a valid name of leaf ``pb_type`` in physical mode.
* **physical_pb_type_index_factor** aims to align the indices for ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_pb_type_name`` is larger than 1, the index of ``pb_type`` will be multipled by the given factor.
* **physical_pb_type_index_offset** aims to align the indices for ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_pb_type_name`` is larger than 1, the index of ``pb_type`` will be shifted by the given factor.
* **physical_mode_pin** creates the linke on ``port`` of ``pb_type`` between operating and physical modes. This syntax is mandatory for every leaf ``pb_type`` in an operating mode ``pb_type``. It should be a valid ``port`` name of leaf ``pb_type`` in physical mode and the port size should also match.
* **physical_mode_pin_rotate_offset** aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset.
.. note::
It is highly recommended that only one physical mode is defined for a multi-mode configurable block. Try not to use nested physical mode definition. This will ease the debugging and lead to clean XML description.
.. note::
Be careful in using ``physical_pb_type_index_factor``, ``physical_pb_type_index_offset`` and ``physical_mode_pin_rotate_offset``! Try to avoid using them unless for highly complex configuration blocks with very deep hierarchy.

4
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@ -1,4 +0,0 @@
Modeling Physical Design of Multi-mode Configurable Logic Block Architectures
=============================================================================
Under construction

7
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@ -19,7 +19,7 @@ import shlex
import sphinx_rtd_theme
# Uncomment for local build
# Uncomment for local build
#html_theme = "sphinx_rtd_theme"
#html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
@ -55,7 +55,8 @@ extensions = [
'sphinx.ext.todo',
'sphinx.ext.mathjax',
'sphinx.ext.graphviz',
'sphinxcontrib.bibtex'
'sphinxcontrib.bibtex',
'sphinx.ext.autosectionlabel',
]
# Add any paths that contain templates here, relative to this directory.
@ -89,7 +90,7 @@ pygments_style = 'sphinx'
# If true, `todo` and `todoList` produce output, else they produce nothing.
todo_include_todos = True
#Number figures for referencing
# Number figures for referencing
numfig = True

11
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@ -12,10 +12,15 @@ Welcome to OpenFPGA's documentation!
motivation
.. toctree::
:caption: Getting Started
:caption: Getting Started
eda_flow
run_fpga_flow
run_fpga_task
.. toctree::
:maxdepth: 2
:caption: Tools Guide
@ -37,10 +42,10 @@ Welcome to OpenFPGA's documentation!
.. toctree::
:maxdepth: 2
:caption: Appendix
contact
reference
For more information on the VTR see vtr_doc_ or vtr_github_
For more information on the Yosys see yosys_doc_ or yosys_github_

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@ -15,7 +15,7 @@ In this manual, we will introduce how to use FPGA-SPICE to conduct an accurate p
In the appendix, we introduce the hierarchy of the generated SPICE netlists and testbenches, to help you customize the SPICE netlists. We also attach an example of an architecture XML file for your interest.
The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015`.
The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015` and TVLSI'19 paper :cite:`XTang_TVLSI_2019`.
FPGA-Verilog
------------
@ -24,7 +24,9 @@ On a second note, it is becoming more and more necessary to have fast access to
This motivates us to generate the Verilog code of the architecture to enable a second level of research concerning the architectures to be explored. This Verilog code encompasses the whole design and is divided into multiple sub-directories for targetted analysis or a global one. This is left to the choice of the user.
In this manual, we present FPGA-Verilog. This extension enables the generation of a fully functional Verilog code enabling a deeper understanding of the architectures of the FPGAs. We introduce different options to this module to do the verification of the system. This will be presented in more depth in the FPGA-Bitstream section
In this manual, we present FPGA-Verilog. This extension enables the generation of a fully functional Verilog code enabling a deeper understanding of the architectures of the FPGAs. We introduce different options to this module to do the verification of the system. This will be presented in more depth in the FPGA-Bitstream section.
The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019`.
FPGA-Bitstream
--------------

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@ -0,0 +1,183 @@
.. _run_fpga_flow:
OpenFPGA Flow
---------------
This python script executes the supported OpenFPGA flow for a
single benchmark and architecture file for given script parameters.
The script is located at::
${OPENFPGA_PATH}/openfpga_flow/scripts/run_fpga_flow.py
.. program:: run_fpga_flow.py
Basic Usage
~~~~~~~~~~~
At a minimum ``open_fpga_flow.py`` requires following command-line arguments::
open_fpga_flow.py <architecture_file> <benchmark_files> --top_module <top_module_name>
where:
* ``<architecture_file>`` is the target :ref:`FPGA architecture <fpga_architecture_description>`
* ``<circuit_file>`` The list of files in the benchmark (Supports ../directory/\*.v)
* ``<top_module_name>`` The name of the top level module in Verilog project
.. note::
The script will create a ``tmp`` run directory in base OpenFPGA path, unless otherwise specified with the :option:`--run_dir` option.
All stages of the flow will be run within run directory.
Several intermediate files will be generated and maintian in run directory.
The path variables declared in architecture XML file will be resolved with absolute path and copied to the ``tmp/arch`` directory before executing flow.
All the benchmark files provided will be copied to ``tmp/bench`` directory without maintaining any directory structure.
**Users should ensure that no important files are kept in this directory as script will clear directory before each execution**
.. _openfpga-variables:
OpenFPGA Variables
~~~~~~~~~~~~~~~~~~
Frequently, while running OpenFPGA flow User is suppose to refer external files.
To avoid long names and referencing errors user can use
following openfpga variables.
These variables are resolved with absolute path while execution making
each run independent of launch directory.
* ``<OPENFPGA_PATH>`` Path to the base OpenFPGA directory
* ``<OPENFPGA_FLOW_PATH>`` Path to the run_fpga_flow script directory
* ``<SPICENETLIST_PATH>`` Path where spice netlists are saved
* ``<VERILOG_PATH>`` Path where Verilog modules are saved
* ``<TECH_PATH>`` Path where all characterized XML files are stored
For example in architecture file path vairable can be used as follows::
.... lib_path="${TECH_PATH}/PTM_45nm/45nm.pm" ....
Output
~~~~~~
Based on which flow is executed, resulting in intermediate files are generated in run_directory
The output log of the script provides the status of each stage to the user.
If any stage failed to execute, the output log would indicate the stage at which execution failed, and execution traceback.
In case of successful execution, The OpenFPGA flow script will parse
parameters listed in configuration from different result files and will create
``vpr_stat.txt``, ``vpr_stat_power.txt`` \(optional\) file in run_directory.
Advanced Usage
~~~~~~~~~~~~~~
User can pass additional *optional* command arguments to ``run_fpga_flow.py`` script::
run_fpga_flow.py <architecture_file> <benchmark_files> [<options>] [<vpr_options>] [<fpga-verilog_options>] [<fpga-spice_options>] [<fpga-bitstream_options>] [<ace_options>]
where:
* ``<options>`` are additional arguments passed to ``run_fpga_flow.py`` (described below),
* ``<vpr_options>`` Any argument prefixed with ``--vpr-*`` will be forwarded to vpr script as it is. The detail of supported vpr argument is available ``Add corrrect reference``
* ``<fpga-verilog_options>`` are any arguments not recognized by ``run_vtr_flow.pl``. These will be forwarded to VPR.
* ``<ace_options>`` these arguments will be passed to ACE activity estimator program
For example::
run_fpga_flow.py my_circuit.v my_arch.xml -track_memory_usage --pack --place
will run the VTR flow to map the circuit ``my_circuit.v`` onto the architecture ``my_arch.xml``; the arguments ``--pack`` and ``--place`` will be passed to VPR (since they are unrecognized arguments to ``run_vtr_flow.pl``).
They will cause VPR to perform only :ref:`packing and placement <general_options>`.
Detailed Command-line Options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. Note:: All the commnadline arguments starting with ``vpr_*`` , ``fpga-verilog_*`` , ``fpga-spice_*`` or ``fpga-bitstream_*`` will be passed to VPR without suffix
General Arguments
^^^^^^^^^^^^^^^^^
.. option:: --top_module <name>
Provide top module name of the benchmark. Default ``top``
.. option:: --run_dir <directory_path>
Using this option user can provide a custom path as a run directory. Default is ``tmp`` directory in OpenFPGA root path.
.. option:: --K <lut_inputs>
This option defines the number of inputs to the LUT. By default, the script parses provided architecture file and finds out inputs to the biggest LUT.
.. option:: --yosys_tmpl <yosys_template_file>
This option allows the user to provide a custom Yosys template
While running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_FILE`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables, which can be used as ``${var_name}``. Alternately, user can create a copy and modify according to their need.
.. option:: --debug
To enable detailed log printing.
.. option:: --flow_config
User can provide option flow configuration file to override some of the default script parameters.
for detail information refer :ref:`OpenFPGA Flow Configuration <OpenFPGA_Conf_File>`
ACE Arguments
^^^^^^^^^^^^^
.. option:: --black_box_ace
Performs ACE simulation on the black box [deprecated]
VPR RUN Arguments
^^^^^^^^^^^^^^^^^
.. option:: --fix_route_chan_width <channel_number>
Performs VPR implementation for a fixed number of channels defined as the 'channel_number'
.. option:: --min_route_chan_width <percentage_slack>
Performs VPR implementation to get minimum channel width and then perform fixed channel rerouting with ``percentage_slack`` increase in the channel width.
.. option:: --max_route_width_retry <max_retry_count>
Number of times the channel width should be increased and attempt VPR implementation, while performing ``min_route_chan_width``
.. option:: --power
.. option:: --power_tech
blif_vpr_flow Arguments
^^^^^^^^^^^^^^^^^^^^^^^^
.. option:: --activity_file
Activity to be used for the given benchmark while running ``blif_vpr_flow``
.. option:: --base_verilog
Verilog benchmark file to perform verification while running ``bliff_vpr_flow``
.. _OpenFPGA_Conf_File:
OpenFPGA Flow Configuration file
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The OpenFPGA Flow configuration file consists of following sections
* ``CAD_TOOLS_PATH``
Lists executable file path for different CAD tools used in the script
* ``FLOW_SCRIPT_CONFIG``
Lists the supported flows by the script.
* ``DEFAULT_PARSE_RESULT_VPR``
List of default parameters to be parsed from Place, Pack, and Route output
* ``DEFAULT_PARSE_RESULT_POWER``
List of default parameters to be parsed from VPR power analysis output
* ``INTERMIDIATE_FILE_PREFIX``
[Not implemented yet]
Default OpenFPGA_flow Configuration file is located in ``open_fpga_flow\misc\fpgaflow_default_tool_path.conf``.
User-supplied configuration file overrides or extends the default configuration.

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@ -0,0 +1,244 @@
.. _run_fpga_task:
OpenFPGA Task
---------------
Tasks provide a framework for running the :ref:`run_fpga_flow` on
multiple benchmarks, architectures, and set of OpenFPGA parameters.
The structure of the framework is very similar to
`VTR-Tasks <https://docs.verilogtorouting.org/en/latest/vtr/tasks/>`_
implementation with additional functionality and minor file extension changes.
Task Directory
~~~~~~~~~~~~~~
The tasks are stored in a ``TASK_DIRECTORY``, which by default points to
``${OPENFPGA_PATH}/openfpga_flow/tasks``. Every directory or sub-directory in
task directory consisting of ``../config/task.conf`` file can be referred to as a
task.
To create as task name called ``basic_flow`` following directory has to exist::
${TASK_DIRECTORY}/basic_flow/conf/task.conf
Similarly ``regression/regression_quick`` expect following structure::
${TASK_DIRECTORY}/regression/regression_quick/conf/task.conf
Running OpenFPGA Task:
~~~~~~~~~~~~~~~~~~~~~~
At a minimum ``open_fpga_flow.py`` requires following command-line arguments::
open_fpga_flow.py <task1_name> <task2_name> ... [<options>]
where:
* ``<task_name>`` is the name of the task to run
* ``<options>`` Other command line arguments described below
Command-line Options
~~~~~~~~~~~~~~~~~~~~
.. option:: --maxthreads <number_of_threads>
This option defines the number of threads to run while executing task.
Each combination of architecture, benchmark and set of OpenFPGA Flow options
runs in a individual thread.
.. option:: --skip_thread_logs
Passsing this option skips printing logs from each OpenFPGA Flow script run.
.. option:: --exit_on_fail
Passsing this option exits the OpenFPGA task script with returncode 1,
if any threads fail to execute successfully. It is mainly used to while
performing regression test.
.. option:: --test_run
This option allows to debug OpenFPGA Task script
by skiping actual execution of OpenFPGA flow .
Passing this option prints the list of
commnad generated to execute using OpenFPGA flow.
.. option:: --debug
To enable detailed log printing.
Creating a new OpenFPGA Task
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- Create the folder ``${TASK_DIRECTORY}/<task_name>``
- Create a file ``${TASK_DIRECTORY}/<task_name>/config/task.conf`` in it
- Configure the task as explained in :ref:`Configuring a new OpenFPGA Task`
Configuring a new OpenFPGA Task
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The task configuration file ``task.conf`` consists of ``GENERAL``,
``ARCHITECTURES``, ``BENCHMARKS``, ``SYNTHESIS_PARAM`` and
``SCRIPT_PARAM_<var_name>`` sections.
Declaring all the above sections are mandatory.
.. note::
The configuration file supports all the OpenFPGA Variables refer
:ref:`openfpga-variables` section to know more. Variable in the configuration
file is declared as ``${PATH:<variable_name>}``
General Section
^^^^^^^^^^^^^^^
.. option:: fpga_flow==<yosys_vpr|vpr_blif>
This option defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed.
.. option:: power_analysis=<true|false>
Specifies whether to perform power analysis or not.
.. option:: power_tech_file=<path_to_tech_XML_file>
Declares which tech XML file to use while performing Power Analysis.
.. option:: spice_output=<true|false>
Setting up this variable generates Spice Netlist at the end of the flow.
Equivalent of passing ``--vpr_fpga_spice`` command to :ref:`run_fpga_flow`
.. option:: verilog_output=<true|false>
Setting up this variable generates Verilog Netlist at the end of the flow.
Equivalent of passing ``--vpr_fpga_spice`` command to :ref:`run_fpga_flow`
.. option:: timeout_each_job=<true|false>
Specifies the timeout for each :ref:`run_fpga_flow` execution. Default is set to ``20 min. ``
Architectures Sections
^^^^^^^^^^^^^^^^^^^^^^
User can define the list of architecture files in this section.
.. option:: arch<arch_label>=<xml_architecture_file_path>
The ``arch_label`` variable can be any number of string without
white-spaces. ``xml_architecture_file_path`` is path to the actual XML
architecture file
.. note::
In the final OpenFPGA Task result, the architecture will be referred by its
``arch_label``.
Benchmarks Sections
^^^^^^^^^^^^^^^^^^^
User can define the list of benchmarks files in this section.
.. option:: bench<bench_label>=<list_of_files_in_benchmark>
The ``bench_label`` variable can be any number of string without
white-spaces. ``xml_architecture_file_path`` is path to the actual XML
architecture file
For Example following code shows how to define a benchmarks,
with a single file, multiple files and files added from a specific directory.
.. code-block:: text
[BENCHMARKS]
# To declare single benchmark file
bench_design1=${BENCH_PATH}/design/top.v
# To declare multiple benchmark file
bench_design2=${BENCH_PATH}/design/top.v,${BENCH_PATH}/design/sub_module.v
# To add all files in specific directory to the benchmark
bench_design3=${BENCH_PATH}/design/top.v,${BENCH_PATH}/design/lib/*.v
.. note::
``bench_label`` is referred again in ``Synthesis_Param`` section to
provide additional information about benchmark
Synthesis Parameter Sections
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
User can define extra parameters for each benchmark in the
``BENCHMARKS`` sections.
.. option:: bench<bench_label>_top=<Top_Module_Name>
This option defines the Top Level module name for ``bench_label`` benchmark.
By default, the top-level module name is considered as a ``top``.
.. option:: bench<bench_label>_yosys_tmpl=<yosys_template_file>
[TODO]
.. option:: bench<bench_label>_chan_width=<chan_width_to_use>
In case of running fixed channel width routing for each benchmark,
this option defines the channel width to be used for ``bench_label``
benchmark
.. option:: bench<bench_label>_act=<activity_file_path>
In case of running ``blif_vpr_flow`` this option provides the activity files
to be used to generate testbench for ``bench_label`` benchmark
.. option:: bench<bench_label>_verilog=<source_verilog_file_path>
In case of running ``blif_vpr_flow`` with verification this option provides
the source Verilog design for ``bench_label`` benchmark to be used
while verification.
Script Parameter Sections
^^^^^^^^^^^^^^^^^^^^^^^^^
The script parameter section lists set of commnad line pararmeters to be passed to :ref:`run_fpga_flow` script. The section name is defines as ``SCRIPT_PARAM_<parameter_set_label>`` where `parameter_set_label` can be any word without white spaces.
The section is referred with ``parameter_set_label`` in the final result file.
For example following code Specifies the two sets (``Fixed_Routing_30`` and ``Fixed_Routing_50``) of :ref:`run_fpga_flow` arguments.
.. code-block:: text
[SCRIPT_PARAM_Fixed_Routing_30]
# Execute fixed routing with channel with 30
fix_route_chan_width=30
[SCRIPT_PARAM_Fixed_Routing_50]
# Execute fixed routing with channel with 50
fix_route_chan_width=50
Example Task Configuration File
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. code-block:: text
[GENERAL]
spice_output=false
verilog_output=false
power_analysis = true
power_tech_file = ${PATH:TECH_PATH}/winbond90nm/winbond90nm_power_properties.xml
timeout_each_job = 20*60
[ARCHITECTURES]
arch0=${PATH:ARCH_PATH}/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
[BENCHMARKS]
bench0=${PATH:BENCH_PATH}/MCNC_Verilog/s298/s298.v
bench1=${PATH:BENCH_PATH}/MCNC_Verilog/elliptic/elliptic.v
[SYNTHESIS_PARAM]
bench0_top = s298
bench1_top = elliptic
[SCRIPT_PARAM_Slack_30]
min_route_chan_width=1.3
[SCRIPT_PARAM_Slack_80]
min_route_chan_width=1.8

15
docs/source/z_reference.bib
View File

@ -38,7 +38,7 @@ month={Sept},}
@article{XTang_TCAS1_2016,
title={{A Study on the Programming Structures for RRAM-based FPGA Architectures}},
author={Tang, Xifan and Kim, Gain and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni},
author={X. Tang and Kim, Gain and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni},
journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
volume={63},
number={4},
@ -106,3 +106,16 @@ month={Sept},}
address = {New York, NY, USA},
keywords = {CAD, FPGA, architecture},
}
@ARTICLE{XTang_TVLSI_2019,
author={X. Tang and E. Giacomin and G. D. Micheli and P. Gaillardon},
journal={{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}},
title={{FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs}},
year={2019},
volume={27},
number={3},
pages={637-650},
doi={10.1109/TVLSI.2018.2883923},
ISSN={1063-8210},
month={March},
}

230
fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
View File

@ -164,7 +164,7 @@
<!-- Physical descriptions begin -->
<layout auto="1.0" tileable_routing="off"/>
<!--layout width="5" height="5" tileable_routing="off"/-->
<!--layout width="12" height="12" tileable_routing="off"/-->
<spice_settings>
<parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>
@ -201,8 +201,8 @@
<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
</transistors>
<module_spice_models>
<spice_model type="inv_buf" name="INV1X" prefix="INV1X" is_default="1">
<module_circuit_models>
<circuit_model type="inv_buf" name="INV1X" prefix="INV1X" is_default="1">
<design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
@ -212,9 +212,9 @@
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</spice_model>
<spice_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="2" f_per_stage="4"/>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
@ -223,9 +223,9 @@
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</spice_model>
<spice_model type="inv_buf" name="INV4X" prefix="INV4X" is_default="0" >
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="3" f_per_stage="4"/>
</circuit_model>
<circuit_model type="inv_buf" name="INV4X" prefix="INV4X" is_default="0" >
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
@ -234,9 +234,9 @@
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</spice_model>
<spice_model type="inv_buf" name="INV2X" prefix="INV2X" is_default="0" >
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="3" f_per_stage="4"/>
</circuit_model>
<circuit_model type="inv_buf" name="INV2X" prefix="INV2X" is_default="0" >
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
@ -245,9 +245,9 @@
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</spice_model>
<spice_model type="inv_buf" name="buf2" prefix="buf2" is_default="0" >
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="2" f_per_stage="2"/>
</circuit_model>
<circuit_model type="inv_buf" name="buf2" prefix="buf2" is_default="0" >
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="2"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
@ -256,8 +256,8 @@
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</spice_model>
<spice_model type="inv_buf" name="buf1" prefix="buf1" is_default="0" >
</circuit_model>
<circuit_model type="inv_buf" name="buf1" prefix="buf1" is_default="0" >
<design_technology type="cmos" topology="buffer" size="1" tapered="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
@ -267,8 +267,8 @@
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</spice_model>
<spice_model type="pass_gate" name="TGATEX1" prefix="TGATEX1" is_default="1">
</circuit_model>
<circuit_model type="pass_gate" name="TGATEX1" prefix="TGATEX1" is_default="1">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
@ -282,8 +282,8 @@
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
</spice_model>
<spice_model type="gate" name="OR2" prefix="OR2" is_default="1">
</circuit_model>
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="1">
<design_technology type="cmos" topology="OR"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
@ -296,135 +296,135 @@
<delay_matrix type="fall" in_port="a b" out_port="out">
10e-12 10e-12
</delay_matrix>
</spice_model>
<spice_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
</spice_model>
<spice_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
</spice_model>
<spice_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
<input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic spice_model_name="TGATEX1"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="1"/>
<port type="sram" prefix="sram" size="1"/>
<port type="output" prefix="out" size="1"/>
</spice_model>
<spice_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
<input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV4X"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV4X"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic spice_model_name="TGATEX1"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="1"/>
<port type="sram" prefix="sram" size="1"/>
<port type="output" prefix="out" size="1"/>
</spice_model>
<spice_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="1" dump_structural_verilog="true">
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="1" dump_structural_verilog="true">
<design_technology type="cmos" structure="one-level" add_const_input="true" const_input_val="1"/>
<input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV4X"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV4X"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic spice_model_name="TGATEX1"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="1"/>
<port type="sram" prefix="sram" size="1"/>
<port type="output" prefix="out" size="1"/>
</spice_model>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<spice_model type="ff" name="static_dff" prefix="dff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
<design_technology type="cmos"/>
<input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/>
<pass_gate_logic spice_model_name="TGATEX1"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</spice_model>
<spice_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
</circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/>
<lut_input_buffer exist="on" spice_model_name="buf2"/>
<lut_intermediate_buffer exist="on" spice_model_name="buf1" location_map="-1-1-"/>
<lut_input_inverter exist="on" spice_model_name="INV2X"/>
<pass_gate_logic spice_model_name="TGATEX1"/>
<port type="input" prefix="in" size="6" tri_state_map="----11" spice_model_name="OR2"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<lut_input_buffer exist="on" circuit_model_name="buf2"/>
<lut_intermediate_buffer exist="on" circuit_model_name="buf1" location_map="-1-1-"/>
<lut_input_inverter exist="on" circuit_model_name="INV2X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
<port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="64"/>
<port type="sram" prefix="mode" size="2" mode_select="true" spice_model_name="sc_dff_compact" default_val="1"/>
</spice_model>
<spice_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
</circuit_model>
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/>
<lut_input_inverter exist="on" spice_model_name="INV1X"/>
<lut_intermediate_buffer exist="on" spice_model_name="buf1" location_map="-1-"/>
<lut_input_buffer exist="on" spice_model_name="buf2"/>
<pass_gate_logic spice_model_name="TGATEX1"/>
<port type="input" prefix="in" size="4" tri_state_map="--11" spice_model_name="OR2"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<lut_input_inverter exist="on" circuit_model_name="INV1X"/>
<lut_intermediate_buffer exist="on" circuit_model_name="buf1" location_map="-1-"/>
<lut_input_buffer exist="on" circuit_model_name="buf2"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="4" tri_state_map="--11" circuit_model_name="OR2"/>
<port type="output" prefix="lut2_out" size="4" lut_frac_level="2" lut_output_mask="0,1,2,3"/>
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="16"/>
<port type="sram" prefix="mode" size="2" mode_select="true" spice_model_name="sc_dff_compact" default_val="1"/>
</spice_model>
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<spice_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
<circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
<design_technology type="cmos"/>
<input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/>
<pass_gate_logic spice_model_name="TGATEX1"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<!-- <port type="input" prefix="pSet" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> -->
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</spice_model>
<spice_model type="iopad" name="iopad" prefix="iopad" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/io.v">
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/>
<pass_gate_logic spice_model_name="TGATEX1"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="inout" prefix="pad" size="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" spice_model_name="sc_dff_compact" default_val="1"/>
<!--port type="sram" prefix="enb" size="1" mode_select="true" spice_model_name="sc_dff_compact" default_val="0"/-->
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
<!--port type="sram" prefix="enb" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="0"/-->
<port type="input" prefix="outpad" size="1"/>
<!-- <port type="input" prefix="zin" size="1" is_global="true" default_val="0" /> -->
<port type="output" prefix="inpad" size="1"/>
</spice_model>
</circuit_model>
<!-- Hard logic definition for heterogenous blocks -->
<spice_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="true" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/adder.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/adder.v">
<circuit_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="true" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/adder.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" size="1"/>
<port type="input" prefix="cin" size="1"/>
<port type="output" prefix="sumout" size="1"/>
<port type="output" prefix="cout" size="1"/>
</spice_model>
<spice_model type="hard_logic" name="dpram" prefix="dpram" dump_explicit_port_map="true" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/spram.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/memory_wrapper.v">
</circuit_model>
<circuit_model type="hard_logic" name="dpram" prefix="dpram" dump_explicit_port_map="true" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/spram.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/memory_wrapper.v">
<design_technology type="cmos"/>
<input_buffer exist="on" spice_model_name="buf1"/>
<output_buffer exist="on" spice_model_name="buf1"/>
<input_buffer exist="on" circuit_model_name="buf1"/>
<output_buffer exist="on" circuit_model_name="buf1"/>
<port type="input" prefix="waddr" size="11"/>
<port type="input" prefix="raddr" size="11"/>
<port type="input" prefix="d_in" size="64"/>
@ -432,17 +432,17 @@
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="d_out" size="64"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
</spice_model>
<spice_model type="sram" name="sram6T" prefix="sram" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/sram.v">
</circuit_model>
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/>
<pass_gate_logic spice_model_name="TGATEX1"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
</spice_model>
</circuit_model>
</module_spice_models>
</module_circuit_models>
</spice_settings>
<device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
@ -469,9 +469,9 @@
-->
<area grid_logic_tile_area="0"/>
<sram area="6">
<verilog organization="scan-chain" spice_model_name="sc_dff_compact"/>
<!--verilog organization="memory-bank" spice_model_name="sram6T_blwl"/-->
<spice organization="standalone" spice_model_name="sram6T" />
<verilog organization="scan-chain" circuit_model_name="sc_dff_compact"/>
<!--verilog organization="memory-bank" circuit_model_name="sram6T_blwl"/-->
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
<chan_width_distr>
<io width="1.000000"/>
@ -482,7 +482,7 @@
</device>
<cblocks>
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" spice_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
</cblocks>
<switchlist>
@ -499,25 +499,25 @@
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="sb_mux_L16" R="0" Cin="0" Cout="" Tdel="1.3e-9" mux_trans_size="3" buf_size="63" spice_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
<switch type="mux" name="sb_mux_L16" R="0" Cin="0" Cout="" Tdel="1.3e-9" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
<switch type="mux" name="sb_mux_L4" R="0" Cin="0" Cout="" Tdel="0.72e-9" mux_trans_size="3" buf_size="63" spice_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
<switch type="mux" name="sb_mux_L4" R="0" Cin="0" Cout="" Tdel="0.72e-9" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
<switch type="mux" name="sb_mux_L2" R="115" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" spice_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
<switch type="mux" name="sb_mux_L2" R="115" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
</switch>
<switch type="mux" name="sb_mux_L1" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" spice_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
<switch type="mux" name="sb_mux_L1" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
</switch>
</switchlist>
<segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment freq="0.13" length="16" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
<segment freq="0.13" length="16" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L16"/>
<sb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</cb>
</segment>
<segment freq="0.87" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
<segment freq="0.87" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
@ -548,7 +548,7 @@
<!-- physical design description -->
<mode name="io_phy" disabled_in_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" spice_model_name="iopad" mode_bits="1">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad" mode_bits="1">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
@ -631,7 +631,7 @@
<input name="ren" num_pins="1"/>
<output name="d_out" num_pins="64"/>
<clock name="clk" num_pins="1"/>
<pb_type name="dpram" num_pb="1" blif_model=".subckt dpram" spice_model_name="dpram">
<pb_type name="dpram" num_pb="1" blif_model=".subckt dpram" circuit_model_name="dpram">
<input name="waddr" num_pins="11" port_class="address"/>
<input name="raddr" num_pins="11" port_class="address"/>
<input name="d_in" num_pins="64" port_class="data_in"/>
@ -729,7 +729,7 @@
<clock name="clk" num_pins="1"/>
<mode name="fle_phy" disabled_in_packing="true">
<!--pb_type name="fle_phy" num_pb="1" spice_model_name="fle_phy">
<!--pb_type name="fle_phy" num_pb="1" circuit_model_name="fle_phy">
<input name="in" num_pins="6"/>
<input name="cin" num_pins="1"/>
<output name="cout" num_pins="2"/>
@ -741,13 +741,13 @@
<input name="regchain" num_pins="1"/>
<output name="out" num_pins="2"/>
<output name="cout" num_pins="1"/>
<pb_type name="frac_lut6" blif_model=".frac_lut6" mode_bits="11" num_pb="1" spice_model_name="frac_lut6">
<pb_type name="frac_lut6" blif_model=".frac_lut6" mode_bits="11" num_pb="1" circuit_model_name="frac_lut6">
<input name="in" num_pins="6"/>
<output name="lut4_out" num_pins="4"/>
<output name="lut5_out" num_pins="2"/>
<output name="lut6_out" num_pins="1"/>
</pb_type>
<pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2" spice_model_name="adder">
<pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2" circuit_model_name="adder">
<input name="a" num_pins="1"/>
<input name="b" num_pins="1"/>
<input name="cin" num_pins="1"/>
@ -769,7 +769,7 @@
</mux>
</interconnect>
</pb_type>
<pb_type name="ff_phy" blif_model=".latch" num_pb="2" class="flipflop" spice_model_name="static_dff">
<pb_type name="ff_phy" blif_model=".latch" num_pb="2" class="flipflop" circuit_model_name="static_dff">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
@ -1064,31 +1064,31 @@
Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. -->
<complete name="crossbar0" input="clb.I2 clb.I3 fle[9:0].out" output="fle[9:0].in[0]" spice_model_name="mux_2level">
<complete name="crossbar0" input="clb.I2 clb.I3 fle[9:0].out" output="fle[9:0].in[0]" circuit_model_name="mux_2level">
<delay_constant max="90.2e-12" in_port="clb.I2 clb.I3" out_port="fle[9:0].in[0]" />
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[0]" />
</complete>
<complete name="crossbar1" input="clb.I1 clb.I2 fle[9:0].out" output="fle[9:0].in[1]" spice_model_name="mux_2level">
<complete name="crossbar1" input="clb.I1 clb.I2 fle[9:0].out" output="fle[9:0].in[1]" circuit_model_name="mux_2level">
<delay_constant max="90.2e-12" in_port="clb.I1 clb.I2" out_port="fle[9:0].in[1]" />
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[1]" />
</complete>
<complete name="crossbar2" input="clb.I0 clb.I1 fle[9:0].out" output="fle[9:0].in[2]" spice_model_name="mux_2level">
<complete name="crossbar2" input="clb.I0 clb.I1 fle[9:0].out" output="fle[9:0].in[2]" circuit_model_name="mux_2level">
<delay_constant max="90.2e-12" in_port="clb.I0 clb.I1" out_port="fle[9:0].in[2]" />
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[2]" />
</complete>
<complete name="crossbar3" input="clb.I1 clb.I3 fle[9:0].out" output="fle[9:0].in[3]" spice_model_name="mux_2level">
<complete name="crossbar3" input="clb.I1 clb.I3 fle[9:0].out" output="fle[9:0].in[3]" circuit_model_name="mux_2level">
<delay_constant max="90.2e-12" in_port="clb.I1 clb.I3" out_port="fle[9:0].in[3]" />
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[3]" />
</complete>
<complete name="crossbar4" input="clb.I0 clb.I2 fle[9:0].out" output="fle[9:0].in[4]" spice_model_name="mux_2level">
<complete name="crossbar4" input="clb.I0 clb.I2 fle[9:0].out" output="fle[9:0].in[4]" circuit_model_name="mux_2level">
<delay_constant max="90.2e-12" in_port="clb.I0 clb.I2" out_port="fle[9:0].in[4]" />
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[4]" />
</complete>
<complete name="crossbar5" input="clb.I0 clb.I3 fle[9:0].out" output="fle[9:0].in[5]" spice_model_name="mux_2level">
<complete name="crossbar5" input="clb.I0 clb.I3 fle[9:0].out" output="fle[9:0].in[5]" circuit_model_name="mux_2level">
</complete>
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
</complete>
<complete name="carry_in" input="clb.cin clb.cin_trick fle[9:0].out" output="fle[0:0].cin" spice_model_name="mux_2level">
<complete name="carry_in" input="clb.cin clb.cin_trick fle[9:0].out" output="fle[0:0].cin" circuit_model_name="mux_2level">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.cin clb.cin_trick" out_port="fle[0:0].cin"/>
<!--pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/-->

1
fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif
View File

@ -24,6 +24,7 @@
.subckt adder a=reg_a_2 b=reg_b_2 cin=cint02 cout=cint03 sumout=n03
.subckt adder a=reg_a_3 b=reg_b_3 cin=cint03 cout=cint04 sumout=n04
.subckt adder a=ref0 b=ref0 cin=cint04 cout=unconn sumout=n05
.subckt shift D=d0 clk=clk Q=reg0
.subckt shift D=reg0 clk=clk Q=reg1
.subckt shift D=reg1 clk=clk Q=reg2

34
fpga_flow/configs/tutorial/tuto.conf
View File

@ -1,27 +1,27 @@
# Standard Configuration Example
[dir_path]
script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/
benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC
yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys
odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe
cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit
abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc
abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1
m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net
mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2
vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr
rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial
ace_path = OPENFPGAPATHKEYWORD/ace2/ace
script_base = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/scripts/
benchmark_dir = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC
yosys_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/yosys/yosys
odin2_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/odin2.exe
cirkit_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/cirkit
abc_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/yosys/yosys-abc
abc_mccl_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/abc_with_bb_support/abc
abc_with_bb_support_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/abc_with_bb_support/abc
mpack1_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/mpack1
m2net_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/m2net
mpack2_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/mpack2
vpr_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/vpr
rpt_dir = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/results_tutorial
ace_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/ace2/ace
[flow_conf]
flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml
vpr_arch = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
m2net_conf = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
mpack2_arch = K6_pattern7_I24.arch
power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
power_tech_xml = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:

3
fpga_flow/tuto_fpga_flow.sh
View File

@ -27,8 +27,7 @@ perl rewrite_path_in_file.pl -i $config_file # Replace OPENFPGAPATHKEYWORD in th
perl rewrite_path_in_file.pl -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file
perl rewrite_path_in_file.pl -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file
echo "perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path"
perl rewrite_path_in_file.pl -i $ff_template_path -o $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file
perl rewrite_path_in_file.pl -i ${ff_template_path} -o ${ff_path} -k $dir_keyword $verilog_path # Set the define path in the ff.v file
# SRAM FPGA
# TT case

2
libs/CMakeLists.txt
View File

@ -2,6 +2,8 @@
#add_subdirectory(libarchfpga)
add_subdirectory(libvtrutil)
add_subdirectory(liblog)
add_subdirectory(external)
#add_subdirectory(external)
#add_subdirectory(libpugiutil)
#add_subdirectory(libeasygl)
#add_subdirectory(librtlnumber)

1
libs/external/CMakeLists.txt vendored Normal file
View File

@ -0,0 +1 @@
add_subdirectory(libini)

13
libs/external/libini/CMakeLists.txt vendored Normal file
View File

@ -0,0 +1,13 @@
cmake_minimum_required(VERSION 2.8.12)
project(libini)
file(GLOB_RECURSE LIB_HEADERS src/*.h)
files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
#Create the library
add_library(libini STATIC
${LIB_HEADERS})
target_include_directories(libini PUBLIC ${LIB_INCLUDE_DIRS})
set_target_properties(libini PROPERTIES PREFIX "" LINKER_LANGUAGE CXX)

755
libs/external/libini/src/ini.h vendored Executable file
View File

@ -0,0 +1,755 @@
/*
* The MIT License (MIT)
* Copyright (c) 2018 Danijel Durakovic
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is furnished to do
* so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
///////////////////////////////////////////////////////////////////////////////
//
// /mINI/ v0.9.7
// An INI file reader and writer for the modern age.
//
///////////////////////////////////////////////////////////////////////////////
//
// A tiny utility library for manipulating INI files with a straightforward
// API and a minimal footprint. It conforms to the (somewhat) standard INI
// format - sections and keys are case insensitive and all leading and
// trailing whitespace is ignored. Comments are lines that begin with a
// semicolon. Trailing comments are allowed on section lines.
//
// Files are read on demand, upon which data is kept in memory and the file
// is closed. This utility supports lazy writing, which only writes changes
// and updates to a file and preserves custom formatting and comments. A lazy
// write invoked by a write() call will read the output file, find what
// changes have been made and update the file accordingly. If you only need to
// generate files, use generate() instead. Section and key order is preserved
// on read, write and insert.
//
///////////////////////////////////////////////////////////////////////////////
//
// /* BASIC USAGE EXAMPLE: */
//
// /* read from file */
// mINI::INIFile file("myfile.ini");
// mINI::INIStructure ini;
// file.read(ini);
//
// /* read value; gets a reference to actual value in the structure.
// if key or section don't exist, a new empty value will be created */
// std::string& value = ini["section"]["key"];
//
// /* read value safely; gets a copy of value in the structure.
// does not alter the structure */
// std::string value = ini.get("section").get("key");
//
// /* set or update values */
// ini["section"]["key"] = "value";
//
// /* set multiple values */
// ini["section2"].set({
// {"key1", "value1"},
// {"key2", "value2"}
// });
//
// /* write updates back to file, preserving comments and formatting */
// file.write(ini);
//
// /* or generate a file (overwrites the original) */
// file.generate(ini);
//
///////////////////////////////////////////////////////////////////////////////
//
// Long live the INI file!!!
//
///////////////////////////////////////////////////////////////////////////////
#ifndef MINI_INI_H_
#define MINI_INI_H_
#include <string>
#include <sstream>
#include <algorithm>
#include <utility>
#include <unordered_map>
#include <vector>
#include <memory>
#include <fstream>
#include <sys/stat.h>
namespace mINI
{
namespace INIStringUtil
{
const std::string whitespaceDelimiters = " \t\n\r\f\v";
inline void trim(std::string &str)
{
str.erase(str.find_last_not_of(whitespaceDelimiters) + 1);
str.erase(0, str.find_first_not_of(whitespaceDelimiters));
}
#ifndef MINI_CASE_SENSITIVE
inline void toLower(std::string &str)
{
std::transform(str.begin(), str.end(), str.begin(), ::tolower);
}
#endif
inline void replace(std::string &str, std::string const &a, std::string const &b)
{
if (!a.empty())
{
std::size_t pos = 0;
while ((pos = str.find(a, pos)) != std::string::npos)
{
str.replace(pos, a.size(), b);
pos += b.size();
}
}
}
#ifdef _WIN32
const std::string endl = "\r\n";
#else
const std::string endl = "\n";
#endif
} // namespace INIStringUtil
template <typename T>
class INIMap
{
private:
using T_DataIndexMap = std::unordered_map<std::string, std::size_t>;
using T_DataItem = std::pair<std::string, T>;
using T_DataContainer = std::vector<T_DataItem>;
using T_MultiArgs = typename std::vector<std::pair<std::string, T>>;
T_DataIndexMap dataIndexMap;
T_DataContainer data;
inline std::size_t setEmpty(std::string &key)
{
std::size_t index = data.size();
dataIndexMap[key] = index;
data.emplace_back(key, T());
return index;
}
public:
using const_iterator = typename T_DataContainer::const_iterator;
INIMap() {}
INIMap(INIMap const &other)
{
std::size_t data_size = other.data.size();
for (std::size_t i = 0; i < data_size; ++i)
{
auto const &key = other.data[i].first;
auto const &obj = other.data[i].second;
data.emplace_back(key, obj);
}
dataIndexMap = T_DataIndexMap(other.dataIndexMap);
}
T &operator[](std::string key)
{
INIStringUtil::trim(key);
#ifndef MINI_CASE_SENSITIVE
INIStringUtil::toLower(key);
#endif
auto it = dataIndexMap.find(key);
bool hasIt = (it != dataIndexMap.end());
std::size_t index = (hasIt) ? it->second : setEmpty(key);
return data[index].second;
}
T get(std::string key) const
{
INIStringUtil::trim(key);
#ifndef MINI_CASE_SENSITIVE
INIStringUtil::toLower(key);
#endif
auto it = dataIndexMap.find(key);
if (it == dataIndexMap.end())
{
return T();
}
return T(data[it->second].second);
}
bool has(std::string key) const
{
INIStringUtil::trim(key);
#ifndef MINI_CASE_SENSITIVE
INIStringUtil::toLower(key);
#endif
return (dataIndexMap.count(key) == 1);
}
void set(std::string key, T obj)
{
INIStringUtil::trim(key);
#ifndef MINI_CASE_SENSITIVE
INIStringUtil::toLower(key);
#endif
auto it = dataIndexMap.find(key);
if (it != dataIndexMap.end())
{
data[it->second].second = obj;
}
else
{
dataIndexMap[key] = data.size();
data.emplace_back(key, obj);
}
}
void set(T_MultiArgs const &multiArgs)
{
for (auto const &it : multiArgs)
{
auto const &key = it.first;
auto const &obj = it.second;
set(key, obj);
}
}
bool remove(std::string key)
{
INIStringUtil::trim(key);
#ifndef MINI_CASE_SENSITIVE
INIStringUtil::toLower(key);
#endif
auto it = dataIndexMap.find(key);
if (it != dataIndexMap.end())
{
std::size_t index = it->second;
data.erase(data.begin() + index);
dataIndexMap.erase(it);
for (auto &it2 : dataIndexMap)
{
auto &vi = it2.second;
if (vi > index)
{
vi--;
}
}
return true;
}
return false;
}
void clear()
{
data.clear();
dataIndexMap.clear();
}
std::size_t size() const
{
return data.size();
}
const_iterator begin() const { return data.begin(); }
const_iterator end() const { return data.end(); }
};
using INIStructure = INIMap<INIMap<std::string>>;
namespace INIParser
{
using T_ParseValues = std::pair<std::string, std::string>;
enum class PDataType : char
{
PDATA_NONE,
PDATA_COMMENT,
PDATA_SECTION,
PDATA_KEYVALUE,
PDATA_UNKNOWN
};
inline PDataType parseLine(std::string line, T_ParseValues &parseData)
{
parseData.first.clear();
parseData.second.clear();
INIStringUtil::trim(line);
if (line.empty())
{
return PDataType::PDATA_NONE;
}
char firstCharacter = line[0];
if (firstCharacter == ';')
{
return PDataType::PDATA_COMMENT;
}
if (firstCharacter == '[')
{
auto commentAt = line.find_first_of(';');
if (commentAt != std::string::npos)
{
line = line.substr(0, commentAt);
}
auto closingBracketAt = line.find_last_of(']');
if (closingBracketAt != std::string::npos)
{
auto section = line.substr(1, closingBracketAt - 1);
INIStringUtil::trim(section);
parseData.first = section;
return PDataType::PDATA_SECTION;
}
}
auto lineNorm = line;
INIStringUtil::replace(lineNorm, "\\=", " ");
auto equalsAt = lineNorm.find_first_of('=');
if (equalsAt != std::string::npos)
{
auto key = line.substr(0, equalsAt);
INIStringUtil::trim(key);
INIStringUtil::replace(key, "\\=", "=");
auto value = line.substr(equalsAt + 1);
INIStringUtil::trim(value);
parseData.first = key;
parseData.second = value;
return PDataType::PDATA_KEYVALUE;
}
return PDataType::PDATA_UNKNOWN;
}
} // namespace INIParser
class INIReader
{
public:
using T_LineData = std::vector<std::string>;
using T_LineDataPtr = std::shared_ptr<T_LineData>;
private:
std::ifstream fileReadStream;
T_LineDataPtr lineData;
T_LineData readFile()
{
std::string fileContents;
fileReadStream.seekg(0, std::ios::end);
fileContents.resize(fileReadStream.tellg());
fileReadStream.seekg(0, std::ios::beg);
std::size_t fileSize = fileContents.size();
fileReadStream.read(&fileContents[0], fileSize);
fileReadStream.close();
T_LineData output;
if (fileSize == 0)
{
return output;
}
std::string buffer;
buffer.reserve(50);
for (std::size_t i = 0; i < fileSize; ++i)
{
char &c = fileContents[i];
if (c == '\n')
{
output.emplace_back(buffer);
buffer.clear();
continue;
}
if (c != '\0' && c != '\r')
{
buffer += c;
}
}
output.emplace_back(buffer);
return output;
}
public:
INIReader(std::string const &filename, bool keepLineData = false)
{
fileReadStream.open(filename, std::ios::in | std::ios::binary);
if (keepLineData)
{
lineData = std::make_shared<T_LineData>();
}
}
~INIReader() {}
bool operator>>(INIStructure &data)
{
if (!fileReadStream.is_open())
{
return false;
}
T_LineData fileLines = readFile();
std::string section;
bool inSection = false;
INIParser::T_ParseValues parseData;
for (auto const &line : fileLines)
{
auto parseResult = INIParser::parseLine(line, parseData);
if (parseResult == INIParser::PDataType::PDATA_SECTION)
{
inSection = true;
data[section = parseData.first];
}
else if (inSection && parseResult == INIParser::PDataType::PDATA_KEYVALUE)
{
auto const &key = parseData.first;
auto const &value = parseData.second;
data[section][key] = value;
}
if (lineData && parseResult != INIParser::PDataType::PDATA_UNKNOWN)
{
if (parseResult == INIParser::PDataType::PDATA_KEYVALUE && !inSection)
{
continue;
}
lineData->emplace_back(line);
}
}
return true;
}
T_LineDataPtr getLines()
{
return lineData;
}
};
class INIGenerator
{
private:
std::ofstream fileWriteStream;
public:
bool prettyPrint = false;
INIGenerator(std::string const &filename)
{
fileWriteStream.open(filename, std::ios::out | std::ios::binary);
}
~INIGenerator() {}
bool operator<<(INIStructure const &data)
{
if (!fileWriteStream.is_open())
{
return false;
}
if (!data.size())
{
return true;
}
auto it = data.begin();
for (;;)
{
auto const &section = it->first;
auto const &collection = it->second;
fileWriteStream
<< "["
<< section
<< "]";
if (collection.size())
{
fileWriteStream << INIStringUtil::endl;
auto it2 = collection.begin();
for (;;)
{
auto key = it2->first;
INIStringUtil::replace(key, "=", "\\=");
auto value = it2->second;
INIStringUtil::trim(value);
fileWriteStream
<< key
<< ((prettyPrint) ? " = " : "=")
<< value;
if (++it2 == collection.end())
{
break;
}
fileWriteStream << INIStringUtil::endl;
}
}
if (++it == data.end())
{
break;
}
fileWriteStream << INIStringUtil::endl;
if (prettyPrint)
{
fileWriteStream << INIStringUtil::endl;
}
}
return true;
}
};
class INIWriter
{
private:
using T_LineData = std::vector<std::string>;
using T_LineDataPtr = std::shared_ptr<T_LineData>;
std::string filename;
T_LineData getLazyOutput(T_LineDataPtr const &lineData, INIStructure &data, INIStructure &original)
{
T_LineData output;
INIParser::T_ParseValues parseData;
std::string sectionCurrent;
bool parsingSection = false;
bool continueToNextSection = false;
bool discardNextEmpty = false;
bool writeNewKeys = false;
std::size_t lastKeyLine = 0;
for (auto line = lineData->begin(); line != lineData->end(); ++line)
{
if (!writeNewKeys)
{
auto parseResult = INIParser::parseLine(*line, parseData);
if (parseResult == INIParser::PDataType::PDATA_SECTION)
{
if (parsingSection)
{
writeNewKeys = true;
parsingSection = false;
--line;
continue;
}
sectionCurrent = parseData.first;
if (data.has(sectionCurrent))
{
parsingSection = true;
continueToNextSection = false;
discardNextEmpty = false;
output.emplace_back(*line);
lastKeyLine = output.size();
}
else
{
continueToNextSection = true;
discardNextEmpty = true;
continue;
}
}
else if (parseResult == INIParser::PDataType::PDATA_KEYVALUE)
{
if (continueToNextSection)
{
continue;
}
if (data.has(sectionCurrent))
{
auto &collection = data[sectionCurrent];
auto const &key = parseData.first;
auto const &value = parseData.second;
if (collection.has(key))
{
auto outputValue = collection[key];
if (value == outputValue)
{
output.emplace_back(*line);
}
else
{
INIStringUtil::trim(outputValue);
auto lineNorm = *line;
INIStringUtil::replace(lineNorm, "\\=", " ");
auto equalsAt = lineNorm.find_first_of('=');
auto valueAt = lineNorm.find_first_not_of(
INIStringUtil::whitespaceDelimiters,
equalsAt + 1);
std::string outputLine = line->substr(0, valueAt);
if (prettyPrint && equalsAt + 1 == valueAt)
{
outputLine += " ";
}
outputLine += outputValue;
output.emplace_back(outputLine);
}
lastKeyLine = output.size();
}
}
}
else
{
if (discardNextEmpty && line->empty())
{
discardNextEmpty = false;
}
else if (parseResult != INIParser::PDataType::PDATA_UNKNOWN)
{
output.emplace_back(*line);
}
}
}
if (writeNewKeys || std::next(line) == lineData->end())
{
T_LineData linesToAdd;
if (data.has(sectionCurrent) && original.has(sectionCurrent))
{
auto const &collection = data[sectionCurrent];
auto const &collectionOriginal = original[sectionCurrent];
for (auto const &it : collection)
{
auto key = it.first;
if (collectionOriginal.has(key))
{
continue;
}
auto value = it.second;
INIStringUtil::replace(key, "=", "\\=");
INIStringUtil::trim(value);
linesToAdd.emplace_back(
key + ((prettyPrint) ? " = " : "=") + value);
}
}
if (!linesToAdd.empty())
{
output.insert(
output.begin() + lastKeyLine,
linesToAdd.begin(),
linesToAdd.end());
}
if (writeNewKeys)
{
writeNewKeys = false;
--line;
}
}
}
for (auto const &it : data)
{
auto const &section = it.first;
if (original.has(section))
{
continue;
}
if (prettyPrint && output.size() > 0 && !output.back().empty())
{
output.emplace_back();
}
output.emplace_back("[" + section + "]");
auto const &collection = it.second;
for (auto const &it2 : collection)
{
auto key = it2.first;
auto value = it2.second;
INIStringUtil::replace(key, "=", "\\=");
INIStringUtil::trim(value);
output.emplace_back(
key + ((prettyPrint) ? " = " : "=") + value);
}
}
return output;
}
public:
bool prettyPrint = false;
INIWriter(std::string const &file_name)
: filename(file_name)
{
}
~INIWriter() {}
bool operator<<(INIStructure &data)
{
struct stat buf;
bool fileExists = (stat(filename.c_str(), &buf) == 0);
if (!fileExists)
{
INIGenerator generator(filename);
generator.prettyPrint = prettyPrint;
return generator << data;
}
INIStructure originalData;
T_LineDataPtr lineData;
bool readSuccess = false;
{
INIReader reader(filename, true);
if ((readSuccess = reader >> originalData))
{
lineData = reader.getLines();
}
}
if (!readSuccess)
{
return false;
}
T_LineData output = getLazyOutput(lineData, data, originalData);
std::ofstream fileWriteStream(filename, std::ios::out | std::ios::binary);
if (fileWriteStream.is_open())
{
if (output.size())
{
auto line = output.begin();
for (;;)
{
fileWriteStream << *line;
if (++line == output.end())
{
break;
}
fileWriteStream << INIStringUtil::endl;
}
}
return true;
}
return false;
}
};
class INIFile
{
private:
std::string filename;
public:
INIFile(std::string const &file_name)
: filename(file_name)
{
}
~INIFile() {}
bool read(INIStructure &data) const
{
if (data.size())
{
data.clear();
}
if (filename.empty())
{
return false;
}
INIReader reader(filename);
return reader >> data;
}
bool generate(INIStructure const &data, bool pretty = false) const
{
if (filename.empty())
{
return false;
}
INIGenerator generator(filename);
generator.prettyPrint = pretty;
return generator << data;
}
bool write(INIStructure &data, bool pretty = false) const
{
if (filename.empty())
{
return false;
}
INIWriter writer(filename);
writer.prettyPrint = pretty;
return writer << data;
}
};
} // namespace mINI
#endif // MINI_INI_H_

5
libs/libvtrutil/src/vtr_geometry.h
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@ -49,6 +49,7 @@ template<class T>
class Point {
public: //Constructors
Point(T x_val, T y_val);
Point();
public: //Accessors
@ -59,6 +60,10 @@ class Point {
friend bool operator== <>(Point<T> lhs, Point<T> rhs);
friend bool operator!= <>(Point<T> lhs, Point<T> rhs);
friend bool operator< <>(Point<T> lhs, Point<T> rhs);
public: //Mutators
void set_x(T x_val);
void set_y(T y_val);
void swap();
private:
T x_;
T y_;

22
libs/libvtrutil/src/vtr_geometry.tpp
View File

@ -10,6 +10,12 @@ namespace vtr {
//pass
}
template<class T>
Point<T>::Point() {
//pass
}
template<class T>
T Point<T>::x() const {
return x_;
@ -36,6 +42,22 @@ namespace vtr {
return std::make_tuple(lhs.x(), lhs.y()) < std::make_tuple(rhs.x(), rhs.y());
}
template<class T>
void Point<T>::set_x(T x_val) {
x_ = x_val;
}
template<class T>
void Point<T>::set_y(T y_val) {
y_ = y_val;
}
template<class T>
void Point<T>::swap() {
std::swap(x_, y_);
}
/*
* Rect
*/

79
openfpga.sh Executable file
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@ -0,0 +1,79 @@
#!/bin/bash
#title : openfpga.sh
#description : This script provides shortcut commands <bash functions>
# for several simple operations in OpenFPGA project
#author : Ganesh Gore <ganesh.gore@utah.edu>
#==============================================================================
export OPENFPGA_PATH="$(pwd)"
export OPENFPGA_SCRIPT_PATH="$(pwd)/openfpga_flow/scripts"
export OPENFPGA_TASK_PATH="$(pwd)/openfpga_flow/tasks"
if [ -z $PYTHON_EXEC ]; then export PYTHON_EXEC="python3"; fi
# This function checks the path and
# raises warning if the command is not executing
# inside current OpendFPGA folder
check_execution_path (){
if [[ $1 != *"${OPENFPGA_PATH}"* ]]; then
echo -e "\e[33mCommand is not executed from configured OPNEFPGA directory\e[0m"
fi
}
run-task () {
$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@"
}
run-modelsim () {
$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_modelsim.py "$@"
}
run-flow () {
$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_flow.py "$@"
}
# lists all the configure task in task directory
list-tasks () {
check_execution_path "$(pwd)"
ls -tdalh ${OPENFPGA_TASK_PATH}/* | awk '{printf("%-4s | %s %-3s | ", $5, $6, $7) ;system("basename " $9)}'
}
# Switch directory to root of OpenFPGA
goto-root () {
cd $OPENFPGA_PATH
}
# Changes directory to task directory [goto_task <task_name> <run_num[default 0]>]
goto-task () {
if [ -z $1 ]; then
echo "requires task name goto_task <task_name> <run_num[default 0]>"
return
fi
goto_path=$OPENFPGA_TASK_PATH/$1
run_num=""
if [ ! -d $goto_path ]; then echo "Task directory not found"; return; fi
if [[ "$2" =~ '^[0-9]+$' ]] ; then
if ! [[ $2 == '0' ]] ; then run_num="$(printf run%03d $2)"; else run_num="latest"; fi
if [ ! -d "$goto_path/$run_num" ]; then run_num="latest"; fi
fi
if [ ! -d $goto_path/$run_num ]; then
echo "\e[33mTask run directory not found -" $goto_path/$run_num "\e[0m"
else
echo "Switching current dirctory to" $goto_path/$run_num
cd $goto_path/$run_num
fi
}
# Clears enviroment variables and fucntions
unset-openfpga (){
unset -v OPENFPGA_PATH
unset -f list-tasks run-task run-flow goto-task goto-root >/dev/null 2>&1
}
# Allow autocompletion of task
if [[ $(ps -p $$ -oargs=) == *"zsh"* ]]; then
autoload -U +X bashcompinit; bashcompinit;
fi
TaskList=$(ls -tdalh ${OPENFPGA_TASK_PATH}/* | awk '{system("basename " $9)}' | awk '{printf("%s ",$1)}')
complete -W "${TaskList}" goto-task
complete -W "${TaskList}" run-task
complete -W "${TaskList}" run-modelsim

1
openfpga_flow/.gitignore vendored Normal file
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@ -0,0 +1 @@
local_test_folder/

30
openfpga_flow/SpiceNetlists/adder.sp Normal file
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@ -0,0 +1,30 @@
* Sub Circuit
* 1-Bit Full-Adder circuit netlist
.subckt adder inA inB Cin Cout Sumout svdd sgnd size=1
X01 nd1 inA svdd svdd vpr_pmos W='size*beta*wp' L='pl'
X02 nd1 inB svdd svdd vpr_pmos W='size*beta*wp' L='pl'
X03 nd2 inB nd1 svdd vpr_pmos W='size*beta*wp' L='pl'
X04 nco inA nd2 svdd vpr_pmos W='size*beta*wp' L='pl'
X05 nco Cin nd1 svdd vpr_pmos W='size*beta*wp' L='pl'
X06 nco Cin nd3 sgnd vpr_nmos W='size*wn' L='nl'
X07 nd3 inA sgnd sgnd vpr_nmos W='size*wn' L='nl'
X08 nd3 inB sgnd sgnd vpr_nmos W='size*wn' L='nl'
X09 nco inA nd4 sgnd vpr_nmos W='size*wn' L='nl'
X10 nd4 inB sgnd sgnd vpr_nmos W='size*wn' L='nl'
Xo1 nco Cout svdd sgnd inv size='size'
X11 nd5 inA svdd svdd vpr_pmos W='size*beta*wp' L='pl'
X12 nd5 inB svdd svdd vpr_pmos W='size*beta*wp' L='pl'
X13 nd5 Cin svdd svdd vpr_pmos W='size*beta*wp' L='pl'
X14 nd6 inA nd5 svdd vpr_pmos W='size*beta*wp' L='pl'
X15 nd7 inB nd6 svdd vpr_pmos W='size*beta*wp' L='pl'
X16 ndS Cin nd7 svdd vpr_pmos W='size*beta*wp' L='pl'
X23 nds nco nd5 svdd vpr_pmos W='size*beta*wp' L='pl'
X24 nds nco nd8 sgnd vpr_nmos W='size*wn' L='nl'
X17 nd8 inA sgnd sgnd vpr_nmos W='size*wn' L='nl'
X18 nd8 inB sgnd sgnd vpr_nmos W='size*wn' L='nl'
X19 nd8 Cin sgnd sgnd vpr_nmos W='size*wn' L='nl'
X20 ndS Cin nd9 sgnd vpr_nmos W='size*wn' L='nl'
X21 nd9 inA n10 sgnd vpr_nmos W='size*wn' L='nl'
X22 n10 inB sgnd sgnd vpr_nmos W='size*wn' L='nl'
Xo2 nds Sumout svdd sgnd inv size='size'
.eom

25
openfpga_flow/SpiceNetlists/ff.sp Normal file
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@ -0,0 +1,25 @@
* Sub Circuits
*
* Static D Flip-flop
.subckt static_dff set rst clk D Q svdd sgnd size=1
* Input inverter
Xinv_clk clk clk_b svdd sgnd inv size=size
Xinv_set set set_b svdd sgnd inv size=size
Xinv_rst rst rst_b svdd sgnd inv size=size
Xinv_d D s1_n1 svdd sgnd inv size=size
Xcpt0 s1_n1 s1_n2 clk_b clk svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
Xset0 s1_n2 set_b svdd svdd vpr_pmos L=pl W='size*wp'
Xrst0 s1_n2 rst sgnd sgnd vpr_nmos L=nl W='size*wn'
Xinv1 s1_n2 s1_q svdd sgnd inv size=size
Xinv2 s1_q s1_n3 svdd sgnd inv size=size
Xcpt1 s1_n3 s1_n2 clk clk_b svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
* Stage 2
R3 s1_q s2_n1 0
Xcpt2 s2_n1 s2_n2 clk clk_b svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
Xrst1 s2_n2 rst_b svdd svdd vpr_pmos L=pl W='size*wp'
Xset1 s2_n2 set sgnd sgnd vpr_nmos L=nl W='size*wn'
Xinv4 s2_n2 Qb svdd sgnd inv size=size
Xinv5 Qb s2_n3 svdd sgnd inv size=size
Xcpt3 s2_n3 s2_n2 clk_b clk svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
Xinv_out Qb Q svdd sgnd inv size=size
.eom static_dff

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Testbench for D-type Flip-flop with set and reset
*********************************
* HSPICE Netlist *
* Author: Xifan TANG *
* Organization: EPFL,LSI *
*********************************
*
* Use Standard CMOS Technology
****** Include Technology Library ******
.lib '/home/xitang/tangxifan-eda-tools/branches/subvt_fpga/process/tsmc40nm/toplevel_crn45gs_2d5_v1d1_shrink0d9_embedded_usage.l' TOP_TT
****** Transistor Parameters ******
.param beta=2
.param nl=4e-08
.param wn=1.4e-07
.param pl=4e-08
.param wp=1.4e-07
****** Include subckt netlists: NMOS and PMOS *****
.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/spice_test/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/spice_test/subckt/inv_buf_trans_gate.sp'
.include '/home/xitang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.param clk_freq = 1e9
*Temperature
.temp 25
*Global nodes
.global vdd gnd
*Print node capacitance
.option captab
*Print waveforms
.option POST
* Parameters for measurements
.param clk2d=3e-09
.param clk_pwl=3e-09
.param clk_pwh=1.5e-08
.param slew=1e-11
.param thold=3e-09
.param vsp=0.9
* Parameters for Measuring Slew
.param slew_upper_threshold_pct_rise=0.9
.param slew_lower_threshold_pct_rise=0.1
.param slew_upper_threshold_pct_fall=0.1
.param slew_lower_threshold_pct_fall=0.9
* Parameters for Measuring Delay
.param input_threshold_pct_rise=0.5
.param input_threshold_pct_fall=0.5
.param output_threshold_pct_rise=0.5
.param output_threshold_pct_fall=0.5
Xdff[0] set rst clk d q vdd gnd static_dff
Vsupply vdd gnd 'vsp'
*Stimulates
vset set gnd 0
vrst rst gnd 0
vclk_in clk gnd pulse (0 vsp '0.5/clk_freq' '0.025/clk_freq' '0.025/clk_freq' '0.4875/clk_freq' '1/clk_freq')
* Measuring Clk2Q, Setup Time and Hold Time
vdata D gnd pulse (0 vsp '0.25/clk_freq' '0.025/clk_freq' '0.025/clk_freq' '2*0.4875/clk_freq' '2/clk_freq')
*Simulation
.tran 1e-15 '10/clk_freq'
.meas tran slew_q trig v(Q) val='slew_lower_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew'
+ targ v(Q) val='slew_upper_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew'
.meas tran clk2q trig v(CLK) val='input_threshold_pct_fall*vsp' rise=2
+ targ v(Q) val='output_threshold_pct_fall*vsp' fall=1 td='2*clk_pwl+clk_pwh+2*slew'
.end TSPC Flip-flop with set and reset

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* Sub Circuit
* OR2 gate
.subckt or2 in0 in1 out svdd sgnd size=1
Xp0 ntwk_n0 in0 svdd svdd vpr_pmos L=pl W='size*beta*wp'
Xp1 ntwk_n0 in1 ntwk_n1 svdd vpr_pmos L=pl W='size*beta*wp'
Xn0 ntwk_n1 in0 sgnd sgnd vpr_nmos L=nl W='wn*size'
Xn1 ntwk_n1 in1 sgnd sgnd vpr_nmos L=nl W='wn*size'
.eom
* AND2 gate
.subckt and2 in0 in1 out svdd sgnd size=1
Xp0 ntwk_n0 in0 svdd svdd vpr_pmos L=pl W='wp*size*beta'
Xp1 ntwk_n0 in1 svdd svdd vpr_pmos L=pl W='wp*size*beta'
Xn0 ntwk_n0 in0 ntwk_n1 sgnd vpr_nmos L=nl W='wn*size'
Xn1 ntwk_n1 in1 sgnd sgnd vpr_nmos L=nl W='wn*size'
.eom

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* Sub Circuit
* IO pads
* When direction = 0, pad <= dout
* When direction = 1, pad => din
.subckt iopad zin dout din pad direction direction_inv svdd sgnd
Xbuf0 pad din_inter svdd sgnd buf size=2
Xbuf1 dout pad_inter svdd sgnd buf size=2
*Xinv0 direction direction_inv svdd sgnd inv size=1
Xcpt0 din_inter din direction direction_inv svdd sgnd cpt
Xcpt1 pad_inter pad direction_inv direction svdd sgnd cpt
.eom iopad

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* Sub Circuit
* SRAM
* Input to force write the stored bit
.subckt sram6T in out outb svdd sgnd size=1
Xinv0 loop_out loop_outb svdd sgnd inv size=size
Xinv1 loop_outb loop_out svdd sgnd inv size=size
Xout_pt loop_out out svdd sgnd svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
Xoutb_pt loop_outb outb svdd sgnd svdd sgnd cpt
Rin in loop_out 0
.eom sram6T

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//------ Module: sram6T_blwl -----//
//------ Verilog file: sram.v -----//
//------ Author: Xifan TANG -----//
module adder(
input [0:0] a, // Input a
input [0:0] b, // Input b
input [0:0] cin, // Input cin
output [0:0] cout, // Output carry
output [0:0] sumout // Output sum
);
//wire[1:0] int_calc;
//assign int_calc = a + b + cin;
//assign cout = int_calc[1];
//assign sumout = int_calc[0];
assign sumout = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule

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//-----------------------------------------------------
// Design Name : dual_port_ram_32x512
// File Name : dpram.v
// Function : Dual port RAM 32x512
// Coder : Aurelien Alacchi
//-----------------------------------------------------
module dual_port_ram_32x512 (
input clk,
input wen,
input ren,
input[0:8] waddr,
input[0:8] raddr,
input[0:31] d_in,
output[0:31] d_out );
dual_port_sram_32x512 memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (d_in),
.rclk (clk),
.ren (ren),
.raddr (raddr),
.d_out (d_out) );
endmodule
module dual_port_sram_32x512 (
input wclk,
input wen,
input[0:8] waddr,
input[0:31] data_in,
input rclk,
input ren,
input[0:8] raddr,
output[0:31] d_out );
reg[0:31] ram[0:511];
reg[0:31] internal;
assign d_out = internal;
always @(posedge wclk) begin
if(wen) begin
ram[waddr] <= data_in;
end
end
always @(posedge rclk) begin
if(ren) begin
internal <= ram[raddr];
end
end
endmodule

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//-----------------------------------------------------
// Design Name : static_dff
// File Name : ff.v
// Function : D flip-flop with asyn reset and set
// Coder : Xifan TANG
//-----------------------------------------------------
//------ Include defines: preproc flags -----
// `include "./SRC/fpga_defines.v"
module static_dff (
/* Global ports go first */
input set, // set input
input reset, // Reset input
input clk, // Clock Input
/* Local ports follow */
input D, // Data Input
output Q // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge clk or posedge reset or posedge set)
if (reset) begin
q_reg <= 1'b0;
end else if (set) begin
q_reg <= 1'b1;
end else begin
q_reg <= D;
end
// Wire q_reg to Q
assign Q = q_reg;
endmodule //End Of Module static_dff
//-----------------------------------------------------
// Design Name : scan_chain_dff
// File Name : ff.v
// Function : D flip-flop with asyn reset and set
// Coder : Xifan TANG
//-----------------------------------------------------
module sc_dff (
/* Global ports go first */
input set, // set input
input reset, // Reset input
input clk, // Clock Input
/* Local ports follow */
input D, // Data Input
output Q, // Q output
output Qb // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge clk or posedge reset or posedge set)
if (reset) begin
q_reg <= 1'b0;
end else if (set) begin
q_reg <= 1'b1;
end else begin
q_reg <= D;
end
// Wire q_reg to Q
assign Q = q_reg;
assign Qb = ~Q;
endmodule //End Of Module static_dff
//-----------------------------------------------------
// Design Name : scan_chain_dff compact
// File Name : ff.v
// Function : Scan-chain D flip-flop without reset and set //Modified to fit Edouards architecture
// Coder : Xifan TANG
//-----------------------------------------------------
module sc_dff_compact (
/* Global ports go first */
input reset, // Reset input
//input set, // set input
input clk, // Clock Input
/* Local ports follow */
input D, // Data Input
output Q, // Q output
output Qb // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge clk or posedge reset /*or posedge set*/)
if (reset) begin
q_reg <= 1'b0;
//end else if (set) begin
// q_reg <= 1'b1;
end else begin
q_reg <= D;
end
/*
// Wire q_reg to Q
assign Q = q_reg;
assign Qb = ~Q;
*/
`ifndef ENABLE_FORMAL_VERIFICATION
// Wire q_reg to Q
assign Q = q_reg;
assign Qb = ~q_reg;
`else
assign Q = 1'bZ;
assign Qb = !Q;
`endif
endmodule //End Of Module static_dff

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//-----------------------------------------------------
// Design Name : testbench for static_dff
// File Name : ff_tb.v
// Function : D flip-flop with asyn reset and set
// Coder : Xifan TANG
//-----------------------------------------------------
//----- Time scale: simulation time step and accuracy -----
`timescale 1ns / 1ps
module static_dff_tb;
// voltage sources
wire set;
reg reset;
reg clk;
reg D;
wire Q;
// Parameters
parameter clk_period = 2; // [ns] a full clock period
parameter half_clk_period = clk_period / 2; // [ns] a half clock period
parameter d_period = 2 * clk_period; // [ns] two clock period
parameter reset_period = 8 * clk_period; // [ns] a full clock period
// Unit Under Test
static_dff U0 (set, reset, clk, D, Q);
// Voltage stimuli
// Reset : enable in the first clock cycle and then disabled
initial
begin
reset = 1'b1;
#clk_period reset = ~reset;
end
always
begin
#reset_period reset = ~reset;
end
// set : alway disabled
assign set = 1'b0;
// clk: clock generator
initial
begin
clk = 1'b0;
end
always
begin
#half_clk_period clk = ~clk;
end
// D: input, flip every two clock cycles
initial
begin
D = 1'b0;
end
always
begin
#d_period D = ~D;
end
// Q is an output
//
endmodule

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//------ Module: iopad -----//
//------ Verilog file: io.v -----//
//------ Author: Xifan TANG -----//
module iopad(
//input zin, // Set output to be Z
input outpad, // Data output
output inpad, // Data input
inout pad, // bi-directional pad
input en // enable signal to control direction of iopad
//input direction_inv // enable signal to control direction of iopad
);
//----- when direction enabled, the signal is propagated from pad to din
assign inpad = en ? pad : 1'bz;
//----- when direction is disabled, the signal is propagated from dout to pad
assign pad = en ? 1'bz : outpad;
endmodule

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//-----------------------------------------------------
// Design Name : testbench for logic blocks
// File Name : lb_tb.v
// Function : Configurable logic block
// Coder : Xifan TANG
//-----------------------------------------------------
//----- Time scale: simulation time step and accuracy -----
`timescale 1ns / 1ps
module lb_tb;
// Parameters
parameter SIZE_IN = 40; //---- MUX input size
parameter SIZE_OUT = 10; //---- MUX input size
parameter SIZE_RESERV_BLWL = 49 + 1; //---- MUX input size
parameter SIZE_BLWL = 1019 - 310 + 1; //---- MUX input size
parameter prog_clk_period = 1; // [ns] half clock period
parameter op_clk_period = 1; // [ns] half clock period
parameter config_period = 2 * prog_clk_period; // [ns] One full clock period
parameter operating_period = SIZE_IN * 2 * op_clk_period; // [ns] One full clock period
// Ports
wire [0:SIZE_IN-1] lb_in;
wire [0:SIZE_IN-1] lb_out;
wire lb_clk;
wire [0:SIZE_RESERV_BLWL-1] reserv_bl;
wire [0:SIZE_RESERV_BLWL-1] reserv_wl;
wire [0:SIZE_BLWL-1] bl;
wire [0:SIZE_BLWL-1] wl;
wire prog_EN;
wire prog_ENb;
wire zin;
wire nequalize;
wire read;
wire clk;
wire Reset;
wire Set;
// Clocks
wire prog_clock;
wire op_clock;
// Registered port
reg [0:SIZE_IN-1] lb_in_reg;
reg [0:SIZE_RESERV_BLWL-1] reserv_bl_reg;
reg [0:SIZE_RESERV_BLWL-1] reserv_wl_reg;
reg [0:SIZE_BLWL-1] bl_reg;
reg [0:SIZE_BLWL-1] wl_reg;
reg prog_clock_reg;
reg op_clock_reg;
// Config done signal;
reg config_done;
// Temp register for rotating shift
reg temp;
// Unit under test
grid_1__1_ U0 (
zin,
nequalize,
read,
clk,
Reset,
Set,
prog_ENb,
prog_EN,
// Top inputs
lb_in[0], lb_in[4], lb_in[8], lb_in[12], lb_in[16],
lb_in[20], lb_in[24], lb_in[28], lb_in[32], lb_in[36],
// Top outputs
lb_out[0], lb_out[4], lb_out[8],
// Right inputs
lb_in[1], lb_in[5], lb_in[9], lb_in[13], lb_in[17],
lb_in[21], lb_in[25], lb_in[29], lb_in[33], lb_in[37],
// Right outputs
lb_out[1], lb_out[5], lb_out[9],
// Bottom inputs
lb_in[2], lb_in[6], lb_in[10], lb_in[14], lb_in[18],
lb_in[22], lb_in[26], lb_in[30], lb_in[34], lb_in[38],
// Bottom outputs
lb_out[2], lb_out[6],
// Bottom inputs
lb_clk,
// left inputs
lb_in[3], lb_in[7], lb_in[11], lb_in[15], lb_in[19],
lb_in[23], lb_in[27], lb_in[31], lb_in[35], lb_in[39],
// left outputs
lb_out[3], lb_out[7],
reserv_bl, reserv_wl,
bl, wl
);
// Task: assign BL and WL values
task prog_lb_blwl;
begin
@(posedge prog_clock);
// Rotate left shift
temp = reserv_bl_reg[SIZE_RESERV_BLWL-1];
//bl_reg = bl_reg >> 1;
reserv_bl_reg[1:SIZE_RESERV_BLWL-1] = reserv_bl_reg[0:SIZE_RESERV_BLWL-2];
reserv_bl_reg[0] = temp;
end
endtask
// Task: assign inputs
task op_lb_in;
begin
@(posedge op_clock);
temp = lb_in_reg[SIZE_IN-1];
lb_in_reg[1:SIZE_IN-1] = lb_in_reg[0:SIZE_IN-2];
lb_in_reg[0] = temp;
end
endtask
// Configuration done signal
initial
begin
config_done = 1'b0;
end
// Enabled during config_period, Disabled during op_period
always
begin
#config_period config_done = ~config_done;
#operating_period config_done = ~config_done;
end
// Programming clocks
initial
begin
prog_clock_reg = 1'b0;
end
always
begin
#prog_clk_period prog_clock_reg = ~prog_clock_reg;
end
// Operating clocks
initial
begin
op_clock_reg = 1'b0;
end
always
begin
#op_clk_period op_clock_reg = ~op_clock_reg;
end
// Programming and Operating clocks
assign prog_clock = prog_clock_reg & (~config_done);
assign op_clock = op_clock_reg & config_done;
// Programming Enable signals
assign prog_EN = prog_clock & (~config_done);
assign prog_ENb = ~prog_EN;
// Programming phase: BL/WL
initial
begin
// Initialize BL/WL registers
reserv_bl_reg = {SIZE_RESERV_BLWL {1'b0}};
reserv_bl_reg[0] = 1'b1;
reserv_wl_reg = {SIZE_RESERV_BLWL {1'b0}};
// Reserved BL/WL
bl_reg = {SIZE_BLWL {1'b0}};
wl_reg = {SIZE_BLWL {1'b1}};
//wl_reg[SIZE_BLWL-1] = 1'b1;
end
always wait (~config_done) // Only invoked when config_done is 0
begin
// Propagate input 1 to the output
// BL[0] = 1, WL[4] = 1
prog_lb_blwl;
end
// Operating Phase
initial
begin
lb_in_reg = {SIZE_IN {1'b0}};
lb_in_reg[0] = 1'b1; // Last bit is 1 initially
end
always wait (config_done) // Only invoked when config_done is 1
begin
/* Update inputs */
op_lb_in;
end
// Wire ports
assign lb_in = lb_in_reg;
assign reserv_bl = reserv_bl_reg;
assign reserv_wl = reserv_wl_reg;
assign bl = bl_reg;
assign wl = wl_reg;
// Constant ports
assign zin = 1'b0;
assign nequalize = 1'b1;
assign read = 1'b0;
assign clk = op_clock;
assign Reset = ~config_done;
assign Set = 1'b0;
endmodule

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//-----------------------------------------------------
// Design Name : lut6
// File Name : lut6.v
// Function : 6-input Look Up Table
// Coder : Xifan TANG
//-----------------------------------------------------
module lut6 (
input [5:0] in,
output out,
input [63:0] sram,
input [63:0] sram_inv);
assign out = sram[in];
endmodule

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//-----------------------------------------------------
// Design Name : MUX2
// File Name : mux2.v
// Function : Standard cell (static gate) implementation
// of 2-input multiplexers
// Coder : Xifan Tang
//-----------------------------------------------------
module MUX2(
input A, // Data input 0
input B, // Data input 1
input S0, // Select port
output Y // Data output
);
assign Y = S0 ? B : A;
// Note:
// MUX2 appears will appear in LUTs, routing multiplexers,
// being a component in combinational loops
// To help convergence in simulation
// i.e., to avoid the X (undetermined) signals,
// the following timing constraints and signal initialization
// has to be added!
`ifdef ENABLE_TIMING
// ------ BEGIN Pin-to-pin Timing constraints -----
specify
(A => Y) = (0.001, 0.001);
(B => Y) = (0.001, 0.001);
(S0 => Y) = (0.001, 0.001);
endspecify
// ------ END Pin-to-pin Timing constraints -----
`endif
`ifdef ENABLE_SIGNAL_INITIALIZATION
// ------ BEGIN driver initialization -----
initial begin
`ifdef ENABLE_FORMAL_VERIFICATION
$deposit(A, 1'b0);
$deposit(B, 1'b0);
$deposit(S0, 1'b0);
`else
$deposit(A, $random);
$deposit(B, $random);
$deposit(S0, $random);
`endif
end
// ------ END driver initialization -----
`endif
endmodule

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//-----------------------------------------------------
// Design Name : testbench for 2-level SRAM MUX
// File Name : mux_tb.v
// Function : SRAM-based 2-level MUXes
// Coder : Xifan TANG
//-----------------------------------------------------
//----- Time scale: simulation time step and accuracy -----
`timescale 1ns / 1ps
module cmos_mux2level_tb;
// Parameters
parameter SIZE_OF_MUX = 50; //---- MUX input size
parameter SIZE_OF_SRAM = 16; //---- MUX input size
parameter op_clk_period = 1; // [ns] half clock period
parameter operating_period = SIZE_OF_MUX * 2 * op_clk_period; // [ns] One full clock period
// voltage sources
wire [0:SIZE_OF_MUX-1] in;
wire out;
wire [0:SIZE_OF_SRAM-1] sram;
wire [0:SIZE_OF_SRAM-1] sram_inv;
// clocks
wire op_clock;
// registered ports
reg op_clock_reg;
reg [0:SIZE_OF_MUX-1] in_reg;
reg [0:SIZE_OF_SRAM-1] sram_reg;
reg [0:SIZE_OF_SRAM-1] sram_inv_reg;
// Config done signal;
reg config_done;
// Temp register for rotating shift
reg temp;
// Unit Under Test
mux_2level_size50 U0 (in, out, sram, sram_inv);
// Task: assign inputs
task op_mux_input;
begin
@(posedge op_clock);
temp = in_reg[SIZE_OF_MUX-1];
in_reg[1:SIZE_OF_MUX-1] = in_reg[0:SIZE_OF_MUX-2];
in_reg[0] = temp;
end
endtask
// Configuration done signal
initial
begin
config_done = 1'b1;
end
// Operating clocks
initial
begin
op_clock_reg = 1'b0;
end
always
begin
#op_clk_period op_clock_reg = ~op_clock_reg;
end
// Programming and Operating clocks
assign op_clock = op_clock_reg & config_done;
// Operating Phase
initial
begin
in_reg = {SIZE_OF_MUX {1'b0}};
in_reg[0] = 1'b1; // Last bit is 1 initially
end
always wait (config_done) // Only invoked when config_done is 1
begin
/* Update inputs */
op_mux_input;
end
// Wire ports
assign in = in_reg;
assign sram[0:7] = 8'b00010000;
assign sram[8:15] = 8'b00010000;
assign sram_inv = ~sram;
endmodule

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//------ Module: sram6T_blwl -----//
//------ Verilog file: sram.v -----//
//------ Author: Xifan TANG -----//
module sram6T_blwl(
//input read,
//input nequalize,
input din, // Data input
output dout, // Data output
output doutb, // Data output
input bl, // Bit line control signal
input wl, // Word line control signal
input blb // Inverted Bit line control signal
);
//----- local variable need to be registered
reg a;
//----- when wl is enabled, we can read in data from bl
always @(bl, wl)
begin
//----- Cases to program internal memory bit
//----- case 1: bl = 1, wl = 1, a -> 0
if ((1'b1 == bl)&&(1'b1 == wl)) begin
a <= 1'b1;
end
//----- case 2: bl = 0, wl = 1, a -> 0
if ((1'b0 == bl)&&(1'b1 == wl)) begin
a <= 1'b0;
end
end
// dout is short-wired to din
assign dout = a;
//---- doutb is always opposite to dout
assign doutb = ~dout;
`ifdef ENABLE_SIGNAL_INITIALIZATION
initial begin
$deposit(a, $random);
end
`endif
endmodule
module sram6T_rram(
input read,
input nequalize,
input din, // Data input
output dout, // Data output
output doutb, // Data output
// !!! Port bit position should start from LSB to MSB
// Follow this convention for BL/WLs in each module!
input [0:2] bl, // Bit line control signal
input [0:2] wl// Word line control signal
);
//----- local variable need to be registered
//----- Modeling two RRAMs
reg r0, r1;
always @(bl[0], wl[2])
begin
//----- Cases to program r0
//----- case 1: bl[0] = 1, wl[2] = 1, r0 -> 0
if ((1'b1 == bl[0])&&(1'b1 == wl[2])) begin
r0 <= 0;
end
end
always @(bl[2], wl[0])
begin
//----- case 2: bl[2] = 1, wl[0] = 1, r0 -> 1
if ((1'b1 == bl[2])&&(1'b1 == wl[0])) begin
r0 <= 1;
end
end
always @(bl[1], wl[2])
begin
//----- Cases to program r1
//----- case 1: bl[1] = 1, wl[2] = 1, r0 -> 0
if ((1'b1 == bl[1])&&(1'b1 == wl[2])) begin
r1 <= 0;
end
end
always @( bl[2], wl[1])
begin
//----- case 2: bl[2] = 1, wl[1] = 1, r0 -> 1
if ((1'b1 == bl[2])&&(1'b1 == wl[1])) begin
r1 <= 1;
end
end
// dout is r0 AND r1
assign dout = r0 | (~r1);
//---- doutb is always opposite to dout
assign doutb = ~dout;
endmodule

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//-----------------------------------------------------
// Design Name : testbench for static_dff
// File Name : ff_tb.v
// Function : D flip-flop with asyn reset and set
// Coder : Xifan TANG
//-----------------------------------------------------
//----- Time scale: simulation time step and accuracy -----
`timescale 1ns / 1ps
module sram6T_rram_tb;
// voltage sources
wire read;
wire nequalize;
wire din;
wire dout;
wire doutb;
reg [0:2] bl;
reg [0:2] wl;
reg prog_clock;
// Parameters
parameter prog_clk_period = 2; // [ns] a full clock period
// Unit Under Test
sram6T_rram U0 (read, nequalize, din, dout, doutb, bl, wl);
// Voltage stimuli
// read : alway disabled
assign read = 1'b0;
// nequalize: always disabled
assign nequalize = 1'b1;
// din: always disabled
assign din = 1'b0;
// Programming clock
initial
begin
prog_clock = 1'b0;
end
always
begin
#prog_clk_period prog_clock = ~prog_clock;
end
// Task: assign BL and WL values
task prog_blwl;
input [0:2] bl_val;
input [0:2] wl_val;
begin
@(posedge prog_clock);
bl = bl_val;
wl = wl_val;
end
endtask
// Test two cases:
// 1. Program dout to 0
// bl[0] = 1, wl[2] = 1
// bl[2] = 1, wl[0] = 1
// 2. Program dout to 1
// bl[1] = 1, wl[2] = 1
// bl[2] = 1, wl[1] = 1
initial
begin
bl = 3'b000;
wl = 3'b000;
// 1. Program dout to 0
// bl[0] = 1, wl[2] = 1
prog_blwl(3'b100, 3'b001);
// bl[2] = 1, wl[0] = 1
prog_blwl(3'b001, 3'b100);
// 2. Program dout to 1
// bl[1] = 1, wl[2] = 1
prog_blwl(3'b010, 3'b001);
// bl[2] = 1, wl[1] = 1
prog_blwl(3'b100, 3'b010);
// 3. Program dout to 0
// bl[0] = 1, wl[2] = 1
prog_blwl(3'b100, 3'b001);
// bl[2] = 1, wl[0] = 1
prog_blwl(3'b001, 3'b100);
end
// Outputs are wired to dout and doutb
endmodule

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<!--
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
- 40 nm technology
- General purpose logic block:
K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared)
with optionally registered outputs
Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
Carry chain links to vertically adjacent logic blocks
- Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.
Height = 6, found on every (8n+2)th column
- Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.
Height = 4, found on every (8n+6)th column
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
Details on Modelling:
The electrical design of the architecture described here is NOT from an
optimized, SPICED architecture. Instead, we attempt to create a reasonable
architecture file by using an existing commercial FPGA to approximate the area,
delay, and power of the underlying components. This is combined with a reasonable 40 nm
model of wiring and circuit design for low-level routing components, where available.
The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also
has wiring electrical parameters that allow the wire lengths and switch patterns to be
modified and you will still get reasonable delay results for the new architecture.
The following describes, in detail, how we obtained the various electrical values for this
architecture.
Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar
architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture.
(n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)
This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to
match the overall target (a 40 nm FPGA).
We obtain delay numbers by measuring delays of routing, soft logic blocks,
memories, and multipliers from test circuits on a Stratix IV GX device
(EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4
wires. Rmetal and Cmetal values for the routing wires were obtained from work done by Charles
Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and
take the R and C data from the ITRS roadmap.
For the general purpose logic block, we assume that the area and delays of the Stratix IV
crossbar is close enough to the crossbar modelled here. We use 40 inputs and 20 feedback lines in
the cluster and a full crossbar, leading to 53:1 multiplexers in front of each BLE input.
Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to
36:1 multiplexers. We require 60 such multiplexers, while Stratix IV requires 88 for its more
complex fracturable BLEs + the extra control signals. We justify this rough approximation as follows:
The Stratix IV crossbar has more inputs (72 vs. 60) and
outputs (88 vs. 60) than our full crossbar which should increase its area and delay, but the
Stratix IV crossbar is also 50% sparse (each mux is 36:1 instead of 53:1) which should reduce its
area and delay. The total number of crossbar switch points is roughly similar between the two
architectures (3160 for SIV and 3600 for the academic architecture below), so we use the area
& delay of the Stratix IV crossbar as a rough approximation of our crossbar.
For LUTs, we include LUT
delays measured from Stratix IV which is dependant on the input used (ie. some
LUT inputs are faster than others). The CAD tools at the time of VTR 7 does
not consider differences in LUT input delays.
Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.
Delay obtained by compiling a 256 bit adder (registered inputs and outputs,
all pins except clock virtual) then measuring the delays in chip-planner,
sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns,
inter-block carry delay = 0.327 ns. Given this data, I will approximate
sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and
inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has
overhead that we don't have, I'll approximate the delay of a simpler chain at
one half what they have. This is very rough, anything from 0.01ns to 0.327ns
can be justified).
Logic block area numbers obtained by scaling overall tile area of a 65nm
Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out
routing area at a channel width of 300. We use a channel width of 300 because it can route
all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
choosing a width that provides high routability. The architecture can be routed at different channel
widths, but we estimate the tile size and hence the physical length of routing wires assuming
a channel width of 300.
Sanity checks employed:
1. We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches
common electrical design.
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
-->
<architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports.
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch)
that describe them.
-->
<models>
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout auto="1.0" tileable_routing="off"/>
<spice_settings>
<parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>
<monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off">
<cmos abs_variation="0.1" num_sigma="3"/>
<rram abs_variation="0.1" num_sigma="3"/>
</monte_carlo>
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measure>
<stimulate>
<!--clock op_freq="200e6" sim_slack="0.2" prog_freq="2.5e6"-->
<clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6"> <!--frequency modified to speedup the fpga programing-->
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
</clock>
<input>
<rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/>
</input>
</stimulate>
</parameters>
<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="${OPENFPGA_PATH}/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
</transistors>
<module_circuit_models>
<circuit_model type="inv_buf" name="INV1X" prefix="INV1X" is_default="1">
<design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="INV4X" prefix="INV4X" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="INV2X" prefix="INV2X" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf2" prefix="buf2" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="2"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf1" prefix="buf1" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="pass_gate" name="TGATEX1" prefix="TGATEX1" is_default="1">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="1">
<design_technology type="cmos" topology="OR"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="a b" out_port="out">
10e-12 10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="false">
<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="1"/>
<port type="sram" prefix="sram" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="false">
<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV4X"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="1"/>
<port type="sram" prefix="sram" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="1" dump_structural_verilog="false">
<design_technology type="cmos" structure="one-level" add_const_input="true" const_input_val="1"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV4X"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="1"/>
<port type="sram" prefix="sram" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="unfrac_lut4" prefix="unfrac_lut4" dump_structural_verilog="false">
<design_technology type="cmos" fracturable_lut="false"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<lut_input_inverter exist="on" circuit_model_name="INV1X"/>
<lut_intermediate_buffer exist="on" circuit_model_name="buf1" location_map="-1-"/>
<lut_input_buffer exist="on" circuit_model_name="buf2"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="4"/>
<port type="output" prefix="out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="16"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
<!-- <port type="input" prefix="pSet" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> -->
<port type="input" prefix="D" lib_name="D" size="1"/>
<port type="output" prefix="Q" lib_name="Q" size="1"/>
<port type="output" prefix="Qb" lib_name="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="inout" prefix="pad" size="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
<!--port type="sram" prefix="enb" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="0"/-->
<port type="input" prefix="outpad" size="1"/>
<!-- <port type="input" prefix="zin" size="1" is_global="true" default_val="0" /> -->
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
<!-- Hard logic definition for heterogenous blocks -->
<circuit_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="false" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" size="1"/>
<port type="input" prefix="cin" size="1"/>
<port type="output" prefix="sumout" size="1"/>
<port type="output" prefix="cout" size="1"/>
</circuit_model>
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>
<pass_gate_logic circuit_model_name="TGATEX1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
</circuit_model>
</module_circuit_models>
</spice_settings>
<device>
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
lined up with Stratix IV.
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
by 2.5x when looking up in Jeff's tables.
The delay values are lined up with Stratix IV, which has an architecture similar to this
proposed FPGA, and which is also 40 nm
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
4x minimum drive strength buffer. -->
<sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="9"/>
<timing C_ipin_cblock="596e-18" T_ipin_cblock="77.93e-12"/>
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-->
<area grid_logic_tile_area="0"/>
<sram area="6">
<verilog organization="scan-chain" circuit_model_name="sc_dff_compact"/>
<!--verilog organization="memory-bank" circuit_model_name="sram6T_blwl"/-->
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
</device>
<cblocks>
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
</cblocks>
<switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="sb_mux_L16" R="0" Cin="0" Cout="" Tdel="1.3e-9" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
<switch type="mux" name="sb_mux_L4" R="0" Cin="0" Cout="" Tdel="0.72e-9" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
<switch type="mux" name="sb_mux_L2" R="115" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
</switch>
<switch type="mux" name="sb_mux_L1" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
</switch>
</switchlist>
<segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment freq="0.13" length="16" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L16"/>
<sb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</cb>
</segment>
<segment freq="0.87" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
</segmentlist>
<!--switch_segment_patterns>
<pattern type="unbuf_sb" seg_length="1" seg_type="unidir" pattern_length="2">
<unbuf_mux name="1"/>
<sb type ="pattern">0 1</sb>
</pattern>
</switch_segment_patterns-->
<complexblocklist>
<!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io" capacity="2" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- physical design description -->
<mode name="io_phy" disabled_in_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad" mode_bits="1">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- IOs can operate as either inputs or outputs.§
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1" physical_pb_type_name="iopad" mode_bits="1">
<output name="inpad" num_pins="1" physical_mode_pin="inpad"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1" physical_pb_type_name="iopad" mode_bits="0">
<input name="outpad" num_pins="1" physical_mode_pin="outpad"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.30" default_out_type="frac" default_out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
<!-- Place I/Os on the sides of the FPGA -->
<gridlocations>
<loc type="perimeter" priority="10"/>
</gridlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic
block. Note that the crossbar / local interconnect is considered part of the logic block
area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range.
-->
<pb_type name="clb" area="11388">
<input name="I" num_pins="12" equivalent="true"/>
<output name="O" num_pins="4" equivalent="false"/>
<clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered
-->
<pb_type name="fle" num_pb="4">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<pb_type name="logic" num_pb="1">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<pb_type name="lut4" blif_model=".names" num_pb="1" circuit_model_name="unfrac_lut4" class="lut">
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
202e-12
202e-12
202e-12
202e-12
</delay_matrix>
</pb_type>
<interconnect>
<direct name="direct_lut_in" input="logic.in[3:0]" output="lut4.in[3:0]"/>
<direct name="direct_lut_out" input="lut4.out" output="logic.out"/>
</interconnect>
</pb_type>
<pb_type name="ff_phy" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
</pb_type>
<interconnect>
<complete name="direct_clk" input="fle.clk" output="ff_phy.clk"/>
<direct name="direct_in" input="fle.in[3:0]" output="logic.in[3:0]"/>
<direct name="direct_frac_out1" input="logic.out" output="ff_phy.D"/>
<mux name="mux_out" input="ff_phy.Q logic.out" output="fle.out">
</mux>
</interconnect>
</pb_type>
<interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
delay within the crossbar is 95 ps.
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in" circuit_model_name="mux_2level">
<delay_constant max="90.2e-12" in_port="clb.I" out_port="fle[3:0].in" />
<delay_constant max="70.2e-12" in_port="fle[3:0].out" out_port="fle[3:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
</complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification).
-->
<direct name="clbouts1" input="fle[3:0].out" output="clb.O[3:0]"/>
</interconnect>
<fc default_in_type="frac" default_in_val="0.1" default_out_type="frac" default_out_val="0.10">
</fc>
<pinlocations pattern="custom">
<loc side="top">clb.clk </loc>
<loc side="right">clb.I[5:0] clb.O[1:0]</loc>
<loc side="bottom">clb.I[11:6] clb.O[3:2]</loc>
<loc side="left"></loc>
</pinlocations>
<gridlocations>
<loc type="fill" priority="1"/>
</gridlocations>
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
</complexblocklist>
<power>
<local_interconnect C_wire="2.5e-10"/>
<mux_transistor_size mux_transistor_size="3"/>
<FF_size FF_size="4"/>
<LUT_transistor_size LUT_transistor_size="4"/>
</power>
<clocks>
<clock buffer_size="auto" C_wire="2.5e-10"/>
</clocks>
</architecture>

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<architecture>
<models>
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout auto="1.0"/>
<!-- <layout width="20" height="20"/> -->
<!--mrFPGA_settings-->
<!-- below is the timing parameters for a single memristor device (or so called RRAM) -->
<!--mrFPGA R="1e3" C="2.24e-17" Tdel="0"-->
<!-- below is the timing parameters for the buffers to insert in channels -->
<!--buffer R="193.5" Cin="3.66e-15" Cout="3.56e-15" Tdel="6.14e-12"/-->
<!--cblock R_opin_cblock="193.5" T_opin_cblock="6.14e-12"/-->
<!--/mrFPGA-->
<!--/mrFPGA_settings-->
<spice_settings>
<parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>
<monte_carlo mc_sim="off" num_mc_points="3" cmos_variation="off" rram_variation="on">
<cmos abs_variation="0.1" num_sigma="1"/>
<rram abs_variation="0.1" num_sigma="1"/>
</monte_carlo>
<measure sim_num_clock_cycle="auto" accuracy="1e-12" accuracy_type="abs">
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measure>
<stimulate>
<clock op_freq="auto" sim_slack="0.2" prog_freq="2.5e6">
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
</clock>
<input>
<rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/>
</input>
</stimulate>
</parameters>
<tech_lib lib_type="industry" transistor_type="TT" lib_path="/research/ece/lnis/CAD_TOOLS/DKITS/wibond_R90_1P4M_v1.3/models/hspice/r90es_logic_v1d3.l" nominal_vdd="1.2" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="100e-9" min_width="120e-9"/>
<pmos model_name="pch" chan_length="100e-9" min_width="120e-9"/>
<io_nmos model_name="nch_25" chan_length="100e-9" min_width="120e-9"/>
<io_pmos model_name="pch_25" chan_length="100e-9" min_width="120e-9"/>
</transistors>
<module_circuit_models>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="inverter" size="3" tapered="off" power_gated="true"/>
<port type="input" prefix="in" size="1" lib_name="I"/>
<port type="input" prefix="EN" size="1" lib_name="EN" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="ENB" size="1" lib_name="ENB" is_global="true" default_val="1" is_config_enable="true"/>
<port type="output" prefix="out" size="1" lib_name="Z"/>
</circuit_model>
<circuit_model type="inv_buf" name="INVD4BWP" prefix="INVD4BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="ZN" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="INVD1BWP" prefix="INVD1BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="ZN" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="INVD2BWP" prefix="INVD2BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="ZN" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="INVD3BWP" prefix="INVD3BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="ZN" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="BUFFD2BWP" prefix="BUFFD2BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="Z" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="BUFFD3BWP" prefix="BUFFD3BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="Z" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="BUFFD1BWP" prefix="BUFFD1BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="Z" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="3" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="3" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_1level" prefix="mux_1level" is_default="1" dump_structural_verilog="true">
<!-- <design_technology type="cmos" structure="one-level"/?]> -->
<design_technology type="rram" ron="2e3" roff="30e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2" structure="one-level" advanced_rram_design="true"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="EN" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="ENB" size="1" is_global="true" default_val="1" is_config_enable="true"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1" circuit_model_name="sram6T_rram"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf4" prefix="mux_1level_tapbuf4" is_default="0" dump_structural_verilog="true">
<!-- <design_technology type="cmos" structure="one-level"/?]> -->
<design_technology type="rram" ron="2e3" roff="30e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2" structure="one-level" advanced_rram_design="true"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="EN" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="ENB" size="1" is_global="true" default_val="1" is_config_enable="true"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1" circuit_model_name="sram6T_rram"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<lut_input_buffer exist="on" circuit_model_name="BUFFD3BWP"/>
<!-- <lut_intermediate_buffer exist="on" circuit_model_name="BUFFD1BWP" location_map="-1-1-"/> -->
<lut_input_inverter exist="on" circuit_model_name="INVD3BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="6"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="64" circuit_model_name="sram6T_rram" default_val="1"/>
</circuit_model>
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
</circuit_model>
<circuit_model type="sram" name="sram6T_rram" prefix="nvsram" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<!--design_technology type="cmos"/-->
<design_technology type="rram" ron="3e3" roff="1e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="read" size="1" is_global="true" default_val="0" />
<port type="input" prefix="nequalize" size="1" is_global="true" default_val="1" />
<port type="output" prefix="out" size="2"/>
<port type="bl" prefix="bl" size="3" default_val="0" inv_circuit_model_name="INVD1BWP"/>
<port type="wl" prefix="wl" size="3" default_val="0" inv_circuit_model_name="INVD1BWP"/>
</circuit_model>
<circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="read" size="1" is_global="true" default_val="0" />
<port type="input" prefix="nequalize" size="1" is_global="true" default_val="0" />
<port type="output" prefix="out" size="2"/>
<port type="bl" prefix="bl" size="1"/>
<port type="wl" prefix="wl" size="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sff" name="sc_ff" prefix="scff" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1"/>
<port type="input" prefix="Reset" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="clk" size="1"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/io.v">
<!--design_technology type="cmos"/-->
<design_technology type="rram" ron="3e3" roff="1e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="inout" prefix="pad" size="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram6T_rram" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="input" prefix="zin" size="1" is_global="true" default_val="0" />
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</module_circuit_models>
</spice_settings>
<device>
<sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="3"/>
<timing C_ipin_cblock="596e-18" T_ipin_cblock="45.54e-12"/>
<area grid_logic_tile_area="0"/>
<!--sram area="6" organization="standalone" circuit_model_name="sram6T"-->
<!--sram area="6" organization="scan-chain" circuit_model_name="sc_dff"-->
<sram area="6">
<verilog organization="memory-bank" circuit_model_name="sram6T_rram" />
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
</device>
<cblocks>
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="45.54e-12" mux_trans_size="1.5" buf_size="4" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
</switch>
</cblocks>
<switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="sb_mux_L4" R="106" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
</switch>
<switch type="mux" name="sb_mux_L2" R="121" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
</switch>
<switch type="mux" name="sb_mux_L1" R="147" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
</switch>
</switchlist>
<segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
<segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb>
</segment>
<segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
</segmentlist>
<complexblocklist>
<!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io" capacity="8" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- physical design description -->
<mode name="io_phy" disabled_in_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad" mode_bits="1">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- IOs can operate as either inputs or outputs.§
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1" physical_pb_type_name="iopad" mode_bits="1">
<output name="inpad" num_pins="1" physical_mode_pin="inpad"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1" physical_pb_type_name="iopad" mode_bits="0">
<input name="outpad" num_pins="1" physical_mode_pin="outpad"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
<!-- Place I/Os on the sides of the FPGA -->
<gridlocations>
<loc type="perimeter" priority="10"/>
</gridlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic
block. Note that the crossbar / local interconnect is considered part of the logic block
area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range.
-->
<pb_type name="clb" area="53894" opin_to_cb="false">
<pin_equivalence_auto_detect input_ports ="off" output_ports="off"/>
<input name="I" num_pins="40" equivalent="true"/>
<output name="O" num_pins="10" equivalent="false"/>
<!--input name="I" num_pins="40" equivalent="true"/-->
<!--output name="O" num_pins="20" equivalent="false"/-->
<clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered
For spice modeling: in each primitive pb_type, user should define a circuit_model_name that linkes to the
defined spice models
-->
<pb_type name="fle" num_pb="10" idle_mode_name="n1_lut6" physical_mode_name="n1_lut6">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- 6-LUT mode definition begin -->
<mode name="n1_lut6">
<!-- Define 6-LUT mode -->
<pb_type name="ble6" num_pb="1">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut" circuit_model_name="lut6">
<input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
2.094e-09
2.094e-09
2.094e-09
2.094e-09
2.094e-09
2.094e-09
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="29e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="16e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
<direct name="direct2" input="lut6.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out" circuit_model_name="mux_1level">
<delay_constant max="2.736e-10" in_port="lut6.out" out_port="ble6.out" />
<delay_constant max="2.736e-10" in_port="ff.Q" out_port="ble6.out" />
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="ble6.in"/>
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
</interconnect>
</mode>
<!-- 6-LUT mode definition end -->
</pb_type>
<interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
delay within the crossbar is 95 ps.
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in" circuit_model_name="mux_1level">
<delay_constant max="1.0877e-09" in_port="clb.I" out_port="fle[9:0].in" />
<delay_constant max="1.0877e-09" in_port="fle[9:0].out" out_port="fle[9:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
</complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification).
-->
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
<!--direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/-->
<!--complete name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/-->
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="top">clb.clk </loc>
<loc side="right">clb.I[19:0] clb.O[4:0] </loc>
<loc side="bottom">clb.I[39:20] clb.O[9:5] </loc>
</pinlocations>
<!-- Place this general purpose logic block in any unspecified column -->
<gridlocations>
<loc type="fill" priority="1"/>
</gridlocations>
</pb_type>
</complexblocklist>
<power>
<local_interconnect C_wire="0"/>
<mux_transistor_size mux_transistor_size="3"/>
<FF_size FF_size="4"/>
<LUT_transistor_size LUT_transistor_size="4"/>
</power>
<clocks>
<clock buffer_size="auto" C_wire="0"/>
</clocks>
</architecture>

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<architecture>
<models>
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout auto="1.0"/>
<!-- <layout width="20" height="20"/> -->
<!--mrFPGA_settings-->
<!-- below is the timing parameters for a single memristor device (or so called RRAM) -->
<!--mrFPGA R="1e3" C="2.24e-17" Tdel="0"-->
<!-- below is the timing parameters for the buffers to insert in channels -->
<!--buffer R="193.5" Cin="3.66e-15" Cout="3.56e-15" Tdel="6.14e-12"/-->
<!--cblock R_opin_cblock="193.5" T_opin_cblock="6.14e-12"/-->
<!--/mrFPGA-->
<!--/mrFPGA_settings-->
<spice_settings>
<parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>
<monte_carlo mc_sim="off" num_mc_points="3" cmos_variation="off" rram_variation="on">
<cmos abs_variation="0.1" num_sigma="1"/>
<rram abs_variation="0.1" num_sigma="1"/>
</monte_carlo>
<measure sim_num_clock_cycle="auto" accuracy="1e-12" accuracy_type="abs">
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measure>
<stimulate>
<clock op_freq="auto" sim_slack="0.2" prog_freq="2.5e6">
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
</clock>
<input>
<rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/>
</input>
</stimulate>
</parameters>
<tech_lib lib_type="industry" transistor_type="TT" lib_path="/research/ece/lnis/CAD_TOOLS/DKITS/wibond_R90_1P4M_v1.3/models/hspice/r90es_logic_v1d3.l" nominal_vdd="1.2" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="100e-9" min_width="120e-9"/>
<pmos model_name="pch" chan_length="100e-9" min_width="120e-9"/>
<io_nmos model_name="nch_25" chan_length="100e-9" min_width="120e-9"/>
<io_pmos model_name="pch_25" chan_length="100e-9" min_width="120e-9"/>
</transistors>
<module_circuit_models>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="inverter" size="3" tapered="off" power_gated="true"/>
<port type="input" prefix="in" size="1" lib_name="I"/>
<port type="input" prefix="EN" size="1" lib_name="EN" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="ENB" size="1" lib_name="ENB" is_global="true" default_val="1" is_config_enable="true"/>
<port type="output" prefix="out" size="1" lib_name="Z"/>
</circuit_model>
<circuit_model type="inv_buf" name="INVD4BWP" prefix="INVD4BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="ZN" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="INVD1BWP" prefix="INVD1BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="ZN" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="INVD2BWP" prefix="INVD2BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="ZN" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="INVD3BWP" prefix="INVD3BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="ZN" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="BUFFD2BWP" prefix="BUFFD2BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="Z" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="BUFFD3BWP" prefix="BUFFD3BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="Z" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="BUFFD1BWP" prefix="BUFFD1BWP" dump_explicit_port_map="true" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" lib_name="I" size="1"/>
<port type="output" prefix="out" lib_name="Z" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="3" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="3" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_1level" prefix="mux_1level" is_default="1" dump_structural_verilog="false">
<!-- <design_technology type="cmos" structure="one-level"/?]> -->
<design_technology type="rram" ron="2e3" roff="30e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2" structure="one-level" advanced_rram_design="true"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="EN" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="ENB" size="1" is_global="true" default_val="1" is_config_enable="true"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1" circuit_model_name="sram6T_rram"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf4" prefix="mux_1level_tapbuf4" is_default="0" dump_structural_verilog="false">
<!-- <design_technology type="cmos" structure="one-level"/?]> -->
<design_technology type="rram" ron="2e3" roff="30e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2" structure="one-level" advanced_rram_design="true"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="EN" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="input" prefix="ENB" size="1" is_global="true" default_val="1" is_config_enable="true"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1" circuit_model_name="sram6T_rram"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<lut_input_buffer exist="on" circuit_model_name="BUFFD3BWP"/>
<!-- <lut_intermediate_buffer exist="on" circuit_model_name="BUFFD1BWP" location_map="-1-1-"/> -->
<lut_input_inverter exist="on" circuit_model_name="INVD3BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="6"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="64" circuit_model_name="sram6T_rram" default_val="1"/>
</circuit_model>
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
</circuit_model>
<circuit_model type="sram" name="sram6T_rram" prefix="nvsram" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<!--design_technology type="cmos"/-->
<design_technology type="rram" ron="3e3" roff="1e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="read" size="1" is_global="true" default_val="0" />
<port type="input" prefix="nequalize" size="1" is_global="true" default_val="1" />
<port type="output" prefix="out" size="2"/>
<port type="bl" prefix="bl" size="3" default_val="0" inv_circuit_model_name="INVD1BWP"/>
<port type="wl" prefix="wl" size="3" default_val="0" inv_circuit_model_name="INVD1BWP"/>
</circuit_model>
<circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="read" size="1" is_global="true" default_val="0" />
<port type="input" prefix="nequalize" size="1" is_global="true" default_val="0" />
<port type="output" prefix="out" size="2"/>
<port type="bl" prefix="bl" size="1"/>
<port type="wl" prefix="wl" size="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sff" name="sc_ff" prefix="scff" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1"/>
<port type="input" prefix="Reset" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="clk" size="1"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists/io.v">
<!--design_technology type="cmos"/-->
<design_technology type="rram" ron="3e3" roff="1e6" wprog_set_nmos="1.5" wprog_reset_nmos="1.6" wprog_set_pmos="3" wprog_reset_pmos="3.2"/>
<input_buffer exist="on" circuit_model_name="INVD1BWP"/>
<output_buffer exist="on" circuit_model_name="INVD1BWP"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="inout" prefix="pad" size="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram6T_rram" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="input" prefix="zin" size="1" is_global="true" default_val="0" />
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</module_circuit_models>
</spice_settings>
<device>
<sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="3"/>
<timing C_ipin_cblock="596e-18" T_ipin_cblock="45.54e-12"/>
<area grid_logic_tile_area="0"/>
<!--sram area="6" organization="standalone" circuit_model_name="sram6T"-->
<!--sram area="6" organization="scan-chain" circuit_model_name="sc_dff"-->
<sram area="6">
<verilog organization="memory-bank" circuit_model_name="sram6T_rram" />
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
</device>
<cblocks>
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="45.54e-12" mux_trans_size="1.5" buf_size="4" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
</switch>
</cblocks>
<switchlist>
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
book area formula. This means the mux transistors are about 5x minimum drive strength.
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
<switch type="mux" name="sb_mux_L4" R="106" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
</switch>
<switch type="mux" name="sb_mux_L2" R="121" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
</switch>
<switch type="mux" name="sb_mux_L1" R="147" Cin="596e-18" Cout="0e-15" Tdel="35.8e-12" mux_trans_size="1.5" buf_size="27.645901" circuit_model_name="mux_1level_tapbuf4" structure="one-level" num_level="1">
</switch>
</switchlist>
<segmentlist>
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
<segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
<segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1</cb>
</segment>
<segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
</segmentlist>
<complexblocklist>
<!-- Define I/O pads begin -->
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
<pb_type name="io" capacity="8" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- physical design description -->
<mode name="io_phy" disabled_in_packing="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad" mode_bits="1">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- IOs can operate as either inputs or outputs.§
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1" physical_pb_type_name="iopad" mode_bits="1">
<output name="inpad" num_pins="1" physical_mode_pin="inpad"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1" physical_pb_type_name="iopad" mode_bits="0">
<input name="outpad" num_pins="1" physical_mode_pin="outpad"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
<!-- Place I/Os on the sides of the FPGA -->
<gridlocations>
<loc type="perimeter" priority="10"/>
</gridlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin -->
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
area is 60 L^2 yields a tile area of 84375 MWTAs.
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
This means that only 37% of our area is in the general routing, and 63% is inside the logic
block. Note that the crossbar / local interconnect is considered part of the logic block
area in this analysis. That is a lower proportion of of routing area than most academics
assume, but note that the total routing area really includes the crossbar, which would push
routing area up significantly, we estimate into the ~70% range.
-->
<pb_type name="clb" area="53894" opin_to_cb="false">
<pin_equivalence_auto_detect input_ports ="off" output_ports="off"/>
<input name="I" num_pins="40" equivalent="true"/>
<output name="O" num_pins="10" equivalent="false"/>
<!--input name="I" num_pins="40" equivalent="true"/-->
<!--output name="O" num_pins="20" equivalent="false"/-->
<clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered
For spice modeling: in each primitive pb_type, user should define a circuit_model_name that linkes to the
defined spice models
-->
<pb_type name="fle" num_pb="10" idle_mode_name="n1_lut6" physical_mode_name="n1_lut6">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- 6-LUT mode definition begin -->
<mode name="n1_lut6">
<!-- Define 6-LUT mode -->
<pb_type name="ble6" num_pb="1">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut" circuit_model_name="lut6">
<input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
2.094e-09
2.094e-09
2.094e-09
2.094e-09
2.094e-09
2.094e-09
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="29e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="16e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
<direct name="direct2" input="lut6.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out" circuit_model_name="mux_1level">
<delay_constant max="2.736e-10" in_port="lut6.out" out_port="ble6.out" />
<delay_constant max="2.736e-10" in_port="ff.Q" out_port="ble6.out" />
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="ble6.in"/>
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
</interconnect>
</mode>
<!-- 6-LUT mode definition end -->
</pb_type>
<interconnect>
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
The delays below come from Stratix IV. the delay through a connection block
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
delay within the crossbar is 95 ps.
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
Since all our outputs LUT outputs go to a BLE output, and have a delay of
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
to get the part that should be marked on the crossbar. -->
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in" circuit_model_name="mux_1level">
<delay_constant max="1.0877e-09" in_port="clb.I" out_port="fle[9:0].in" />
<delay_constant max="1.0877e-09" in_port="fle[9:0].out" out_port="fle[9:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
</complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
naive specification).
-->
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
<!--direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/-->
<!--complete name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/-->
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="top">clb.clk </loc>
<loc side="right">clb.I[19:0] clb.O[4:0] </loc>
<loc side="bottom">clb.I[39:20] clb.O[9:5] </loc>
</pinlocations>
<!-- Place this general purpose logic block in any unspecified column -->
<gridlocations>
<loc type="fill" priority="1"/>
</gridlocations>
</pb_type>
</complexblocklist>
<power>
<local_interconnect C_wire="0"/>
<mux_transistor_size mux_transistor_size="3"/>
<FF_size FF_size="4"/>
<LUT_transistor_size LUT_transistor_size="4"/>
</power>
<clocks>
<clock buffer_size="auto" C_wire="0"/>
</clocks>
</architecture>

802
openfpga_flow/benchmarks/MCNC_Verilog/alu4/alu4.v Normal file
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@ -0,0 +1,802 @@
// Benchmark "TOP" written by ABC on Mon Feb 4 10:08:03 2019
module alu4 (
i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_,
i_11_, i_12_, i_13_,
o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_ );
input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_,
i_10_, i_11_, i_12_, i_13_;
output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_;
wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57,
n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135,
n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219,
n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231,
n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243,
n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267,
n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279,
n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291,
n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303,
n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327,
n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351,
n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363,
n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375,
n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387,
n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399,
n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411,
n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423,
n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471,
n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483,
n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495,
n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543,
n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603,
n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663,
n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675,
n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699,
n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751;
assign o_0_ = ~n42;
assign o_1_ = ~n509;
assign o_2_ = ~n502;
assign o_3_ = ~n488;
assign o_4_ = ~n41;
assign o_5_ = ~n659 | ~n662 | n40 | ~n658 | n38 | n39 | n36 | n37;
assign o_6_ = ~n35;
assign o_7_ = ~n636 | ~n637 | n34 | ~n576 | n32 | n33 | n30 | n31;
assign n30 = ~i_9_ & (~n163 | n165 | n168);
assign n31 = i_9_ & n65 & n419;
assign n32 = ~i_5_ & (~n625 | (~n238 & n250));
assign n33 = i_9_ & (n66 | ~n621 | ~n622);
assign n34 = n244 | n246 | n240 | n242 | ~n630 | ~n632 | n248 | n249;
assign n35 = n278 & n279 & (~i_2_ | n277);
assign n36 = i_11_ & (~n650 | (~n266 & n360));
assign n37 = i_2_ & n361 & n272;
assign n38 = ~n71 & ~n532;
assign n39 = ~n562 & (~n648 | (~i_13_ & ~n532));
assign n40 = ~i_4_ & (~n647 | (~n59 & ~n281));
assign n41 = n473 & n472 & n471 & n470 & n469 & ~n465 & ~n459 & ~n461;
assign n42 = ~n46 & n510 & (~i_0_ | n511);
assign n43 = ~i_1_ | ~i_3_;
assign n44 = ~i_5_ | n43;
assign n45 = ~i_8_ & i_10_;
assign n46 = i_3_ & (n45 | ~n435);
assign n47 = ~n67 & (~i_6_ | ~i_10_);
assign n48 = (n521 | n52) & (n56 | n120);
assign n49 = i_1_ | n445;
assign n50 = i_11_ | n116;
assign n51 = n48 & (n49 | n50);
assign n52 = i_12_ | n116;
assign n53 = i_0_ | n225;
assign n54 = (i_11_ | n53) & (n49 | n52);
assign n55 = ~i_6_ | i_7_;
assign n56 = i_0_ | n212;
assign n57 = ~i_2_ | i_0_ | i_1_;
assign n58 = (i_6_ | n57) & (n55 | n56);
assign n59 = ~i_3_ | n225;
assign n60 = ~i_3_ | n445;
assign n61 = (~i_6_ | n60) & (~i_5_ | n59);
assign n62 = i_0_ | n63;
assign n63 = i_3_ | i_2_;
assign n64 = n62 & (~i_5_ | n63);
assign n65 = ~i_12_ & i_13_;
assign n66 = n65 & (~n613 | (i_8_ & ~n379));
assign n67 = i_6_ & n519;
assign n68 = ~n158 & (~n615 | (n67 & ~n400));
assign n69 = (i_7_ | n200) & (i_6_ | n62);
assign n70 = n69 & (i_8_ | n56);
assign n71 = ~i_12_ | n116;
assign n72 = (~i_1_ | n71) & (~i_6_ | ~n348);
assign n73 = ~i_1_ & i_6_;
assign n74 = (~i_0_ | n73) & (~i_1_ | i_5_);
assign n75 = ~n304 & ~i_9_ & ~n77;
assign n76 = i_3_ & (n75 | (~n71 & ~n98));
assign n77 = ~i_11_ | n116;
assign n78 = i_8_ | i_6_;
assign n79 = n77 | n78 | ~i_2_ | i_9_;
assign n80 = ~i_0_ | n63;
assign n81 = ~i_0_ | n195;
assign n82 = (i_7_ | n81) & (i_6_ | n80);
assign n83 = i_0_ & (n76 | ~n79 | ~n627);
assign n84 = i_3_ | ~i_11_ | n56 | ~n348;
assign n85 = n116 | n400 | ~i_3_ | i_9_;
assign n86 = n178 | ~i_5_ | n72;
assign n87 = n516 | n177 | ~n338;
assign n88 = i_9_ | n74 | n522 | n77;
assign n89 = n88 & n87 & n86 & n85 & ~n83 & n84;
assign n90 = (n99 | n157) & (n134 | n521);
assign n91 = ~i_6_ | n522;
assign n92 = n90 & (n91 | n49);
assign n93 = (~n102 | n521) & (~n67 | n157);
assign n94 = (n518 | n49) & (n520 | n400);
assign n95 = n93 & n94;
assign n96 = (~n103 | n134) & (n53 | n107);
assign n97 = n96 & (n57 | n91);
assign n98 = ~i_6_ | n272;
assign n99 = i_8_ | ~i_6_ | ~i_7_;
assign n100 = n98 & n97 & (n99 | n56);
assign n101 = i_5_ & n365;
assign n102 = ~i_6_ & n519;
assign n103 = ~i_2_ & ~i_0_ & i_1_;
assign n104 = n101 & (~n607 | (n102 & n103));
assign n105 = i_11_ | ~n166;
assign n106 = i_10_ | n304;
assign n107 = i_6_ | n522;
assign n108 = (n107 | n50) & (n105 | n106);
assign n109 = i_12_ | n113;
assign n110 = i_11_ | n113;
assign n111 = (~n67 | n109) & (n99 | n110);
assign n112 = i_11_ | i_12_;
assign n113 = i_9_ | i_13_;
assign n114 = i_3_ | i_10_ | n112 | n113;
assign n115 = i_5_ | n312;
assign n116 = i_10_ | i_13_;
assign n117 = (~i_10_ | n115) & (n116 | ~n164);
assign n118 = i_13_ & (~n600 | (~n547 & ~n548));
assign n119 = i_5_ | n515;
assign n120 = i_12_ | ~n338;
assign n121 = (n119 | n120) & (~n164 | ~n239);
assign n122 = n65 & (~n599 | (~i_3_ & ~i_11_));
assign n123 = n555 | n518 | n554;
assign n124 = n553 | n134 | n552;
assign n125 = n522 | n198 | ~n247;
assign n126 = ~n348 | ~n67 | ~n101;
assign n127 = n449 | n107 | ~n338;
assign n128 = n524 | n99 | ~n319;
assign n129 = (n544 | n546) & (n121 | n520);
assign n130 = n129 & n128 & n127 & n126 & n125 & n124 & ~n122 & n123;
assign n131 = (n107 | ~n419) & (n91 | ~n402);
assign n132 = (n171 | n151) & (n150 | n551);
assign n133 = n597 & n598 & (n545 | n550);
assign n134 = ~i_7_ | n78;
assign n135 = ~n101 | ~n239;
assign n136 = n132 & n133 & (n134 | n135);
assign n137 = i_4_ | ~i_0_ | ~i_1_;
assign n138 = i_4_ | n445;
assign n139 = (~i_6_ | n138) & (~i_7_ | n137);
assign n140 = ~n524 & ~n220 & i_2_ & ~i_8_;
assign n141 = n546 | n549;
assign n142 = n162 | n107 | n158;
assign n143 = n555 | ~n102 | n554;
assign n144 = n553 | n91 | n552;
assign n145 = (n194 | n151) & (n198 | n551);
assign n146 = (n134 | n543) & (n547 | n550);
assign n147 = n146 & n145 & n144 & n143 & n141 & n142;
assign n148 = (n171 | n551) & (n99 | n543);
assign n149 = n595 & n596 & (n545 | n549);
assign n150 = ~i_5_ | n201;
assign n151 = ~n65 | ~n264;
assign n152 = n148 & n149 & (n150 | n151);
assign n153 = (n99 | ~n402) & (n91 | ~n419);
assign n154 = (n544 | n547) & (n172 | n198);
assign n155 = n593 & n594 & (n542 | n546);
assign n156 = n154 & n155 & (n91 | n135);
assign n157 = ~i_0_ | n212;
assign n158 = ~i_5_ | n312;
assign n159 = n158 | n157 | n134;
assign n160 = n115 | n99 | ~n103;
assign n161 = i_2_ | n312;
assign n162 = ~i_10_ | ~n319;
assign n163 = n161 | n162 | ~i_5_ | n91;
assign n164 = ~i_5_ & i_3_ & i_4_;
assign n165 = n164 & ~n77 & i_1_ & ~i_7_;
assign n166 = ~i_12_ & ~i_13_;
assign n167 = i_10_ & i_11_;
assign n168 = n166 & n167 & (~n159 | ~n160);
assign n169 = (n542 | n545) & (n541 | n150);
assign n170 = (n107 | n135) & (~n446 | n544);
assign n171 = i_3_ | n539;
assign n172 = ~n65 | ~n437;
assign n173 = n169 & n170 & (n171 | n172);
assign n174 = (~n446 | n542) & (n171 | n541);
assign n175 = (n544 | n545) & (n91 | n543);
assign n176 = n174 & n175 & (n172 | n150);
assign n177 = i_10_ | n522;
assign n178 = ~i_8_ | n272;
assign n179 = n177 & n178;
assign n180 = (~n460 | n591) & (n179 | ~n463);
assign n181 = n592 & (n533 | n56);
assign n182 = n106 & n98;
assign n183 = n180 & n181 & (n182 | ~n385);
assign n184 = (~n340 | n535) & (n106 | n449);
assign n185 = i_8_ | n534;
assign n186 = ~i_4_ | n212;
assign n187 = n184 & (n185 | n186);
assign n188 = (~n536 | n537) & (n335 | n538);
assign n189 = (n186 | n474) & (n98 | ~n101);
assign n190 = ~i_5_ | n272;
assign n191 = n188 & n189 & (n190 | ~n340);
assign n192 = (n518 | n521) & (n520 | n157);
assign n193 = n192 & (n49 | ~n102);
assign n194 = i_3_ | n214;
assign n195 = i_1_ | i_3_;
assign n196 = n194 & (~i_5_ | n195);
assign n197 = ~i_6_ | i_0_ | i_3_;
assign n198 = i_3_ | n516;
assign n199 = n198 & (i_5_ | n195);
assign n200 = i_0_ | n195;
assign n201 = i_3_ | i_6_;
assign n202 = n200 & n199 & (i_0_ | n201);
assign n203 = ~i_6_ | ~i_0_ | ~i_3_;
assign n204 = i_1_ & ~i_6_;
assign n205 = (i_2_ | ~i_6_) & (~i_7_ | n204);
assign n206 = n517 | i_6_ | n749;
assign n207 = n517 | i_1_ | i_7_;
assign n208 = i_11_ | n435;
assign n209 = n206 & n207 & (n205 | n208);
assign n210 = i_5_ | n63;
assign n211 = i_2_ | n516;
assign n212 = i_1_ | i_2_;
assign n213 = n211 & (i_5_ | n212);
assign n214 = ~i_5_ | ~i_6_;
assign n215 = (~i_5_ | n212) & (i_2_ | n214);
assign n216 = (~i_5_ | n225) & (~i_2_ | n214);
assign n217 = ~i_6_ | n445;
assign n218 = n216 & n217;
assign n219 = ~i_7_ | ~i_1_ | ~i_5_;
assign n220 = ~i_1_ & ~i_6_;
assign n221 = n219 & (~i_0_ | ~i_7_ | n220);
assign n222 = i_10_ & ~n435 & (~n218 | ~n221);
assign n223 = ~i_2_ | n516;
assign n224 = i_6_ | n445;
assign n225 = ~i_1_ | ~i_2_;
assign n226 = n223 & n224 & (i_5_ | n225);
assign n227 = n226 & (i_7_ | n74);
assign n228 = (~i_0_ | i_6_) & (~i_1_ | i_5_);
assign n229 = (i_6_ | n138) & (i_7_ | n137);
assign n230 = n73 | n119 | ~i_2_ | ~i_8_;
assign n231 = n230 & (n229 | ~n475);
assign n232 = (n53 | ~n67) & (~n103 | n518);
assign n233 = n232 & (n57 | ~n102);
assign n234 = ~i_4_ | n225;
assign n235 = ~i_4_ | n557;
assign n236 = (i_6_ | n235) & (i_8_ | n234);
assign n237 = i_4_ & (~n623 | (~i_1_ & ~n177));
assign n238 = ~n237 & (i_6_ | i_10_ | ~n536);
assign n239 = ~i_9_ & n338;
assign n240 = n239 & n164 & ~n233;
assign n241 = n406 & ~i_10_ & ~i_13_;
assign n242 = ~n119 & (~n580 | (~n92 & n241));
assign n243 = ~i_3_ & ~i_8_;
assign n244 = ~n525 & (n140 | (~n139 & n243));
assign n245 = n383 & ~i_9_ & ~i_13_;
assign n246 = ~n524 & (~n582 | (~n193 & n245));
assign n247 = ~i_11_ & i_13_;
assign n248 = n247 & (~n584 | (~n223 & ~n528));
assign n249 = n65 & (~n586 | ~n588 | ~n590);
assign n250 = n338 & i_12_;
assign n251 = n250 & (~n183 | ~n187 | ~n191);
assign n252 = ~n71 & (~n609 | ~n610 | ~n611);
assign n253 = ~n247 & (i_4_ | ~i_8_ | ~n406);
assign n254 = (~i_3_ | n208) & (~n338 | n533);
assign n255 = n253 & n254 & (n120 | ~n475);
assign n256 = ~i_7_ | i_10_;
assign n257 = i_4_ | ~n383;
assign n258 = (~i_7_ | n257) & (n256 | ~n318);
assign n259 = i_7_ & n45;
assign n260 = (i_8_ | n258) & (~n259 | n559);
assign n261 = n260 & ~n731 & (i_7_ | n255);
assign n262 = ~i_7_ | ~i_9_;
assign n263 = n262 & (i_7_ | ~i_10_);
assign n264 = i_10_ & ~i_7_ & i_8_;
assign n265 = i_12_ & (n264 | ~n548);
assign n266 = ~i_10_ | n522;
assign n267 = i_8_ | n262;
assign n268 = ~n265 & (~i_11_ | (n266 & n267));
assign n269 = (n110 | ~n243) & (n109 | ~n475);
assign n270 = ~i_4_ | n116;
assign n271 = n270 & (~i_8_ | n52);
assign n272 = ~i_7_ | i_9_;
assign n273 = ~i_4_ | n272;
assign n274 = (i_7_ | n271) & (i_13_ | n273);
assign n275 = n282 & (i_4_ | n268);
assign n276 = n556 & n638 & (i_3_ | n274);
assign n277 = n275 & n276 & (~i_13_ | n263);
assign n278 = ~n750 & (n548 | n559);
assign n279 = n644 & n645 & (i_2_ | n261);
assign n280 = ~i_6_ | ~i_9_;
assign n281 = n280 & (i_6_ | ~i_10_);
assign n282 = n332 | n116;
assign n283 = (n523 & (~i_7_ | n733)) | (i_7_ & n733);
assign n284 = i_2_ | i_13_;
assign n285 = n282 & (n283 | n284);
assign n286 = i_10_ | i_7_;
assign n287 = i_11_ | n286;
assign n288 = i_11_ | i_13_;
assign n289 = (~n166 | n287) & (n177 | n288);
assign n290 = i_8_ | n272;
assign n291 = (n288 | n290) & (~n166 | n178);
assign n292 = (n289 & (~i_6_ | n291)) | (i_6_ & n291);
assign n293 = (n523 & (~i_8_ | n733)) | (i_8_ & n733);
assign n294 = n292 & (i_13_ | n293);
assign n295 = (~i_7_ & n566) | (n565 & (i_7_ | n566));
assign n296 = i_7_ | n435;
assign n297 = n295 & (~i_6_ | ~i_11_ | n296);
assign n298 = n287 & (i_12_ | n256);
assign n299 = ~i_2_ & ~n751 & (i_6_ | ~n298);
assign n300 = ~n299 & (~i_4_ | ~n578);
assign n301 = n591 | i_2_ | ~i_4_;
assign n302 = n300 & n301 & (n182 | ~n365);
assign n303 = ~i_7_ | n280;
assign n304 = i_6_ | i_7_;
assign n305 = n303 & (~i_10_ | (~i_9_ & n304));
assign n306 = (i_6_ & ~n540) | (~n266 & (~i_6_ | ~n540));
assign n307 = ~i_4_ & (~n577 | (i_11_ & n306));
assign n308 = (n294 & (~i_3_ | n297)) | (i_3_ & n297);
assign n309 = (~i_13_ & n302) | (n281 & (i_13_ | n302));
assign n310 = ~n307 & n656 & (~i_2_ | n305);
assign n311 = n310 & n309 & n308 & n285;
assign n312 = ~i_3_ | i_4_;
assign n313 = (n312 | ~n406) & (n284 | ~n383);
assign n314 = (~i_4_ | ~n338) & (i_3_ | n120);
assign n315 = ~n247 & (~i_3_ | ~n406 | n548);
assign n316 = (~i_2_ | n530) & (~i_7_ | n313);
assign n317 = n315 & n316 & (n314 | n178);
assign n318 = i_4_ & n348;
assign n319 = ~i_11_ & n348;
assign n320 = ~n177 & (n318 | (~i_3_ & n319));
assign n321 = ~n402 | ~i_2_ | i_7_;
assign n322 = ~n319 | n563;
assign n323 = ~n383 | ~i_3_ | n266;
assign n324 = n257 | ~i_2_ | i_8_;
assign n325 = ~n65 & (i_7_ | n312 | ~n383);
assign n326 = n325 & n324 & n323 & n322 & ~n320 & n321;
assign n327 = i_11_ | ~n496 | n558 | ~n563;
assign n328 = (n317 & (~i_6_ | n326)) | (i_6_ & n326);
assign n329 = n327 & n328 & (n91 | n257);
assign n330 = ~i_11_ | n514;
assign n331 = ~n166 | ~n475;
assign n332 = ~i_4_ | i_9_;
assign n333 = (n332 | n77) & (n330 | n331);
assign n334 = ~n517 & i_3_ & i_12_;
assign n335 = i_1_ | n63;
assign n336 = ~i_11_ | ~n166;
assign n337 = (n335 | n336) & (n186 | ~n239);
assign n338 = i_11_ & ~i_13_;
assign n339 = i_4_ & (~n652 | (~n335 & n338));
assign n340 = ~i_1_ & n365;
assign n341 = i_7_ & (n334 | (n340 & n239));
assign n342 = n734 & (~i_8_ | n337);
assign n343 = (n208 | n561) & (n404 | n356);
assign n344 = (n517 | n557) & (~n45 | n59);
assign n345 = n344 & n343 & n342 & ~n341 & n333 & ~n339;
assign n346 = ~i_2_ | i_12_;
assign n347 = (~i_8_ | n59) & (n346 | ~n391);
assign n348 = i_12_ & ~i_13_;
assign n349 = n348 & (~n654 | (i_4_ & ~n335));
assign n350 = n655 & (i_8_ | ~n402 | n561);
assign n351 = ~n349 & n350 & (~i_9_ | n347);
assign n352 = ~i_8_ | i_9_;
assign n353 = (~n263 | ~n340) & (n186 | n352);
assign n354 = i_10_ | n78;
assign n355 = ~i_6_ | n352;
assign n356 = ~i_1_ | n312;
assign n357 = (n303 | n356) & (~n259 | ~n360);
assign n358 = ~n573 & (~i_4_ | i_13_ | ~n496);
assign n359 = ~n512 & (i_6_ | i_11_);
assign n360 = i_3_ & n204;
assign n361 = ~i_6_ & n419;
assign n362 = ~i_9_ | ~i_11_;
assign n363 = ~i_12_ | n362;
assign n364 = ~i_4_ | n113;
assign n365 = ~i_3_ & i_4_;
assign n366 = ~i_9_ | ~i_12_;
assign n367 = n364 & (n365 | n366);
assign n368 = (~i_9_ & n572) | (~i_13_ & (i_9_ | n572));
assign n369 = i_3_ | n111;
assign n370 = ~n166 | i_2_ | n98;
assign n371 = (~i_1_ | n280) & (n363 | ~n391);
assign n372 = (~n67 | n367) & (i_4_ | n363);
assign n373 = ~n737 & n372 & n371 & n370 & n368 & n369;
assign n374 = ~i_4_ & (~n564 | (~n107 & n167));
assign n375 = ~n736 & (~i_10_ | (~i_13_ & ~n204));
assign n376 = ~n374 & n687 & (n107 | n270);
assign n377 = n375 & n376 & (i_3_ | n108);
assign n378 = i_7_ | n516;
assign n379 = ~i_7_ | n214;
assign n380 = (n113 | n379) & (n378 | n116);
assign n381 = ~i_2_ & (~n686 | (~n270 & ~n440));
assign n382 = ~n53 & i_3_ & ~i_8_;
assign n383 = i_11_ & ~i_12_;
assign n384 = n383 & i_10_ & ~i_0_ & i_2_;
assign n385 = ~i_0_ & n365;
assign n386 = ~i_6_ & (n384 | (~n71 & n385));
assign n387 = (n56 | ~n319) & (n53 | ~n402);
assign n388 = i_0_ | n43;
assign n389 = ~n386 & n387 & (n257 | n388);
assign n390 = (~i_7_ | n81) & (~i_6_ | n80);
assign n391 = i_8_ & i_3_;
assign n392 = ~n400 & (i_7_ | n391);
assign n393 = (i_3_ & n553) | (~n241 & (~i_3_ | n553));
assign n394 = n257 & n393 & (~i_4_ | n71);
assign n395 = ~i_12_ | n572;
assign n396 = ~n65 & (i_2_ | n106 | ~n319);
assign n397 = n395 & n396 & (n394 | n107);
assign n398 = ~i_7_ | n362;
assign n399 = (i_2_ | n355) & (n204 | n178);
assign n400 = ~i_1_ | n445;
assign n401 = (~i_8_ | n400) & (~i_6_ | n60);
assign n402 = i_10_ & ~i_12_;
assign n403 = n402 & (n382 | (~i_0_ & n204));
assign n404 = i_7_ | ~n167;
assign n405 = n167 & (~n718 | (~i_8_ & ~n400));
assign n406 = ~i_11_ & i_12_;
assign n407 = n406 & (~n674 | (i_8_ & ~n53));
assign n408 = ~i_0_ | n43;
assign n409 = ~n405 & ~n407 & (n404 | n408);
assign n410 = ~n247 & (~i_1_ | i_11_ | n280);
assign n411 = n672 & (~n67 | (~n423 & n673));
assign n412 = n410 & n411 & (~n73 | n336);
assign n413 = ~n385 | ~i_6_ | ~n239;
assign n414 = ~n166 | ~i_11_ | n56;
assign n415 = n413 & n414 & (n200 | ~n423);
assign n416 = n238 & (~i_4_ | i_6_ | n177);
assign n417 = ~i_7_ & n419;
assign n418 = n417 & i_2_ & i_12_;
assign n419 = i_10_ & ~i_11_;
assign n420 = n116 | ~i_4_ | i_8_;
assign n421 = n420 & (n50 | ~n243);
assign n422 = ~n53 & (~n530 | (i_3_ & ~n208));
assign n423 = i_4_ & n239;
assign n424 = i_6_ & (n418 | (~n62 & n423));
assign n425 = (n517 | n59) & (i_4_ | n409);
assign n426 = (~i_7_ | n415) & (i_0_ | n412);
assign n427 = (n82 | n271) & (~n338 | n416);
assign n428 = (~i_1_ | ~n361) & (~n423 | n671);
assign n429 = (n157 | n421) & (n400 | ~n670);
assign n430 = ~n422 & (n56 | n120 | ~n475);
assign n431 = n430 & n429 & n428 & n427 & n426 & n425 & n333 & ~n424;
assign n432 = n183 & (~i_4_ | i_10_ | n70);
assign n433 = i_7_ | i_9_ | i_11_;
assign n434 = n191 & (n215 | n433);
assign n435 = ~i_8_ | ~i_9_;
assign n436 = i_5_ & ~n558 & (~n540 | ~n568);
assign n437 = i_10_ & n519;
assign n438 = ~i_4_ & ~n539 & (n437 | ~n568);
assign n439 = ~i_8_ | n214;
assign n440 = i_8_ | n516;
assign n441 = (n366 | n439) & (~n167 | n440);
assign n442 = ~i_12_ & (~n158 | n417 | ~n530);
assign n443 = n435 | ~i_3_ | n112;
assign n444 = ~n442 & n443 & (i_11_ | n115);
assign n445 = ~i_0_ | ~i_2_;
assign n446 = ~i_6_ & i_3_ & i_5_;
assign n447 = n383 & (~n684 | (~i_7_ & n446));
assign n448 = n406 & (~n685 | (i_7_ & ~n545));
assign n449 = i_5_ | ~n365;
assign n450 = (~n338 | n449) & (~n101 | ~n348);
assign n451 = i_5_ | n522;
assign n452 = (n80 | n440) & (n81 | n451);
assign n453 = ~i_5_ | ~n519;
assign n454 = (n453 | n81) & (n439 | n80);
assign n455 = n137 & n408;
assign n456 = ~i_0_ | n312;
assign n457 = (n379 | n456) & (n455 | n453);
assign n458 = ~i_5_ & i_0_ & i_3_;
assign n459 = n167 & (~n663 | (~n107 & n458));
assign n460 = i_4_ & ~i_0_ & ~i_2_;
assign n461 = ~n569 & (~n664 | (n239 & n460));
assign n462 = ~i_5_ & n519;
assign n463 = i_4_ & ~i_0_ & ~i_1_;
assign n464 = n462 & (~n665 | (n239 & n463));
assign n465 = ~n570 & (~n666 | (~n71 & n463));
assign n466 = ~n571 & (~n667 | (~n71 & n460));
assign n467 = n406 & (n438 | (n259 & ~n545));
assign n468 = n383 & (n436 | (~n296 & n446));
assign n469 = (n450 | n56) & (n441 | n60);
assign n470 = ~n464 & (~i_9_ | n158 | n400);
assign n471 = n702 & n701 & (n452 | n50);
assign n472 = n699 & n698 & (n457 | n366);
assign n473 = ~n740 & ~n739 & n709 & n707 & n706 & n705 & n703 & n704;
assign n474 = ~i_5_ | n352;
assign n475 = ~i_3_ & i_8_;
assign n476 = ~n56 & (i_7_ | n475);
assign n477 = (i_1_ | n537) & (n589 | n178);
assign n478 = ~n476 & n715 & (n335 | n474);
assign n479 = n477 & n478 & (i_0_ | ~i_5_);
assign n480 = ~n56 & (~i_7_ | n243);
assign n481 = n300 & (i_1_ | n359);
assign n482 = n746 & (i_5_ | n416);
assign n483 = n187 & (i_3_ | n293);
assign n484 = (n56 | ~n365) & (i_12_ | n479);
assign n485 = (n213 | n298) & (n215 | n574);
assign n486 = n716 & (i_1_ | n359 | n534);
assign n487 = n717 & (i_11_ | (n714 & n711));
assign n488 = n487 & n486 & n485 & n484 & n483 & n482 & n432 & n434;
assign n489 = ~i_7_ | n366;
assign n490 = ~i_10_ | ~i_12_;
assign n491 = n489 & ~n496 & (i_7_ | n490);
assign n492 = (n747 & (~i_5_ | n748)) | (i_5_ & n748);
assign n493 = n492 & (~i_0_ | n281);
assign n494 = i_8_ | ~i_11_;
assign n495 = ~n496 & n494 & ~i_3_ & n263;
assign n496 = i_8_ & i_12_;
assign n497 = n496 & (~n221 | ~n379);
assign n498 = (n218 | n491) & (~i_1_ | n493);
assign n499 = n726 & (~i_12_ | (n61 & n723));
assign n500 = n725 & (~i_11_ | (n719 & n722));
assign n501 = n724 & (n494 | (n227 & n378));
assign n502 = n501 & n500 & n498 & n499;
assign n503 = i_12_ | ~n475;
assign n504 = ~n46 & n503 & (i_11_ | ~n243);
assign n505 = (~n243 | ~n338) & (n113 | ~n391);
assign n506 = (~n243 | ~n247) & (~n65 | ~n475);
assign n507 = (n504 & (~i_4_ | n505)) | (i_4_ & n505);
assign n508 = n727 & n728 & (~i_13_ | ~n46);
assign n509 = n508 & n506 & n507;
assign n510 = (~i_1_ | n281) & (~i_2_ | n263);
assign n511 = (~i_5_ & ~i_10_) | (~i_9_ & (i_5_ | ~i_10_));
assign n512 = i_6_ & ~i_12_;
assign n513 = i_9_ & (n392 | (n512 & i_1_));
assign n514 = i_9_ | i_10_;
assign n515 = i_3_ | i_4_;
assign n516 = i_5_ | i_6_;
assign n517 = i_8_ | ~n419;
assign n518 = ~i_8_ | n55;
assign n519 = i_8_ & i_7_;
assign n520 = ~i_8_ | n304;
assign n521 = i_2_ | ~i_0_ | ~i_1_;
assign n522 = i_8_ | i_7_;
assign n523 = i_11_ | n514;
assign n524 = ~i_5_ | n515;
assign n525 = ~n348 | n523;
assign n526 = ~i_9_ | ~i_10_;
assign n527 = i_7_ | n526;
assign n528 = ~i_3_ | n526;
assign n529 = ~i_7_ | n526;
assign n530 = i_11_ | n262;
assign n531 = ~i_5_ | ~i_3_ | ~i_4_;
assign n532 = ~i_6_ | n332;
assign n533 = ~i_8_ | n332;
assign n534 = i_5_ | i_10_;
assign n535 = i_7_ | n534;
assign n536 = ~i_2_ & n365;
assign n537 = i_9_ | n214;
assign n538 = ~i_5_ | n332;
assign n539 = i_5_ | ~i_6_;
assign n540 = ~i_9_ | n522;
assign n541 = ~n247 | n540;
assign n542 = ~n65 | ~n259;
assign n543 = ~n239 | n449;
assign n544 = ~n247 | n296;
assign n545 = ~i_3_ | n539;
assign n546 = ~i_3_ | n516;
assign n547 = ~i_3_ | n214;
assign n548 = ~i_7_ | n435;
assign n549 = ~n247 | n548;
assign n550 = ~n65 | n266;
assign n551 = ~n247 | n267;
assign n552 = i_13_ | n115;
assign n553 = ~i_11_ | ~n402;
assign n554 = i_13_ | n158;
assign n555 = ~i_9_ | ~n406;
assign n556 = n114 & n528;
assign n557 = ~i_2_ | ~i_3_;
assign n558 = i_4_ | i_6_;
assign n559 = ~i_3_ | i_12_;
assign n560 = i_4_ | n225;
assign n561 = i_1_ | n557;
assign n562 = ~i_1_ | n63;
assign n563 = i_7_ | i_2_;
assign n564 = ~i_11_ | n490;
assign n565 = ~i_9_ | n490;
assign n566 = ~i_9_ | ~n167;
assign n567 = ~i_8_ | n286;
assign n568 = i_0_ | n557;
assign n569 = ~i_8_ | n539;
assign n570 = ~i_5_ | n522;
assign n571 = ~i_5_ | n78;
assign n572 = ~n220 | n288;
assign n573 = n243 & n319;
assign n574 = i_12_ | n272;
assign n575 = (~i_5_ & n419) | (n402 & (i_5_ | n419));
assign n576 = (~i_4_ & n729) | (n89 & (i_4_ | n729));
assign n577 = (~i_6_ & n564) | (n363 & (i_6_ | n564));
assign n578 = (i_6_ & ~n178) | (~n177 & (~i_6_ | ~n178));
assign n579 = i_10_ | i_13_ | ~n383 | n520;
assign n580 = n579 & (n233 | ~n245);
assign n581 = i_9_ | i_13_ | n99 | ~n406;
assign n582 = n581 & (n97 | ~n241);
assign n583 = n527 | ~i_3_ | n228;
assign n584 = n583 & (i_8_ | n227 | n526);
assign n585 = (n213 | n517) & (n210 | ~n361);
assign n586 = ~n222 & n585 & (n208 | n215);
assign n587 = n547 & n408 & n44 & n203;
assign n588 = (n587 | n529) & (i_0_ | n209);
assign n589 = n196 & n200 & n197;
assign n590 = (n530 | n589) & (n202 | ~n417);
assign n591 = n355 & n354;
assign n592 = (n273 | n200) & (n62 | n532);
assign n593 = n541 | n194;
assign n594 = n113 | n153 | n158;
assign n595 = ~n402 | n107 | n158;
assign n596 = ~n446 | n550;
assign n597 = ~n446 | n549;
assign n598 = n113 | n131 | n158;
assign n599 = (~n259 | n547) & (n194 | ~n519);
assign n600 = n528 & (n546 | n266);
assign n601 = n531 | ~n67 | n113;
assign n602 = n601 & (n117 | n107);
assign n603 = (n99 | n135) & (n198 | n151);
assign n604 = n602 & n603 & (n194 | n551);
assign n605 = (n108 | n119) & (n111 | n524);
assign n606 = ~n118 & n605 & (i_4_ | n556);
assign n607 = (n518 | n57) & (n53 | n520);
assign n608 = (n95 | n449) & (n92 | ~n164);
assign n609 = ~n104 & n608 & (n100 | n531);
assign n610 = (n537 | n235) & (n474 | n234);
assign n611 = (n273 | n408) & (n538 | n59);
assign n612 = n64 | ~i_6_ | i_11_;
assign n613 = n612 & (~i_10_ | n61);
assign n614 = i_10_ | ~n103 | ~n319 | n520;
assign n615 = n614 & (n58 | n162);
assign n616 = i_10_ | n157 | ~n319 | n518;
assign n617 = n616 & (n47 | n57 | n120);
assign n618 = n617 & (n520 | n521 | n50);
assign n619 = (n54 | ~n67) & (n51 | ~n102);
assign n620 = n161 | n534 | ~n102 | n120;
assign n621 = n620 & (i_4_ | n59 | ~n575);
assign n622 = ~n68 & (n115 | (n618 & n619));
assign n623 = (i_2_ | n354) & (i_10_ | n335);
assign n624 = i_11_ | n266 | n59 | n558;
assign n625 = n624 & (i_9_ | n236 | n77);
assign n626 = n355 | ~i_2_ | n71;
assign n627 = n626 & (n220 | n71 | n178);
assign n628 = n332 | i_10_ | ~n250;
assign n629 = n628 & (~n166 | n231 | n330);
assign n630 = n629 & (~i_13_ | n378 | n517);
assign n631 = n531 | n193 | ~n239;
assign n632 = ~n251 & n631 & (~n103 | n176);
assign n633 = (n156 | n521) & (n173 | n157);
assign n634 = n633 & (n152 | n53);
assign n635 = (n136 | n49) & (n147 | n57);
assign n636 = n635 & n634 & (n130 | n56);
assign n637 = ~n252 & (n400 | (n604 & n606));
assign n638 = n730 & (~i_7_ | n269);
assign n639 = ~n435 | ~i_4_ | n77;
assign n640 = n639 & (i_8_ | i_13_ | n235);
assign n641 = (i_11_ | n161) & (~n338 | ~n536);
assign n642 = n235 | ~i_8_ | i_13_;
assign n643 = n642 & (~n348 | (n533 & ~n536));
assign n644 = n312 | ~i_2_ | n263;
assign n645 = ~n732 & (i_7_ | (n640 & n641));
assign n646 = ~n563 | ~n361 | ~n496;
assign n647 = n646 & (n359 | n561);
assign n648 = (n288 | n354) & (~n166 | n355);
assign n649 = ~i_8_ | i_3_ | i_6_ | n749 | i_10_ | ~n166;
assign n650 = n649 & (~n348 | n353);
assign n651 = i_10_ | i_13_ | n749 | n494;
assign n652 = n651 & (n116 | n562);
assign n653 = i_10_ | i_8_;
assign n654 = (n286 | ~n340) & (n186 | n653);
assign n655 = n335 | i_8_ | ~n319;
assign n656 = n365 | n548 | ~i_6_ | ~i_12_;
assign n657 = ~i_3_ | ~i_9_ | ~n383 | n518;
assign n658 = n657 & (n281 | ~n496 | n560);
assign n659 = (n358 | n98) & (n346 | n303);
assign n660 = (n345 & (~i_6_ | n351)) | (i_6_ & n351);
assign n661 = (~i_1_ & n329) | (n311 & (i_1_ | n329));
assign n662 = n660 & n661 & (~i_12_ | n357);
assign n663 = (n378 | n456) & (n455 | n451);
assign n664 = (n555 | n568) & (n62 | ~n245);
assign n665 = (n388 | n555) & (n200 | ~n245);
assign n666 = (n388 | n553) & (n200 | ~n241);
assign n667 = (n553 | n568) & (n62 | ~n241);
assign n668 = (n288 | n535) & (~n166 | n190);
assign n669 = (n116 | n449) & (~n101 | n113);
assign n670 = i_10_ & (~i_7_ | (i_3_ & ~i_8_));
assign n671 = ~i_8_ | n56;
assign n672 = n741 & (~i_2_ | n303 | ~n406);
assign n673 = (i_3_ & n555) | (~n245 & (~i_3_ | n555));
assign n674 = (~i_7_ | n388) & (i_0_ | ~n67);
assign n675 = ~n383 | i_8_ | n53;
assign n676 = n675 & (n401 | n366);
assign n677 = n157 | ~i_8_ | n113;
assign n678 = n677 & (~n348 | n399);
assign n679 = n346 | i_6_ | n398;
assign n680 = n679 & (n390 | n364);
assign n681 = (~n243 | n525) & (n157 | n269);
assign n682 = n680 & n681 & (n56 | ~n573);
assign n683 = (i_7_ | n389) & (i_0_ | n397);
assign n684 = (~i_2_ | n571) & (~i_1_ | n570);
assign n685 = (~i_2_ | n569) & (~i_1_ | ~n462);
assign n686 = (n364 | n439) & (n105 | n537);
assign n687 = n288 | i_2_ | n106;
assign n688 = (n451 | n270) & (n364 | n453);
assign n689 = n211 | i_10_ | n105;
assign n690 = n689 & (~i_9_ | n536 | n564);
assign n691 = ~n381 & n690 & (~n365 | n380);
assign n692 = i_3_ | i_13_ | n293;
assign n693 = n735 & (~i_6_ | ~i_12_ | n529);
assign n694 = n285 & n692 & (~i_3_ | n693);
assign n695 = (~i_5_ & n377) | (n373 & (i_5_ | n377));
assign n696 = n695 & ~n738 & (~i_1_ | n526);
assign n697 = n564 | i_8_ | ~n458;
assign n698 = n697 & (n213 | n256 | n336);
assign n699 = n400 | ~i_10_ | n115;
assign n700 = n567 | n199 | n120;
assign n701 = n700 & (n454 | n109);
assign n702 = ~n319 | n196 | n290;
assign n703 = ~n466 & (n157 | (n668 & n669));
assign n704 = (n444 | n53) & (n217 | n565);
assign n705 = ~n467 & ~n468 & (n138 | n441);
assign n706 = (~n348 | n434) & (~n250 | n432);
assign n707 = (n538 | n71) & (n566 | n224);
assign n708 = n445 | i_5_ | n512 | n404;
assign n709 = n708 & ~n745 & (i_5_ | n431);
assign n710 = (n589 | n290) & (n202 | n177);
assign n711 = ~n480 & n710 & (n62 | n354);
assign n712 = (n185 | n335) & (n210 | n354);
assign n713 = ~n220 | ~i_5_ | i_9_;
assign n714 = n713 & n712 & (i_0_ | i_5_);
assign n715 = (n202 | n567) & (n64 | n355);
assign n716 = i_10_ | n332;
assign n717 = (i_2_ | n283) & (i_0_ | n481);
assign n718 = i_6_ | n60;
assign n719 = ~i_12_ & n718 & (i_5_ | n59);
assign n720 = n228 | ~i_3_ | i_7_;
assign n721 = n720 & (i_7_ | n408);
assign n722 = n721 & (n546 | (~i_2_ & i_7_));
assign n723 = (~i_7_ | n587) & (~i_2_ | n547);
assign n724 = ~n497 & (n226 | (n398 & n404));
assign n725 = ~i_0_ | n511;
assign n726 = n495 | n400;
assign n727 = ~n435 | ~i_3_ | n270;
assign n728 = ~n365 | ~i_8_ | ~n348;
assign n729 = ~i_5_ | n59 | ~n512 | n548;
assign n730 = ~n243 | i_7_ | n50;
assign n731 = i_7_ & (n573 | n65);
assign n732 = i_7_ & (~n643 | (~i_12_ & ~n161));
assign n733 = i_12_ | n514;
assign n734 = n560 | i_8_ | ~n167;
assign n735 = n527 | i_6_ | ~i_11_;
assign n736 = ~i_10_ & (~n572 | (n73 & n166));
assign n737 = i_2_ & i_12_ & (~n303 | ~n398);
assign n738 = ~i_1_ & (~n688 | (n166 & ~n537));
assign n739 = ~i_0_ & ~i_4_ & (n447 | n448);
assign n740 = i_0_ & (~n691 | ~n694 | ~n696);
assign n741 = i_2_ | n98 | n120;
assign n742 = i_4_ & (~n678 | (~n70 & ~n71));
assign n743 = ~i_4_ & (~n676 | (~n408 & ~n489));
assign n744 = ~n682 | n403 | n513 | n743 | ~n683 | n742;
assign n745 = i_5_ & n744;
assign n746 = n399 | ~i_4_ | ~i_5_;
assign n747 = (i_6_ & n362) | (~n167 & (~i_6_ | n362));
assign n748 = (~i_6_ & n490) | (n366 & (i_6_ | n490));
assign n749 = i_2_ & i_7_;
assign n750 = n417 & n533 & i_3_;
assign n751 = i_6_ & n574 & n433;
endmodule

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// Benchmark "TOP" written by ABC on Mon Feb 4 17:25:42 2019
module apex4 (
i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_,
o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_,
o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_ );
input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_;
output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_,
o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_;
wire n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74,
n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88,
n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101,
n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113,
n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125,
n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137,
n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149,
n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161,
n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173,
n174, n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197,
n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, n209,
n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221,
n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233,
n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244, n245,
n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269,
n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, n281,
n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305,
n306, n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317,
n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, n329,
n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, n341,
n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353,
n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, n365,
n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376, n377,
n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, n388, n389,
n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, n401,
n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413,
n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425,
n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449,
n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, n461,
n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, n473,
n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485,
n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, n497,
n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508, n509,
n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520, n521,
n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545,
n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, n581,
n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593,
n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605,
n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617,
n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629,
n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640, n641,
n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653,
n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677,
n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713,
n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725,
n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737,
n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749;
assign o_0_ = 1'b0;
assign o_1_ = ~n134;
assign o_2_ = ~n492;
assign o_3_ = ~n129;
assign o_4_ = ~n128;
assign o_5_ = ~n119;
assign o_6_ = ~n110;
assign o_7_ = ~n101;
assign o_8_ = ~n313;
assign o_9_ = ~n100;
assign o_10_ = ~n526;
assign o_11_ = ~n91;
assign o_12_ = ~n87;
assign o_13_ = ~n80;
assign o_14_ = ~n72;
assign o_15_ = ~n64;
assign o_16_ = ~n63;
assign o_17_ = ~n61;
assign o_18_ = ~n53;
assign n47 = n440 | n512;
assign n48 = n539 | n454;
assign n49 = n425 | n540;
assign n50 = n305 | n557;
assign n51 = n643 & n644 & n409 & n616 & n645 & n646 & n642 & n647;
assign n52 = n65 & (n515 | n514);
assign n53 = n47 & n48 & n49 & n50 & n51 & n52;
assign n54 = n641 & n501 & n624 & n620 & n586;
assign n55 = n314 | n591;
assign n56 = n528 | n208;
assign n57 = n425 | n558;
assign n58 = n236 | n576;
assign n59 = n545 | ~i_6_ | n531;
assign n60 = n49 & n742;
assign n61 = n48 & n54 & n55 & n56 & n57 & n58 & n59 & n60;
assign n62 = n651 & n652 & n653 & n654 & n650 & n259 & n604 & n655;
assign n63 = n54 & n62 & n50 & n47;
assign n64 = n51 & n62 & n58 & n56;
assign n65 = n190 | n543 | n514;
assign n66 = n229 | n548;
assign n67 = n443 | ~i_0_ | n419;
assign n68 = n190 | n562;
assign n69 = n656 & n247 & n657 & n621 & n658 & n599 & n659;
assign n70 = n437 & n456 & n513 & n660 & n661 & n516 & n662 & n663;
assign n71 = n504 & n505 & n506 & n507 & n508 & n509 & n510 & n511;
assign n72 = n65 & n66 & n67 & n68 & n69 & n70 & n71;
assign n73 = n664 & n597 & n556 & n264 & n358 & n391 & n434 & ~n522;
assign n74 = n360 & n517 & n399 & n518 & n519 & n520 & n521;
assign n75 = n515 | n245;
assign n76 = n440 | n558;
assign n77 = ~i_0_ | n190 | n250 | n252;
assign n78 = n430 | n419;
assign n79 = ~n332 | n345;
assign n80 = n73 & n74 & n75 & n70 & n76 & n77 & n78 & n79;
assign n81 = n634 & n596 & n350 & n468 & n130 & n665 & n666 & n667;
assign n82 = n440 | n144;
assign n83 = i_3_ | n373 | n419;
assign n84 = n190 | n575;
assign n85 = n342 | n559;
assign n86 = n182 | n575;
assign n87 = n74 & n81 & n82 & n69 & n83 & n84 & n85 & n86;
assign n88 = n560 | n575;
assign n89 = ~i_3_ | i_5_ | n440 | ~n461;
assign n90 = n345 | ~i_0_ | n250;
assign n91 = n88 & n89 & n59 & n90 & n71 & n73 & n81;
assign n92 = n570 & n193 & n202 & n199 & n588 & n589;
assign n93 = n178 & n184 & n183 & n185 & n186 & n187 & n188 & n189;
assign n94 = n141 & n155 & n160 & n164 & n172 & n122 & n173 & n174;
assign n95 = n221 & n222 & (n223 | n224);
assign n96 = n213 & n214 & n215 & n216 & n217 & n218 & n219 & n220;
assign n97 = n210 & n206 & n583 & n212 & n584 & n585 & n586 & n587;
assign n98 = n582 & n580 & ~n255 & n123 & n238 & n249 & ~n254;
assign n99 = n660 & n685 & n615 & n686 & n687 & n325 & n253 & n684;
assign n100 = n92 & n93 & n94 & n95 & n96 & n97 & n98 & n99;
assign n101 = n102 & n348 & n349 & n347 & n350 & n351 & n352 & n353;
assign n102 = n325 & n326 & n152 & n327 & n328 & n329 & n330 & n331;
assign n103 = n371 & (i_5_ | n372);
assign n104 = n369 & (n190 | n223 | n370);
assign n105 = n630 & n366 & n368 & n149 & n216 & n631;
assign n106 = n151 & n358 & n359 & n360 & n361 & n362 & n363 & n364;
assign n107 = n580 & n379 & n210 & n267 & n285 & ~n377;
assign n108 = n90 & n417 & n712 & n148 & n568 & n713;
assign n109 = n646 & n66 & n75 & n86 & n374 & ~n376;
assign n110 = n102 & n103 & n104 & n105 & n106 & n107 & n108 & n109;
assign n111 = n414 & (n415 | n416);
assign n112 = n281 & n413 & (n224 | ~n332);
assign n113 = n407 & n79 & n408 & n409 & n49 & n410 & n411 & n412;
assign n114 = n399 & n400 & n401 & n402 & n403 & n404 & n405 & n406;
assign n115 = n391 & n392 & n393 & n394 & n395 & n396 & n397 & n398;
assign n116 = n349 & n424 & n420 & n431 & n94 & n307;
assign n117 = n638 & n656 & n713 & n694 & n57 & n651;
assign n118 = n427 & n428 & n429 & n614 & n86 & n696;
assign n119 = n111 & n112 & n113 & n114 & n115 & n116 & n117 & n118;
assign n120 = n262 & n266 & n267 & n268 & n269 & n270 & n271 & n272;
assign n121 = n315 & n202 & n613 & n614;
assign n122 = n168 & n169 & (n170 | n171);
assign n123 = n88 & n231 & (n232 | n233);
assign n124 = n240 | n415 | i_0_ | ~i_2_;
assign n125 = n443 | n190 | n444;
assign n126 = n500 & n719 & n720;
assign n127 = n435 & n457 & n442 & n437 & n386 & n111 & n348 & n106;
assign n128 = n120 & n121 & n122 & n123 & n124 & n125 & n126 & n127;
assign n129 = n447 & n456 & n455 & n457 & n115 & n347 & n458 & n459;
assign n130 = n382 & n496 & (n145 | n335);
assign n131 = n640 & n494 & n495 & n505 & n504 & n619;
assign n132 = n661 & n657 & n497;
assign n133 = n603 & n48 & n68 & n720 & n279 & n187 & n602 & n741;
assign n134 = ~n499 & n97 & n112 & n130 & n131 & n132 & n133 & ~n498;
assign n135 = n339 | n542;
assign n136 = n440 | n416;
assign n137 = n166 | n541;
assign n138 = n236 | n538;
assign n139 = (n440 | n237) & (n305 | n224);
assign n140 = n679 & (n301 | n226 | n515);
assign n141 = n135 & n136 & n137 & n138 & n139 & n140;
assign n142 = n301 | n354 | n474;
assign n143 = n166 | n341;
assign n144 = n430 | n158;
assign n145 = i_6_ | i_7_;
assign n146 = n142 & n143 & (n144 | n145);
assign n147 = n422 | n467;
assign n148 = n170 | n544;
assign n149 = n342 | n367;
assign n150 = n440 | n436;
assign n151 = n166 | n365;
assign n152 = ~i_6_ | ~i_8_ | n453;
assign n153 = n422 | n546;
assign n154 = n146 & (n440 | n232 | n430);
assign n155 = n147 & n148 & n149 & n150 & n151 & n152 & n153 & n154;
assign n156 = n425 | n448;
assign n157 = n229 | n252 | n226;
assign n158 = i_5_ | n533;
assign n159 = n182 | ~n332;
assign n160 = n156 & n157 & (n158 | n159);
assign n161 = n529 | n548;
assign n162 = n425 | n546;
assign n163 = (n440 | n534) & (n423 | n454);
assign n164 = n161 & n162 & n163;
assign n165 = n182 | n430;
assign n166 = i_5_ | n240;
assign n167 = n165 | n166;
assign n168 = n240 | n223 | n208;
assign n169 = n342 | n337;
assign n170 = ~i_5_ | n533;
assign n171 = n425 | n430;
assign n172 = n553 & n554 & n167 & n286 & n555 & n556;
assign n173 = n683 & n477 & (n425 | n195);
assign n174 = n633 & n482 & n637 & n609 & n681 & n682 & n621 & n680;
assign n175 = n454 | n463;
assign n176 = n236 | n209;
assign n177 = (n166 | n559) & (n158 | n341);
assign n178 = n175 & n176 & n177;
assign n179 = n560 | n441;
assign n180 = n531 | n224;
assign n181 = n166 | n305;
assign n182 = ~i_6_ | n529;
assign n183 = n179 & n180 & (n181 | n182);
assign n184 = n295 & n294 & n563;
assign n185 = n166 | n367;
assign n186 = n529 | n531 | n472;
assign n187 = n225 | n301 | ~n332;
assign n188 = n678 & (~i_8_ | n562);
assign n189 = n675 & n676 & n269 & n76 & n362 & n624 & n677 & n50;
assign n190 = i_7_ | i_8_;
assign n191 = ~i_6_ | n543;
assign n192 = ~i_0_ | ~n469;
assign n193 = n85 & (n190 | n191 | n192);
assign n194 = i_6_ | ~i_7_;
assign n195 = n166 | n223;
assign n196 = n194 | n195;
assign n197 = n416 | n454;
assign n198 = n232 | n223;
assign n199 = n197 & (n198 | n145);
assign n200 = n166 | n566;
assign n201 = n339 | n274;
assign n202 = n200 & n201 & (n182 | n144);
assign n203 = n166 | n337;
assign n204 = n425 | n209;
assign n205 = (n158 | n233) & (n198 | n454);
assign n206 = n203 & n204 & n205;
assign n207 = n145 | n170 | ~n461;
assign n208 = ~i_6_ | n229;
assign n209 = n241 | n545;
assign n210 = n207 & (n208 | n209);
assign n211 = n223 | n339;
assign n212 = n211 | n208;
assign n213 = n440 | n209;
assign n214 = n158 | n274;
assign n215 = n236 | n572;
assign n216 = n182 | n572;
assign n217 = n415 | n211;
assign n218 = n301 | n191 | n488;
assign n219 = n182 | n211;
assign n220 = (n166 | n573) & (n532 | n145);
assign n221 = n531 | n229 | n545;
assign n222 = n59 & (n232 | ~n332 | n574);
assign n223 = ~i_2_ | n321;
assign n224 = n425 | n339;
assign n225 = i_6_ | n487;
assign n226 = ~i_1_ | n443;
assign n227 = n226 | ~i_7_ | n225;
assign n228 = i_0_ | n191 | ~n469;
assign n229 = ~i_7_ | ~i_8_;
assign n230 = n228 | n229;
assign n231 = n422 | n195;
assign n232 = ~i_5_ | n240;
assign n233 = n182 | ~n461;
assign n234 = n190 | n515 | n488;
assign n235 = n342 | n372;
assign n236 = i_6_ | n529;
assign n237 = n531 | n158;
assign n238 = n234 & n235 & (n236 | n237);
assign n239 = n321 | n577;
assign n240 = ~i_3_ | i_4_;
assign n241 = ~i_2_ | n373;
assign n242 = ~i_6_ | i_8_;
assign n243 = n239 & (n240 | n241 | n242);
assign n244 = i_6_ | n323;
assign n245 = n190 | ~n461;
assign n246 = n244 | n245;
assign n247 = n339 | n573;
assign n248 = i_3_ | i_4_ | i_6_;
assign n249 = n247 & (n229 | n248 | ~n332);
assign n250 = i_2_ | ~i_3_;
assign n251 = n250 | ~i_0_ | n225;
assign n252 = i_6_ | ~i_4_ | i_5_;
assign n253 = ~i_1_ | ~i_7_ | n250 | n252;
assign n254 = i_8_ & (~n251 | (~n430 & ~n472));
assign n255 = ~i_5_ & (~n591 | (~n422 & ~n561));
assign n256 = n425 | n436;
assign n257 = n378 | ~n461;
assign n258 = n170 | n367;
assign n259 = n208 | n558;
assign n260 = n327 & (n166 | n229 | ~n461);
assign n261 = n301 | n144;
assign n262 = n256 & n257 & n258 & n259 & n260 & n261;
assign n263 = n415 | n538;
assign n264 = n181 | n208;
assign n265 = n578 & (n301 | n241 | n444);
assign n266 = n78 & n263 & n264 & n265;
assign n267 = n592 & n593;
assign n268 = n238 & n700 & (n537 | n191);
assign n269 = n339 | n440 | ~n461;
assign n270 = n342 | n365;
assign n271 = n232 | n241 | n242;
assign n272 = n669 & n699 & n656 & n410;
assign n273 = ~n415 & (~n237 | (~n305 & ~n533));
assign n274 = n208 | ~n332;
assign n275 = n274 | n170;
assign n276 = n444 | n565;
assign n277 = n365 | ~i_4_ | i_5_;
assign n278 = n276 & n277 & (n225 | n245);
assign n279 = n232 | n372;
assign n280 = n529 | n571;
assign n281 = n342 | n159;
assign n282 = n182 | n539;
assign n283 = n691 & (n527 | n544);
assign n284 = n689 & n466 & n690 & n658 & n452 & n648 & n138 & n402;
assign n285 = n279 & n280 & n281 & n282 & n183 & n146 & n283 & n284;
assign n286 = n545 | n274;
assign n287 = n158 | n542;
assign n288 = n532 | n425;
assign n289 = n425 | n453;
assign n290 = n170 | n302 | n430;
assign n291 = n182 | n423;
assign n292 = (n532 | n454) & (n528 | n145);
assign n293 = n286 & n136 & n287 & n288 & n289 & n290 & n291 & n292;
assign n294 = n208 | n546;
assign n295 = n440 | n493;
assign n296 = n236 | n564;
assign n297 = n158 | n591;
assign n298 = n688 & (n158 | n236 | ~n332);
assign n299 = n305 | n229 | n354;
assign n300 = n294 & n295 & n296 & n297 & n298 & n299;
assign n301 = ~i_7_ | i_8_;
assign n302 = i_6_ | ~i_8_;
assign n303 = n531 | n339;
assign n304 = (n301 | n228) & (n302 | n303);
assign n305 = i_2_ | n321;
assign n306 = i_3_ | i_5_;
assign n307 = n239 & (n305 | n236 | n306);
assign n308 = n602 & n603 & n604 & n519;
assign n309 = n702 & (~i_1_ | n182 | n342);
assign n310 = n351 & n285 & n120 & n300 & n304 & n293;
assign n311 = n673 & n84 & n640 & n675 & n701 & n67;
assign n312 = n76 & n404 & n219 & n636 & n649 & n79;
assign n313 = n308 & n95 & n307 & n309 & n160 & n310 & n311 & n312;
assign n314 = i_3_ | n487;
assign n315 = n159 | n314;
assign n316 = n165 | n232;
assign n317 = n440 | n423;
assign n318 = n190 | n248 | ~n332;
assign n319 = (n236 | n536) & (n415 | n575);
assign n320 = n317 & n318 & n319;
assign n321 = i_0_ | ~i_1_;
assign n322 = n191 | n301 | n321 | i_3_;
assign n323 = i_3_ | ~i_5_;
assign n324 = n208 | n223 | n323;
assign n325 = n537 | n252;
assign n326 = n415 | n467;
assign n327 = n342 | n573;
assign n328 = n706 & (i_0_ | n443 | n419);
assign n329 = i_3_ | n566;
assign n330 = n320 & n478 & n300 & n172 & n121 & n612 & n617;
assign n331 = n705 & n218 & n403 & n257 & n150 & n187 & n583 & n704;
assign n332 = ~i_2_ & ~n426;
assign n333 = ~n170 & (~n233 | (~n301 & n332));
assign n334 = ~n430 & (~n224 | (~n314 & ~n529));
assign n335 = n342 | n241;
assign n336 = n335 | n190;
assign n337 = ~n332 | n422;
assign n338 = n337 | n232;
assign n339 = i_5_ | n527;
assign n340 = n242 | n339 | ~n461;
assign n341 = n415 | ~n461;
assign n342 = ~i_5_ | n527;
assign n343 = n341 | n342;
assign n344 = n681 & n563 & n703;
assign n345 = n229 | n444;
assign n346 = i_1_ | ~n469;
assign n347 = n243 & n344 & (n345 | n346);
assign n348 = n621 & n622 & n623 & n624 & n496 & n625 & n626 & n627;
assign n349 = n340 & n343 & n58 & n620;
assign n350 = n618 & n405 & n619;
assign n351 = n605 & n178 & n606 & n607 & n278 & n596 & n601 & n608;
assign n352 = n582 & n193 & n266;
assign n353 = n399 & n258 & n695 & n708 & n506 & n186 & n654 & n707;
assign n354 = ~i_6_ | n487;
assign n355 = n301 | n354 | ~n461;
assign n356 = ~i_4_ | ~i_5_;
assign n357 = n356 | n165;
assign n358 = n182 | n448;
assign n359 = n241 | n224;
assign n360 = n232 | n182 | n241;
assign n361 = n166 | n159;
assign n362 = n170 | n341;
assign n363 = n47 & n501 & n147;
assign n364 = n408 & n396 & n676 & n197 & n710 & n388 & n711 & n709;
assign n365 = n430 | n208;
assign n366 = n365 | n232;
assign n367 = ~n332 | n425;
assign n368 = n367 | n158;
assign n369 = n531 | n208 | n547;
assign n370 = i_6_ | n547;
assign n371 = n534 | n449;
assign n372 = n425 | ~n461;
assign n373 = ~i_0_ | ~i_1_;
assign n374 = n373 | n301 | n339;
assign n375 = (i_1_ & (~i_5_ | ~n426)) | (i_5_ & ~n426);
assign n376 = ~n454 & ~i_4_ & n375;
assign n377 = ~n195 & (~n425 | ~n449);
assign n378 = n232 | n236;
assign n379 = ~n332 | n378;
assign n380 = n241 | n557;
assign n381 = n423 | n208;
assign n382 = n166 | n590;
assign n383 = n232 | n542;
assign n384 = (n170 | n541) & (n422 | n453);
assign n385 = n716 & (~i_1_ | i_2_ | n577);
assign n386 = n380 & n381 & n382 & n383 & n384 & n385;
assign n387 = n422 | n549;
assign n388 = n355 & n357 & n628 & n629;
assign n389 = n529 | n515;
assign n390 = n387 & n388 & (n389 | n346);
assign n391 = n236 | n549;
assign n392 = n170 | n590;
assign n393 = n415 | n441;
assign n394 = n182 | n564;
assign n395 = n425 | n538;
assign n396 = n208 | n441;
assign n397 = n425 | n441;
assign n398 = n390 & n320 & n386 & n308 & n278 & n718;
assign n399 = n166 | n430 | n454;
assign n400 = n170 | n159;
assign n401 = n314 | n559;
assign n402 = n425 | n564;
assign n403 = n144 | n454;
assign n404 = n314 | n274;
assign n405 = n538 | n208;
assign n406 = n326 & n607 & n282 & n697 & n714 & n715;
assign n407 = n474 | n438;
assign n408 = n314 | n449 | ~n461;
assign n409 = n449 | n564;
assign n410 = n182 | n467;
assign n411 = n708 & n625 & (n537 | n248);
assign n412 = n613 & n698 & n710;
assign n413 = n594 & n693 & n90;
assign n414 = n301 | n430 | n252;
assign n415 = i_6_ | n301;
assign n416 = n305 | n170;
assign n417 = n415 | n453;
assign n418 = n425 | n576;
assign n419 = n225 | n229;
assign n420 = n417 & n418 & (n192 | n419);
assign n421 = n574 | ~n332 | n545;
assign n422 = ~i_6_ | n301;
assign n423 = n166 | n241;
assign n424 = n421 & (n422 | n423);
assign n425 = ~i_6_ | n190;
assign n426 = ~i_0_ | i_1_;
assign n427 = n425 | n240 | n426;
assign n428 = n354 | i_7_ | n192;
assign n429 = n229 | n241 | n244;
assign n430 = i_2_ | n373;
assign n431 = n224 | n430;
assign n432 = ~n454 & ((~n223 & ~n306) | ~n534);
assign n433 = n372 | n158;
assign n434 = n415 | n546;
assign n435 = n434 & (n229 | ~n332 | n370);
assign n436 = n223 | n545;
assign n437 = n401 & (n236 | n436);
assign n438 = n229 | n515;
assign n439 = ~i_0_ | ~i_2_;
assign n440 = i_6_ | n190;
assign n441 = n223 | n170;
assign n442 = (n438 | n439) & (n440 | n441);
assign n443 = ~i_2_ | i_3_;
assign n444 = i_6_ | n356;
assign n445 = n208 | n493;
assign n446 = (n422 | n575) & (n529 | n441);
assign n447 = n445 & n361 & n446;
assign n448 = n430 | n545;
assign n449 = ~i_6_ | ~i_7_;
assign n450 = n448 | n449;
assign n451 = n232 | n367;
assign n452 = n305 | n422 | n533;
assign n453 = n342 | n223;
assign n454 = i_6_ | n229;
assign n455 = n451 & n452 & (n453 | n454);
assign n456 = n636 & n450 & n622 & n579;
assign n457 = n635 & n634 & n633 & n632 & n553 & n552 & ~n432 & n433;
assign n458 = n601 & n249 & n617;
assign n459 = n294 & n297 & n701 & n721 & n206 & n199 & n722 & n155;
assign n460 = ~n252 & ~n529;
assign n461 = i_2_ & ~n426;
assign n462 = n461 & ((~n194 & ~n314) | n460);
assign n463 = n305 | n339;
assign n464 = n463 | n415;
assign n465 = n182 | n534;
assign n466 = n314 | n365;
assign n467 = n241 | n158;
assign n468 = n465 & n466 & (n236 | n467);
assign n469 = i_3_ & i_2_;
assign n470 = n469 & ((~n229 & ~n252) | ~n389);
assign n471 = ~n470 & (i_2_ | n306 | n440);
assign n472 = ~i_6_ | n527;
assign n473 = (n229 | n472) & (i_7_ | n370);
assign n474 = i_3_ | n426;
assign n475 = (n321 | n158) & (i_4_ | n474);
assign n476 = n639 & n638 & n637 & n464 & n148 & ~n462;
assign n477 = n550 & n551 & n552;
assign n478 = n291 & n322 & n324;
assign n479 = n732 & n734 & (~i_1_ | n471);
assign n480 = n554 & n701 & n731 & n730 & n396 & n161 & n688 & n727;
assign n481 = n468 & n420 & n476 & n96 & n477 & n478 & n479 & n480;
assign n482 = n440 | n540;
assign n483 = n482 & (n198 | n415);
assign n484 = n302 | n158;
assign n485 = n166 | n236;
assign n486 = n484 & n485 & (~i_5_ | n440);
assign n487 = i_4_ | ~i_5_;
assign n488 = i_3_ | ~i_0_ | i_2_;
assign n489 = (n487 | n488) & (n373 | n170);
assign n490 = n262 & n92 & n612 & n738 & n739 & n737;
assign n491 = n621 & n649 & n644 & n643 & n289 & n162 & n393 & n736;
assign n492 = n483 & n447 & n481 & n114 & n103 & n442 & n490 & n491;
assign n493 = n241 | n314;
assign n494 = n493 | n422;
assign n495 = n209 | n182;
assign n496 = n425 | n493;
assign n497 = n356 | n182 | n346;
assign n498 = ~n170 & ~n449 & (~n430 | n461);
assign n499 = n332 & (~n378 | ~n485 | ~n740);
assign n500 = n545 | n145 | ~n332;
assign n501 = n531 | n557;
assign n502 = (n342 | n171) & (n449 | n335);
assign n503 = n500 & n501 & n502;
assign n504 = n166 | n274;
assign n505 = n158 | n566;
assign n506 = n422 | n576;
assign n507 = n719 & (n190 | n354 | n561);
assign n508 = n430 | n345;
assign n509 = n476 & n455 & n503 & n293 & n570 & n424;
assign n510 = n611 & n383 & n203 & n213 & n682 & n361;
assign n511 = n317 & n176 & n175 & n643 & n641 & n318;
assign n512 = n166 | n531;
assign n513 = n270 & (n425 | n512);
assign n514 = i_3_ | n530;
assign n515 = i_6_ | n543;
assign n516 = n514 | n515;
assign n517 = n145 | n575;
assign n518 = n166 | n233;
assign n519 = n170 | n566;
assign n520 = n669 & n387 & n217 & n693 & n200;
assign n521 = n404 & n692 & n359 & n744 & n650 & n642 & n483 & n105;
assign n522 = ~n232 & (~n544 | ~n591);
assign n523 = n390 & n104 & n113 & n93 & n141 & n304;
assign n524 = n745 & n746 & n747 & n77 & n381 & n605;
assign n525 = n689 & n271 & n705 & n360 & n47 & n618;
assign n526 = n481 & n435 & n131 & n513 & n503 & n523 & n524 & n525;
assign n527 = i_3_ | ~i_4_;
assign n528 = n305 | n342;
assign n529 = i_7_ | ~i_8_;
assign n530 = i_1_ | i_0_;
assign n531 = ~i_2_ | n530;
assign n532 = n342 | n531;
assign n533 = ~i_3_ | ~i_4_;
assign n534 = n170 | n241;
assign n535 = i_0_ | n443 | n225;
assign n536 = n339 | n430;
assign n537 = n223 | n229;
assign n538 = n531 | n170;
assign n539 = n305 | n158;
assign n540 = n305 | n314;
assign n541 = n422 | n430;
assign n542 = n208 | ~n461;
assign n543 = i_4_ | i_5_;
assign n544 = n415 | n430;
assign n545 = i_4_ | n306;
assign n546 = n305 | n545;
assign n547 = ~i_3_ | ~i_5_;
assign n548 = n430 | n370;
assign n549 = n223 | n158;
assign n550 = n232 | n341;
assign n551 = n170 | n372;
assign n552 = n208 | n540;
assign n553 = n182 | n549;
assign n554 = n208 | n463;
assign n555 = n540 | n454;
assign n556 = n425 | n467;
assign n557 = n422 | n339;
assign n558 = n531 | n314;
assign n559 = ~n332 | n454;
assign n560 = ~i_6_ | i_7_;
assign n561 = i_1_ | n443;
assign n562 = n426 | ~i_3_ | n252;
assign n563 = n236 | n211;
assign n564 = n305 | n232;
assign n565 = n529 | n474;
assign n566 = n422 | ~n461;
assign n567 = n236 | n463;
assign n568 = n536 | n560;
assign n569 = n339 | n341;
assign n570 = n567 & n196 & n568 & n569;
assign n571 = n223 | n314;
assign n572 = n241 | n339;
assign n573 = ~n332 | n415;
assign n574 = i_6_ | i_8_;
assign n575 = ~n461 | n545;
assign n576 = n232 | n531;
assign n577 = i_3_ | n190 | n444;
assign n578 = n49 & n394 & n421 & n387 & n445;
assign n579 = n440 | n564;
assign n580 = n246 & n578 & n243 & n410 & n579 & n418;
assign n581 = ~n461 | n485;
assign n582 = n227 & n230 & n451 & n581;
assign n583 = n422 | n441;
assign n584 = n422 | n571;
assign n585 = n182 | n546;
assign n586 = n425 | n416;
assign n587 = n182 | n436;
assign n588 = n672 & n673 & n606 & n674;
assign n589 = n668 & n626 & n669 & n670 & n671 & n287 & n645 & n296;
assign n590 = ~n332 | n440;
assign n591 = n182 | n531;
assign n592 = n407 & n135 & n692 & n392 & n137 & n693 & n694 & n55;
assign n593 = n695 & n696 & n685 & n687 & n585 & n697 & n698 & n681;
assign n594 = n339 | n559;
assign n595 = n181 | n425;
assign n596 = n418 & n393 & n594 & n595 & n550;
assign n597 = ~n332 | n557;
assign n598 = n425 | n144;
assign n599 = n440 | n571;
assign n600 = n314 | n541;
assign n601 = n600 & n599 & n598 & n597 & n518 & ~n273 & n275;
assign n602 = n182 | n493;
assign n603 = n232 | n274;
assign n604 = n422 | n558;
assign n605 = n170 | n236 | ~n461;
assign n606 = n430 | n485;
assign n607 = n208 | n416;
assign n608 = n551 & n686 & n639 & n637 & n671 & n569 & n57 & n653;
assign n609 = n339 | n159;
assign n610 = n422 | n237;
assign n611 = n237 | n454;
assign n612 = n609 & n395 & n316 & n610 & n611 & n391;
assign n613 = n236 | n416;
assign n614 = n539 | n242;
assign n615 = n181 | n302;
assign n616 = n454 | n564;
assign n617 = n615 & n256 & n269 & n234 & n214 & n270 & n50 & n616;
assign n618 = n529 | n535;
assign n619 = n223 | n557;
assign n620 = n532 | n208;
assign n621 = n422 | n538;
assign n622 = n182 | n571;
assign n623 = n181 | n440;
assign n624 = n182 | n463;
assign n625 = n182 | n195;
assign n626 = n565 | n191;
assign n627 = n397 & n338 & n336 & ~n334 & n82 & ~n333;
assign n628 = n425 | n571;
assign n629 = n342 | n274;
assign n630 = n236 | n342 | ~n461;
assign n631 = n534 | n415;
assign n632 = n232 | n171;
assign n633 = n236 | n539;
assign n634 = n342 | n233;
assign n635 = n672 & (n252 | ~n332 | n529);
assign n636 = n546 | n454;
assign n637 = n232 | n159;
assign n638 = n182 | n416;
assign n639 = n430 | n557;
assign n640 = n422 | n540;
assign n641 = i_2_ | n530;
assign n642 = n402 & n623 & n641 & n394;
assign n643 = n425 | n237;
assign n644 = n237 | n208;
assign n645 = n415 | n564;
assign n646 = n415 | n576;
assign n647 = n138 & n263 & n694 & n610 & n501 & n677 & n297;
assign n648 = n440 | n576;
assign n649 = n440 | n303;
assign n650 = n59 & n57 & n648 & n649 & n587;
assign n651 = n339 | n591;
assign n652 = i_5_ | n236 | n514;
assign n653 = n528 | n422;
assign n654 = n303 | n194;
assign n655 = n742 & n55 & n180;
assign n656 = n181 | n454;
assign n657 = n236 | n448;
assign n658 = n198 | n182;
assign n659 = n214 & n235 & n671 & n58 & n652 & n137;
assign n660 = n528 | n425;
assign n661 = n440 | n572;
assign n662 = n725 & n632 & n581 & n231 & n400 & n699 & n584;
assign n663 = n147 & n143 & n644 & n410 & n296 & n201 & n362 & n743;
assign n664 = n651 & n445 & n628;
assign n665 = n670 & n713 & n668 & n633 & n598 & n600;
assign n666 = n180 & n257 & n151 & n49 & n694 & n742;
assign n667 = n403 & n219 & n555 & n392 & n371 & n629;
assign n668 = n415 | n448;
assign n669 = n208 | n549;
assign n670 = n454 | n441;
assign n671 = n440 | n467;
assign n672 = n440 | n195;
assign n673 = n422 | n209;
assign n674 = n236 | n453;
assign n675 = n198 | n425;
assign n676 = n236 | n493;
assign n677 = n440 | n538;
assign n678 = n301 | n561 | n444;
assign n679 = n208 | n303;
assign n680 = n263 & n610 & n56;
assign n681 = n208 | n467;
assign n682 = n539 | n449;
assign n683 = ~n461 | ~i_3_ | n454;
assign n684 = n658 & n288 & n623 & n653 & n631 & n630 & n595;
assign n685 = n301 | n423;
assign n686 = n301 | n535;
assign n687 = n536 | n229;
assign n688 = n208 | n575;
assign n689 = n422 | n531 | n356;
assign n690 = n241 | n378;
assign n691 = n301 | n241 | n472;
assign n692 = n538 | n454;
assign n693 = n314 | n544;
assign n694 = n440 | n539;
assign n695 = n190 | n548;
assign n696 = n192 | n389;
assign n697 = n208 | n448;
assign n698 = n236 | n335;
assign n699 = n342 | n590;
assign n700 = n153 & (n440 | n223 | n306);
assign n701 = n440 | n549;
assign n702 = n305 | ~i_7_ | n244;
assign n703 = n527 | n182 | n373;
assign n704 = n638 & n235 & n136 & n677 & n669 & n567 & n217;
assign n705 = n540 | n574;
assign n706 = n425 | n241 | n547;
assign n707 = n164 & (n321 | n415 | n543);
assign n708 = n181 | n301;
assign n709 = n674 & (~i_7_ | n223 | n248);
assign n710 = n342 | n541;
assign n711 = n158 | n337;
assign n712 = ~i_3_ | i_5_ | n305 | n415;
assign n713 = n422 | n198;
assign n714 = n712 & (n354 | ~n461 | n529);
assign n715 = n171 | n323;
assign n716 = i_7_ | n244 | ~n461;
assign n717 = n301 | n225 | n226;
assign n718 = n717 & (n419 | n346);
assign n719 = n182 | n453;
assign n720 = n529 | n225 | n488;
assign n721 = n679 & (n226 | n438);
assign n722 = (n449 | n195) & (n223 | n224);
assign n723 = (n527 | n194) & (n301 | n232);
assign n724 = (n529 | n444) & (n190 | n166);
assign n725 = n339 | n233;
assign n726 = n549 | n194;
assign n727 = n517 & n149 & n725 & n726;
assign n728 = i_8_ | n252 | n488;
assign n729 = n728 & (n240 | n373 | n415);
assign n730 = n729 & (i_3_ | n454 | ~n461);
assign n731 = n533 | n236 | ~n332;
assign n732 = (n475 | n425) & (n473 | n241);
assign n733 = (n194 | n512) & (n529 | n540);
assign n734 = n733 & (n430 | (n724 & n723));
assign n735 = ~i_0_ | ~i_2_ | ~i_7_ | n342;
assign n736 = n280 & n89 & n735 & n380 & n169 & n83;
assign n737 = (~n332 | n486) & (n232 | n591);
assign n738 = n489 | n190;
assign n739 = n373 | n208 | n547;
assign n740 = (n533 | n415) & (n422 | n232);
assign n741 = n383 & n295 & n675;
assign n742 = i_4_ | i_6_ | n514;
assign n743 = n215 & n204 & n690 & n162 & n726 & n258;
assign n744 = n184 & (n534 | n236);
assign n745 = ~i_2_ | ~i_5_ | n748 | n749;
assign n746 = i_3_ | n430 | n574;
assign n747 = n487 | n565;
assign n748 = i_1_ & (i_4_ | n229);
assign n749 = ~i_1_ & (~i_4_ | n208);
endmodule

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// Benchmark "TOP" written by ABC on Mon Feb 4 17:31:22 2019
module ex1010 (
i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_,
o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_ );
input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_;
output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_;
wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57,
n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135,
n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219,
n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231,
n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243,
n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267,
n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279,
n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291,
n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303,
n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327,
n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351,
n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363,
n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375,
n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387,
n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399,
n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411,
n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423,
n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471,
n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483,
n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495,
n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543,
n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603,
n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663,
n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675,
n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699,
n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759,
n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771,
n772, n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, n795,
n796, n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807,
n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819,
n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867,
n868, n869;
assign o_0_ = ~n418;
assign o_1_ = ~n31;
assign o_2_ = ~n403;
assign o_3_ = ~n378;
assign o_4_ = ~n349;
assign o_5_ = ~n30;
assign o_6_ = ~n270;
assign o_7_ = ~n216;
assign o_8_ = ~n170;
assign o_9_ = ~n109;
assign n30 = n155 & n50 & n301 & n302 & n303 & n304 & n305 & n306;
assign n31 = n97 & n404 & n151 & n405 & n406 & n407 & n408 & n409;
assign n32 = (n436 | n458) & (n219 | n479);
assign n33 = ~i_9_ | n429;
assign n34 = n423 | n446;
assign n35 = n32 & (n33 | n34);
assign n36 = (n222 | n481) & (n43 | n480);
assign n37 = ~i_9_ | n419;
assign n38 = n423 | n457;
assign n39 = n36 & (n37 | n38);
assign n40 = i_9_ | n440;
assign n41 = n420 | n441;
assign n42 = n419 | n450;
assign n43 = i_9_ | n421;
assign n44 = (n42 | n43) & (n40 | n41);
assign n45 = n219 | n103;
assign n46 = n439 | n290;
assign n47 = n565 & n320 & n566;
assign n48 = n563 & n564 & (n272 | n476);
assign n49 = n561 & n562 & n125 & n556 & n560 & n557;
assign n50 = n45 & n46 & n44 & n35 & n39 & n47 & n48 & n49;
assign n51 = n40 | n456;
assign n52 = n436 | n203;
assign n53 = ~i_9_ | n427;
assign n54 = n426 | n446;
assign n55 = n51 & n52 & (n53 | n54);
assign n56 = n37 | n262;
assign n57 = n272 | n487;
assign n58 = n319 & (n219 | n488);
assign n59 = n555 & n55 & (n91 | n489);
assign n60 = n53 | n92;
assign n61 = n219 | n485;
assign n62 = n33 | n486;
assign n63 = n388 & n554 & (n53 | n483);
assign n64 = n56 & n57 & n58 & n59 & n60 & n61 & n62 & n63;
assign n65 = n552 & (n37 | n490);
assign n66 = n436 | n491;
assign n67 = (n33 | n469) & (n96 | n43);
assign n68 = n219 | n339;
assign n69 = (n37 | n478) & (n439 | n494);
assign n70 = n553 & n328 & (n309 | n481);
assign n71 = n65 & n66 & n67 & n68 & n69 & n70;
assign n72 = n91 | n496;
assign n73 = n100 | n41;
assign n74 = (n309 | n463) & (n222 | n495);
assign n75 = (n222 | n463) & (n43 | n255);
assign n76 = (n422 | n462) & (n43 | n223);
assign n77 = n72 & n73 & n74 & n75 & n76;
assign n78 = n219 | n498;
assign n79 = n436 | n480;
assign n80 = (n436 | n447) & (n222 | n497);
assign n81 = (n86 | n475) & (n258 | n499);
assign n82 = (n309 | n480) & (n40 | n493);
assign n83 = n78 & n79 & n80 & n81 & n82;
assign n84 = (n443 | n86) & (n462 | n502);
assign n85 = n225 & n551 & (n258 | n500);
assign n86 = i_9_ | n460;
assign n87 = n433 | n466;
assign n88 = n84 & n85 & (n86 | n87);
assign n89 = (n222 | n203) & (n33 | n150);
assign n90 = n549 & n550 & (n219 | n199);
assign n91 = ~i_9_ | n466;
assign n92 = n435 | n442;
assign n93 = n89 & n90 & (n91 | n92);
assign n94 = n462 | n507;
assign n95 = n548 & n124 & (n100 | n506);
assign n96 = n441 | n442;
assign n97 = n94 & n95 & (n96 | n86);
assign n98 = (n219 | n92) & (n53 | n469);
assign n99 = n431 | n432;
assign n100 = i_9_ | n457;
assign n101 = n98 & (n99 | n100);
assign n102 = (n100 | n508) & (n33 | n489);
assign n103 = n423 | n460;
assign n104 = n102 & (n37 | n103);
assign n105 = (n86 | n465) & (n464 | n219);
assign n106 = n64 & n71 & n50 & n83 & n88 & n77;
assign n107 = n589 & n593 & n592 & n586 & n585 & n588;
assign n108 = n580 & n584 & n583 & n579 & n577 & n575;
assign n109 = n97 & n101 & n93 & n105 & n104 & n106 & n107 & n108;
assign n110 = n623 & (n100 | n514);
assign n111 = n37 | n507;
assign n112 = n86 | (n468 & n492);
assign n113 = n622 & (n462 | n498);
assign n114 = n620 & n621 & (n43 | n310);
assign n115 = n619 & n285 & n561 & n209 & n56 & n618 & n299 & n616;
assign n116 = n110 & n111 & n112 & n113 & n114 & n115;
assign n117 = (n37 | n471) & (n33 | n520);
assign n118 = n53 | n34;
assign n119 = (n91 | n523) & (n462 | n488);
assign n120 = n609 & n608 & (n100 | n475);
assign n121 = n312 & n613 & (n309 | n458);
assign n122 = n611 & n610 & (n447 | n43);
assign n123 = n117 & n118 & n119 & n120 & n121 & n122;
assign n124 = n462 | n505;
assign n125 = n43 | n468;
assign n126 = n73 & (n222 | n518);
assign n127 = (n86 | n525) & (n272 | n465);
assign n128 = n606 & (n309 | n524);
assign n129 = n603 & (n462 | n526);
assign n130 = n601 & n602 & (n439 | n498);
assign n131 = n605 & n604 & (n37 | n461);
assign n132 = n124 & n125 & n126 & n127 & n128 & n129 & n130 & n131;
assign n133 = (n272 | n495) & (n91 | n103);
assign n134 = n454 | n100;
assign n135 = n600 & (n309 | n484);
assign n136 = n462 | n477;
assign n137 = n598 & n599 & (n219 | n500);
assign n138 = n596 & n597 & (n222 | n42);
assign n139 = n133 & n134 & n135 & n136 & n137 & n138;
assign n140 = (n91 | n511) & (n272 | n528);
assign n141 = n594 & n595 & (n91 | n34);
assign n142 = n420 | n432;
assign n143 = n140 & n141 & (n86 | n142);
assign n144 = (n272 | n529) & (n258 | n503);
assign n145 = n86 | n530;
assign n146 = (n53 | n103) & (n424 | n462);
assign n147 = n144 & n145 & n146 & n61;
assign n148 = (n309 | n531) & (n436 | n456);
assign n149 = (n86 | n532) & (n100 | n472);
assign n150 = n421 | n442;
assign n151 = n148 & n149 & (n91 | n150);
assign n152 = (n40 & n436) | n533;
assign n153 = n380 & (n53 | n496);
assign n154 = n423 | n435;
assign n155 = n152 & n153 & (n91 | n154);
assign n156 = (n100 | n531) & (n91 | n534);
assign n157 = n426 | n466;
assign n158 = n156 & (n86 | n157);
assign n159 = (n33 | n505) & (n91 | n38);
assign n160 = n433 | n460;
assign n161 = n159 & (n33 | n160);
assign n162 = (n436 | n513) & (n33 | n92);
assign n163 = (n53 | n509) & (n222 | n512);
assign n164 = (n222 | n513) & (n37 | n467);
assign n165 = (n258 | n467) & (n43 | n501);
assign n166 = n626 & n625 & (n309 | n42);
assign n167 = n633 & n634 & n631 & n630 & n629 & n387 & n628 & n627;
assign n168 = n139 & n143 & n147 & n151 & n123 & n132 & n116 & n644;
assign n169 = n640 & n641 & n639 & n638 & n637 & n642 & n636 & n635;
assign n170 = n162 & n163 & n164 & n165 & n166 & n167 & n168 & n169;
assign n171 = (n37 | n92) & (n43 | n484);
assign n172 = n648 & n649 & (n458 | n86);
assign n173 = n647 & (n100 | n294);
assign n174 = n645 & n646 & (n219 | n540);
assign n175 = n171 & n172 & n173 & n174;
assign n176 = n33 | n477;
assign n177 = n272 | n255;
assign n178 = (n91 | n538) & (n452 | n43);
assign n179 = n91 | n504;
assign n180 = (n100 | n492) & (n258 | n504);
assign n181 = n559 & (n53 | n290);
assign n182 = n176 & n177 & n178 & n179 & n180 & n181;
assign n183 = n428 | n100;
assign n184 = n219 | n34;
assign n185 = (n436 | n472) & (n43 | n474);
assign n186 = n40 | n542;
assign n187 = (n91 | n339) & (n445 | n219);
assign n188 = (n40 | n525) & (n219 | n505);
assign n189 = n183 & n184 & n185 & n186 & n187 & n188;
assign n190 = n436 | n525;
assign n191 = n86 | n512;
assign n192 = (n86 | n480) & (n436 | n544);
assign n193 = n53 | n486;
assign n194 = n309 | n543;
assign n195 = (n258 | n251) & (n222 | n294);
assign n196 = n190 & n191 & n192 & n193 & n194 & n195;
assign n197 = (n96 | n100) & (n272 | n532);
assign n198 = n350 & n351 & (n40 | n513);
assign n199 = n450 | n457;
assign n200 = n197 & n198 & (n53 | n199);
assign n201 = (n462 | n496) & (n37 | n522);
assign n202 = (n309 | n517) & (n439 | n539);
assign n203 = n423 | n432;
assign n204 = n201 & n202 & (n86 | n203);
assign n205 = (n222 | n142) & (n272 | n521);
assign n206 = (n439 | n496) & (n33 | n470);
assign n207 = n205 & n206;
assign n208 = (n86 | n519) & (n100 | n537);
assign n209 = n53 | n150;
assign n210 = n674 & n673 & (n272 | n514);
assign n211 = n566 & n563 & n234 & n605 & n672 & n671;
assign n212 = n64 & n139 & (n461 | n91);
assign n213 = n676 & n675 & (n53 | n539);
assign n214 = n196 & n200 & n204 & n207 & n182 & n189 & n175;
assign n215 = n670 & n227 & n668 & n667 & n663 & n662 & n666 & n661;
assign n216 = n208 & n209 & n210 & n211 & n212 & n213 & n214 & n215;
assign n217 = n258 | n92;
assign n218 = (n309 | n542) & (n40 | n518);
assign n219 = ~i_9_ | n451;
assign n220 = n217 & n218 & (n219 | n38);
assign n221 = (n86 | n513) & (n462 | n545);
assign n222 = i_9_ | n425;
assign n223 = n442 | n466;
assign n224 = n221 & (n222 | n223);
assign n225 = n272 | n501;
assign n226 = n438 | n439;
assign n227 = n456 | n100;
assign n228 = n45 & n72 & (n43 | n525);
assign n229 = n686 & n685 & (n309 | n294);
assign n230 = n276 & n652 & n684 & n277;
assign n231 = n224 & n158 & n220 & n44 & n404 & n693 & n692 & n690;
assign n232 = n225 & n226 & n227 & n176 & n228 & n229 & n230 & n231;
assign n233 = n434 | n33;
assign n234 = n462 | n478;
assign n235 = n674 & (n40 | n536);
assign n236 = (n258 | n527) & (n222 | n510);
assign n237 = n33 | n523;
assign n238 = (n40 | n519) & (n37 | n259);
assign n239 = n439 | (n339 & n516);
assign n240 = n682 & n683 & (n100 | n541);
assign n241 = n233 & n234 & n235 & n236 & n237 & n238 & n239 & n240;
assign n242 = (n53 | n534) & (n462 | n54);
assign n243 = n96 | n272;
assign n244 = n681 & (n86 | n501);
assign n245 = n43 | n491;
assign n246 = n46 & n615 & (n91 | n479);
assign n247 = n679 & n680 & (n436 | n508);
assign n248 = n242 & n243 & n244 & n245 & n246 & n247;
assign n249 = n392 & (n40 | n492);
assign n250 = n678 & n677 & (n33 | n546);
assign n251 = n442 | n446;
assign n252 = n249 & n250 & (n53 | n251);
assign n253 = n272 | n536;
assign n254 = (n258 | n540) & (n86 | n515);
assign n255 = n431 | n441;
assign n256 = n253 & n254 & (n40 | n255);
assign n257 = (n91 | n520) & (n456 | n43);
assign n258 = ~i_9_ | n441;
assign n259 = n420 | n440;
assign n260 = n257 & (n258 | n259);
assign n261 = (n222 | n468) & (n258 | n339);
assign n262 = n420 | n449;
assign n263 = n261 & (n53 | n262);
assign n264 = (n37 | n290) & (n454 | n86);
assign n265 = (n219 | n511) & (n33 | n494);
assign n266 = n710 & n709 & (n309 | n506);
assign n267 = n713 & n712 & (n33 | n479);
assign n268 = n252 & n256 & n260 & n263 & n241 & n248 & n232 & n717;
assign n269 = n700 & n177 & n699 & n698 & n695 & n694 & n697 & n708;
assign n270 = n264 & n265 & n266 & n267 & n268 & n269;
assign n271 = (n100 | n535) & (n439 | n251);
assign n272 = i_9_ | n449;
assign n273 = n271 & (n272 | n42);
assign n274 = n91 | n546;
assign n275 = n439 | n546;
assign n276 = n436 | n476;
assign n277 = n219 | n150;
assign n278 = n253 & n719 & (n309 | n528);
assign n279 = n714 & (n91 | n526);
assign n280 = n321 & (n37 | n438);
assign n281 = n721 & n720 & (n86 | n41);
assign n282 = n274 & n275 & n276 & n277 & n278 & n279 & n280 & n281;
assign n283 = n219 | n478;
assign n284 = n428 | n436;
assign n285 = n100 | n521;
assign n286 = n665 & (n455 | n219);
assign n287 = n161 & n283 & n263 & n284 & n285 & n286;
assign n288 = (n40 | n497) & (n37 | n539);
assign n289 = n718 & (n219 | n486);
assign n290 = n453 | n460;
assign n291 = n288 & n289 & (n290 | n91);
assign n292 = n43 | (n476 & n506);
assign n293 = n686 & (n53 | n473);
assign n294 = n423 | n466;
assign n295 = n292 & n293 & (n272 | n294);
assign n296 = n219 | n469;
assign n297 = n100 | n533;
assign n298 = (n272 | n543) & (n462 | n486);
assign n299 = n455 | n53;
assign n300 = n296 & n297 & n298 & n299;
assign n301 = (n436 | n529) & (n219 | n547);
assign n302 = n749 & n748 & (n91 | n516);
assign n303 = n282 & n287 & n291 & n295 & n300 & n252 & n224 & n196;
assign n304 = n747 & n746 & n745 & n744 & n743 & n742 & n741 & n740;
assign n305 = n738 & n739 & n730 & n732 & n731 & n737 & n736 & n735;
assign n306 = n729 & n728 & n727 & n726 & n725 & n724 & n723 & n722;
assign n307 = n678 & (n219 | n490);
assign n308 = (n219 | n507) & (n459 | n462);
assign n309 = i_9_ | n446;
assign n310 = n419 | n433;
assign n311 = n307 & n308 & (n309 | n310);
assign n312 = n53 | n503;
assign n313 = n710 & n632 & (n309 | n501);
assign n314 = n753 & n590 & n190 & n78 & n79 & n51;
assign n315 = n469 | n91;
assign n316 = n669 & n649 & (n37 | n477);
assign n317 = n751 & n752 & (n439 | n92);
assign n318 = n311 & n312 & n313 & n314 & n315 & n234 & n316 & n317;
assign n319 = n447 | n100;
assign n320 = n219 | n477;
assign n321 = n219 | n154;
assign n322 = (n439 | n461) & (n100 | n530);
assign n323 = n222 | n472;
assign n324 = n654 & (n91 | n259);
assign n325 = (n222 | n537) & (n37 | n482);
assign n326 = n750 & n738 & (n272 | n484);
assign n327 = n319 & n320 & n321 & n322 & n323 & n324 & n325 & n326;
assign n328 = n436 | n492;
assign n329 = n53 | n489;
assign n330 = n452 | n100;
assign n331 = (n465 | n43) & (n272 | n512);
assign n332 = (n439 | n538) & (n37 | n527);
assign n333 = n462 | n538;
assign n334 = (n462 | n520) & (n424 | n219);
assign n335 = n258 | n490;
assign n336 = n328 & n329 & n330 & n331 & n332 & n333 & n334 & n335;
assign n337 = n53 | n520;
assign n338 = n43 | n203;
assign n339 = n420 | n425;
assign n340 = n337 & n338 & (n53 | n339);
assign n341 = n759 & n758 & (n462 | n527);
assign n342 = n602 & n757 & (n258 | n479);
assign n343 = n614 & n756 & (n43 | n497);
assign n344 = n755 & n754 & (n43 | n294);
assign n345 = n599 & n274 & n761 & n763 & n762 & n765 & n764 & n766;
assign n346 = n773 & n621 & n772 & n771;
assign n347 = n769 & n770 & n552 & n562 & n768 & n767;
assign n348 = n340 & n300 & n248 & n220 & n327 & n336 & n318 & n777;
assign n349 = n341 & n342 & n343 & n344 & n345 & n346 & n347 & n348;
assign n350 = n99 | n272;
assign n351 = n462 | n103;
assign n352 = n340 & (n459 | n219);
assign n353 = (n436 | n468) & (n33 | n467);
assign n354 = n94 & n582 & (n43 | n541);
assign n355 = n315 & n782 & (n258 | n511);
assign n356 = n739 & n780 & (n222 | n491);
assign n357 = n297 & n350 & n351 & n352 & n353 & n354 & n355 & n356;
assign n358 = (n436 | n532) & (n91 | n470);
assign n359 = n40 | n528;
assign n360 = (n43 | n515) & (n424 | n53);
assign n361 = n222 | n536;
assign n362 = n779 & n676 & (n100 | n142);
assign n363 = n778 & n760 & (n91 | n477);
assign n364 = n358 & n359 & n360 & n361 & n362 & n363;
assign n365 = (n222 | n524) & (n436 | n537);
assign n366 = n100 | n532;
assign n367 = (n91 | n498) & (n40 | n541);
assign n368 = (n33 | n154) & (n222 | n541);
assign n369 = n53 | n502;
assign n370 = n569 & (n436 | n157);
assign n371 = n365 & n366 & n367 & n368 & n369 & n370;
assign n372 = n801 & n800 & (n455 | n462);
assign n373 = n798 & n797 & (n272 | n530);
assign n374 = n364 & n371 & n357 & n804 & n88 & n55 & n116 & n803;
assign n375 = n795 & n794 & (n290 | n219);
assign n376 = n792 & n791 & (n100 | n493);
assign n377 = n788 & n789 & n787 & n786 & n785 & n217 & n784 & n783;
assign n378 = n372 & n373 & n374 & n375 & n376 & n377;
assign n379 = n462 | (n444 & n534);
assign n380 = n258 | n507;
assign n381 = n808 & (n53 | n471);
assign n382 = n809 & n810 & (n100 | n501);
assign n383 = n806 & n807 & (n53 | n461);
assign n384 = n759 & n805 & (n40 | n484);
assign n385 = n379 & n380 & n381 & n382 & n383 & n384;
assign n386 = n86 | n514;
assign n387 = n219 | n496;
assign n388 = n91 | n482;
assign n389 = n101 & (n272 | n519);
assign n390 = n40 | n514;
assign n391 = n37 | n154;
assign n392 = n430 | n100;
assign n393 = n596 & n597 & (n439 | n520);
assign n394 = n386 & n387 & n388 & n389 & n390 & n391 & n392 & n393;
assign n395 = (n222 | n447) & (n37 | n339);
assign n396 = n43 | (n454 & n510);
assign n397 = n811 & (n37 | n434);
assign n398 = n813 & (n462 | n546);
assign n399 = n812 & (n53 | n498);
assign n400 = n817 & n818 & (n439 | n103);
assign n401 = n816 & n815 & (n272 | n508);
assign n402 = n182 & n143 & n260 & n827 & n93 & n828 & n826 & n822;
assign n403 = n395 & n396 & n397 & n398 & n399 & n400 & n401 & n402;
assign n404 = n33 | n534;
assign n405 = (n37 | n502) & (n86 | n524);
assign n406 = (n100 | n518) & (n222 | n454);
assign n407 = n318 & n287 & n256 & n200 & n394 & n364 & n273;
assign n408 = n111 & n606 & n808 & n849 & n848 & n847 & n846 & n845;
assign n409 = n843 & n564 & n842 & n840 & n832 & n831 & n830 & n836;
assign n410 = (n86 | n533) & (n439 | n199);
assign n411 = n438 | n91;
assign n412 = n858 & n555 & (n43 | n533);
assign n413 = n721 & n857 & (n100 | n517);
assign n414 = n781 & n856 & (n462 | n499);
assign n415 = n855 & n854 & (n309 | n468);
assign n416 = n852 & n851 & (n33 | n444);
assign n417 = n132 & n83 & n175 & n868 & n867 & n869 & n866 & n862;
assign n418 = n410 & n411 & n412 & n413 & n414 & n415 & n416 & n417;
assign n419 = i_8_ | i_6_ | ~i_7_;
assign n420 = ~i_5_ | ~i_3_ | i_4_;
assign n421 = ~i_0_ | ~i_1_ | ~i_2_;
assign n422 = n420 | n421;
assign n423 = i_5_ | i_3_ | ~i_4_;
assign n424 = n421 | n423;
assign n425 = ~i_0_ | ~i_1_ | i_2_;
assign n426 = ~i_3_ | ~i_4_ | i_5_;
assign n427 = ~i_6_ | ~i_7_ | i_8_;
assign n428 = n426 | n427;
assign n429 = ~i_6_ | ~i_7_ | ~i_8_;
assign n430 = n420 | n429;
assign n431 = ~i_5_ | i_3_ | i_4_;
assign n432 = i_8_ | i_6_ | i_7_;
assign n433 = i_5_ | i_3_ | i_4_;
assign n434 = n425 | n433;
assign n435 = ~i_2_ | ~i_0_ | i_1_;
assign n436 = i_9_ | n435;
assign n437 = i_8_ | ~i_6_ | i_7_;
assign n438 = n433 | n435;
assign n439 = ~i_9_ | n437;
assign n440 = i_2_ | ~i_0_ | i_1_;
assign n441 = ~i_8_ | ~i_6_ | i_7_;
assign n442 = ~i_3_ | ~i_4_ | ~i_5_;
assign n443 = n419 | n442;
assign n444 = n431 | n440;
assign n445 = n433 | n440;
assign n446 = ~i_2_ | i_0_ | ~i_1_;
assign n447 = n419 | n420;
assign n448 = n431 | n437;
assign n449 = i_2_ | i_0_ | ~i_1_;
assign n450 = i_5_ | ~i_3_ | i_4_;
assign n451 = ~i_8_ | i_6_ | ~i_7_;
assign n452 = n450 | n451;
assign n453 = ~i_5_ | i_3_ | ~i_4_;
assign n454 = n429 | n453;
assign n455 = n423 | n449;
assign n456 = n423 | n441;
assign n457 = ~i_2_ | i_0_ | i_1_;
assign n458 = n429 | n431;
assign n459 = n433 | n457;
assign n460 = i_2_ | i_0_ | i_1_;
assign n461 = n450 | n460;
assign n462 = ~i_9_ | n432;
assign n463 = n423 | n429;
assign n464 = n431 | n460;
assign n465 = n427 | n433;
assign n466 = ~i_8_ | i_6_ | i_7_;
assign n467 = n421 | n450;
assign n468 = n423 | n437;
assign n469 = n421 | n431;
assign n470 = n425 | n426;
assign n471 = n425 | n453;
assign n472 = n433 | n441;
assign n473 = n426 | n440;
assign n474 = n453 | n466;
assign n475 = n423 | n451;
assign n476 = n432 | n450;
assign n477 = n426 | n457;
assign n478 = n420 | n460;
assign n479 = n420 | n435;
assign n480 = n432 | n453;
assign n481 = n426 | n429;
assign n482 = n421 | n426;
assign n483 = n421 | n453;
assign n484 = n427 | n453;
assign n485 = n425 | n431;
assign n486 = n431 | n446;
assign n487 = n420 | n427;
assign n488 = n431 | n449;
assign n489 = n453 | n457;
assign n490 = n425 | n450;
assign n491 = n420 | n466;
assign n492 = n429 | n450;
assign n493 = n441 | n453;
assign n494 = n442 | n449;
assign n495 = n429 | n433;
assign n496 = n426 | n460;
assign n497 = n431 | n466;
assign n498 = n431 | n435;
assign n499 = n449 | n453;
assign n500 = n440 | n450;
assign n501 = n442 | n451;
assign n502 = n431 | n457;
assign n503 = n423 | n440;
assign n504 = n426 | n449;
assign n505 = n435 | n453;
assign n506 = n420 | n437;
assign n507 = n442 | n460;
assign n508 = n419 | n423;
assign n509 = n423 | n425;
assign n510 = n437 | n453;
assign n511 = n420 | n457;
assign n512 = n441 | n450;
assign n513 = n419 | n426;
assign n514 = n432 | n433;
assign n515 = n433 | n451;
assign n516 = n435 | n450;
assign n517 = n426 | n451;
assign n518 = n433 | n437;
assign n519 = n451 | n453;
assign n520 = n421 | n433;
assign n521 = n437 | n442;
assign n522 = n426 | n435;
assign n523 = n442 | n457;
assign n524 = n429 | n442;
assign n525 = n427 | n442;
assign n526 = n420 | n446;
assign n527 = n440 | n442;
assign n528 = n431 | n451;
assign n529 = n426 | n441;
assign n530 = n420 | n451;
assign n531 = n437 | n450;
assign n532 = n427 | n431;
assign n533 = n427 | n450;
assign n534 = n433 | n446;
assign n535 = n419 | n453;
assign n536 = n432 | n442;
assign n537 = n423 | n427;
assign n538 = n446 | n453;
assign n539 = n449 | n450;
assign n540 = n433 | n449;
assign n541 = n426 | n432;
assign n542 = n419 | n431;
assign n543 = n426 | n437;
assign n544 = n450 | n466;
assign n545 = n446 | n450;
assign n546 = n440 | n453;
assign n547 = n425 | n442;
assign n548 = n462 | n259;
assign n549 = n439 | n504;
assign n550 = n91 | n503;
assign n551 = (n222 | n493) & (n424 | n33);
assign n552 = n53 | n479;
assign n553 = n436 | n493;
assign n554 = (n222 | n484) & (n33 | n339);
assign n555 = n456 | n86;
assign n556 = n315 & n338 & (n462 | n470);
assign n557 = n323 & n411 & (n33 | n471);
assign n558 = n40 | n157;
assign n559 = n91 | n473;
assign n560 = n558 & n559 & (n309 | n474);
assign n561 = n53 | n467;
assign n562 = n157 | n43;
assign n563 = n309 | n475;
assign n564 = n272 | n203;
assign n565 = n428 | n86;
assign n566 = n33 | n478;
assign n567 = (n219 | n467) & (n422 | n37);
assign n568 = (n37 | n424) & (n91 | n483);
assign n569 = n222 | n430;
assign n570 = n569 & (n428 | n222);
assign n571 = (n222 | n99) & (n258 | n485);
assign n572 = (n436 | n510) & (n434 | n439);
assign n573 = n99 | n436;
assign n574 = n33 | n509;
assign n575 = n572 & n573 & n571 & n233 & n570 & n574 & n568 & n567;
assign n576 = n96 | n40;
assign n577 = n576 & n226 & (n40 | n443);
assign n578 = (n33 | n445) & (n37 | n444);
assign n579 = n578 & (n439 | n54);
assign n580 = n309 | (n447 & n448);
assign n581 = n272 | n454;
assign n582 = n272 | n452;
assign n583 = n581 & n582 & (n272 | n493);
assign n584 = n443 | n272;
assign n585 = (n33 & n258) | n455;
assign n586 = (n33 | n511) & (n272 | n456);
assign n587 = n100 | n42;
assign n588 = n587 & n330 & (n100 | n203);
assign n589 = (n459 | n53) & (n100 | n458);
assign n590 = n463 | n86;
assign n591 = n290 | n462;
assign n592 = n590 & n591 & (n448 | n86);
assign n593 = n258 | n461;
assign n594 = n40 | n476;
assign n595 = n91 | n527;
assign n596 = n458 | n43;
assign n597 = n439 | n505;
assign n598 = n40 | n524;
assign n599 = n40 | n465;
assign n600 = n91 | n262;
assign n601 = n258 | n498;
assign n602 = n436 | n223;
assign n603 = n40 | n521;
assign n604 = (n258 | n477) & (n309 | n510);
assign n605 = n439 | n38;
assign n606 = n430 | n436;
assign n607 = n100 | n481;
assign n608 = n607 & (n100 | n484);
assign n609 = n100 | n463;
assign n610 = n549 & n584 & (n43 | n521);
assign n611 = n422 | n258;
assign n612 = n222 | n456;
assign n613 = n612 & (n439 | n485);
assign n614 = n219 | n520;
assign n615 = n436 | n518;
assign n616 = n614 & n615 & (n219 | n470);
assign n617 = n40 | n508;
assign n618 = n617 & (n219 | n503);
assign n619 = n86 | n472;
assign n620 = n222 | n443;
assign n621 = n462 | n339;
assign n622 = (n436 | n42) & (n439 | n522);
assign n623 = n219 | n259;
assign n624 = n40 | (n491 & n529);
assign n625 = n391 & n624 & (n436 | n514);
assign n626 = (n40 | n458) & (n33 | n500);
assign n627 = (n272 | n497) & (n258 | n262);
assign n628 = (n33 | n38) & (n272 | n87);
assign n629 = (n33 | n502) & (n100 | n468);
assign n630 = (n33 | n461) & (n91 | n478);
assign n631 = (n219 | n482) & (n86 | n294);
assign n632 = n462 | n467;
assign n633 = n632 & (n43 | n495);
assign n634 = n222 | n501;
assign n635 = (n436 | n443) & (n222 | n515);
assign n636 = (n37 | n479) & (n462 | n92);
assign n637 = (n40 | n517) & (n37 | n516);
assign n638 = n309 | (n491 & n497);
assign n639 = (n272 | n518) & (n37 | n499);
assign n640 = (n100 | n519) & (n219 | n489);
assign n641 = n100 | n87;
assign n642 = n91 | n251;
assign n643 = (n258 | n464) & (n86 | n535);
assign n644 = n158 & n161 & n155 & n71 & n35 & n643;
assign n645 = n436 | n454;
assign n646 = n43 | n87;
assign n647 = n272 | n310;
assign n648 = n86 | n541;
assign n649 = n439 | n502;
assign n650 = n43 | (n493 & n513);
assign n651 = (n258 | n520) & (n43 | n475);
assign n652 = n53 | n470;
assign n653 = n652 & (n439 | n470);
assign n654 = n222 | n532;
assign n655 = n654 & (n91 | n509);
assign n656 = (n434 | n91) & (n222 | n528);
assign n657 = (n436 | n536) & (n222 | n87);
assign n658 = n436 | n484;
assign n659 = n658 & (n462 | n516);
assign n660 = n462 | n154;
assign n661 = n659 & n660 & n657 & n656 & n655 & n653 & n651 & n650;
assign n662 = (n40 | n42) & (n436 | n465);
assign n663 = n40 | (n510 & n537);
assign n664 = (n37 | n445) & (n40 | n448);
assign n665 = n258 | n54;
assign n666 = n665 & n664 & (n309 | n536);
assign n667 = (n272 | n517) & (n37 | n34);
assign n668 = (n100 | n529) & (n53 | n523);
assign n669 = n462 | n199;
assign n670 = n669 & (n100 | n513);
assign n671 = (n37 | n503) & (n33 | n527);
assign n672 = (n219 | n538) & (n444 | n91);
assign n673 = (n272 | n524) & (n258 | n34);
assign n674 = n272 | n463;
assign n675 = (n219 | n526) & (n309 | n157);
assign n676 = n439 | n507;
assign n677 = (n439 | n479) & (n258 | n150);
assign n678 = n309 | n537;
assign n679 = n436 | n531;
assign n680 = n430 | n43;
assign n681 = n309 | n530;
assign n682 = n272 | n492;
assign n683 = n309 | n508;
assign n684 = n219 | n483;
assign n685 = (n33 | n545) & (n439 | n473);
assign n686 = n33 | n488;
assign n687 = n43 | n528;
assign n688 = n687 & (n33 | n490);
assign n689 = n53 | n494;
assign n690 = n689 & n688 & (n53 | n527);
assign n691 = n462 | n540;
assign n692 = n691 & n623 & (n272 | n535);
assign n693 = (n219 | n509) & (n37 | n523);
assign n694 = (n462 | n509) & (n43 | n518);
assign n695 = (n40 | n487) & (n53 | n505);
assign n696 = (n444 | n53) & (n40 | n544);
assign n697 = n390 & n696 & (n428 | n309);
assign n698 = (n37 | n538) & (n258 | n545);
assign n699 = n179 & (n91 | n494);
assign n700 = (n439 | n262) & (n272 | n41);
assign n701 = (n91 | n199) & (n258 | n523);
assign n702 = (n258 | n38) & (n100 | n476);
assign n703 = n619 & (n86 | n518);
assign n704 = (n222 | n448) & (n43 | n142);
assign n705 = (n436 | n530) & (n462 | n522);
assign n706 = (n436 | n515) & (n219 | n516);
assign n707 = n706 & (n436 | n310);
assign n708 = n550 & n60 & n703 & n702 & n701 & n705 & n704 & n707;
assign n709 = (n309 | n512) & (n53 | n545);
assign n710 = n40 | n515;
assign n711 = n351 & (n99 | n86);
assign n712 = n620 & n711 & (n43 | n543);
assign n713 = (n272 | n472) & (n91 | n54);
assign n714 = n309 | n535;
assign n715 = n714 & (n430 | n40);
assign n716 = (n219 | n494) & (n33 | n540);
assign n717 = n207 & n123 & n104 & n39 & n716 & n715;
assign n718 = (n40 | n506) & (n258 | n470);
assign n719 = (n272 | n542) & (n53 | n499);
assign n720 = (n436 | n517) & (n43 | n544);
assign n721 = n53 | n477;
assign n722 = (n53 | n482) & (n439 | n150);
assign n723 = (n439 | n483) & (n422 | n219);
assign n724 = (n43 | n508) & (n424 | n258);
assign n725 = (n33 & n258) | n547;
assign n726 = n222 | (n487 & n543);
assign n727 = (n33 | n516) & (n439 | n490);
assign n728 = n598 & (n436 | n528);
assign n729 = n595 & (n462 | n500);
assign n730 = (n40 | n535) & (n37 | n546);
assign n731 = n186 & (n309 | n142);
assign n732 = n309 | (n255 & n519);
assign n733 = (n430 | n272) & (n309 | n514);
assign n734 = n100 | n524;
assign n735 = n734 & n733 & (n272 | n475);
assign n736 = (n258 | n489) & (n100 | n536);
assign n737 = (n258 | n103) & (n462 | n38);
assign n738 = n444 | n219;
assign n739 = n462 | n503;
assign n740 = n386 & (n258 | n160);
assign n741 = (n422 | n33) & (n43 | n524);
assign n742 = (n222 | n521) & (n448 | n43);
assign n743 = n436 | (n495 & n512);
assign n744 = n681 & (n37 | n494);
assign n745 = (n219 | n523) & (n272 | n541);
assign n746 = (n37 | n496) & (n258 | n199);
assign n747 = n612 & (n434 | n258);
assign n748 = (n219 | n502) & (n272 | n537);
assign n749 = n219 | n522;
assign n750 = n219 | n262;
assign n751 = (n222 | n506) & (n43 | n472);
assign n752 = n595 & n194 & (n436 | n448);
assign n753 = n462 | n471;
assign n754 = (n258 | n483) & (n43 | n531);
assign n755 = n424 | n91;
assign n756 = n222 | (n529 & n530);
assign n757 = (n434 | n219) & (n222 | n542);
assign n758 = (n37 | n498) & (n436 | n294);
assign n759 = n258 | n546;
assign n760 = n40 | n472;
assign n761 = n760 & (n445 | n258);
assign n762 = (n309 | n525) & (n439 | n445);
assign n763 = (n309 | n493) & (n462 | n251);
assign n764 = n118 & (n219 | n534);
assign n765 = n272 | (n157 & n506);
assign n766 = n600 & n607 & (n33 | n539);
assign n767 = (n86 | n536) & (n37 | n511);
assign n768 = (n219 | n160) & (n86 | n517);
assign n769 = n222 | n519;
assign n770 = n222 | n525;
assign n771 = n40 | (n468 & n543);
assign n772 = (n91 | n486) & (n33 | n526);
assign n773 = n100 | (n495 & n544);
assign n774 = (n436 | n542) & (n222 | n517);
assign n775 = (n439 | n34) & (n40 | n463);
assign n776 = n258 | n534;
assign n777 = n189 & n147 & n77 & n776 & n775 & n774;
assign n778 = n309 | n476;
assign n779 = n436 | n519;
assign n780 = n680 & n652 & (n33 | n483);
assign n781 = n439 | n499;
assign n782 = n781 & n734 & (n37 | n486);
assign n783 = (n422 | n53) & (n43 | n517);
assign n784 = (n222 | n452) & (n258 | n469);
assign n785 = (n222 | n535) & (n462 | n490);
assign n786 = (n436 | n475) & (n91 | n522);
assign n787 = (n438 | n219) & (n33 | n498);
assign n788 = (n219 | n546) & (n37 | n500);
assign n789 = n445 | n91;
assign n790 = (n447 | n272) & (n37 | n504);
assign n791 = n184 & n790 & (n40 | n87);
assign n792 = (n53 & n258) | n488;
assign n793 = (n100 | n310) & (n91 | n502);
assign n794 = n793 & (n86 | n223);
assign n795 = n86 | (n491 & n529);
assign n796 = n558 & (n86 | n537);
assign n797 = n769 & n796 & (n43 | n542);
assign n798 = n753 & (n258 | n516);
assign n799 = (n258 | n526) & (n100 | n512);
assign n800 = n691 & n799 & (n272 | n531);
assign n801 = (n272 | n491) & (n33 | n504);
assign n802 = (n86 | n310) & (n37 | n199);
assign n803 = n44 & n802 & (n439 | n477);
assign n804 = n241 & n204 & n282;
assign n805 = n658 & n755 & (n91 | n500);
assign n806 = (n459 | n91) & (n53 | n504);
assign n807 = n57 & (n219 | n471);
assign n808 = n422 | n439;
assign n809 = n749 & (n222 | n465);
assign n810 = (n428 | n43) & (n462 | n150);
assign n811 = (n37 | n485) & (n222 | n533);
assign n812 = n436 | (n463 & n524);
assign n813 = n40 | (n142 & n530);
assign n814 = (n445 | n462) & (n444 | n258);
assign n815 = n814 & (n443 | n309);
assign n816 = (n272 | n481) & (n309 | n529);
assign n817 = (n258 | n478) & (n53 | n511);
assign n818 = n68 & n62 & (n439 | n160);
assign n819 = (n467 | n91) & (n462 | n482);
assign n820 = n687 & n819 & (n439 | n509);
assign n821 = (n33 | n473) & (n53 | n516);
assign n822 = n821 & n820 & (n40 | n531);
assign n823 = n91 | n499;
assign n824 = n823 & n689 & (n53 | n540);
assign n825 = (n436 | n543) & (n86 | n495);
assign n826 = n825 & n824 & (n258 | n505);
assign n827 = (n42 | n86) & (n428 | n272);
assign n828 = n394 & n357 & n385 & n311 & n295 & n336;
assign n829 = (n43 | n514) & (n462 | n483);
assign n830 = n684 & n829 & (n443 | n43);
assign n831 = (n91 | n490) & (n222 | n41);
assign n832 = (n436 | n501) & (n462 | n485);
assign n833 = (n436 | n41) & (n33 | n522);
assign n834 = n645 & n833 & (n438 | n258);
assign n835 = n603 & (n40 | n474);
assign n836 = n835 & n834 & (n309 | n521);
assign n837 = (n219 | n499) & (n272 | n142);
assign n838 = n683 & n837 & (n462 | n262);
assign n839 = (n272 | n458) & (n455 | n91);
assign n840 = n839 & n838 & (n439 | n488);
assign n841 = n647 & (n100 | n223);
assign n842 = n609 & n841 & (n439 | n511);
assign n843 = n33 | (n459 & n464);
assign n844 = (n436 | n506) & (n53 | n490);
assign n845 = n565 & n844 & (n43 | n41);
assign n846 = (n219 | n251) & (n91 | n505);
assign n847 = n37 | (n54 & n251);
assign n848 = (n439 | n540) & (n430 | n309);
assign n849 = n611 & (n462 | n464);
assign n850 = (n436 | n535) & (n43 | n487);
assign n851 = n275 & n850 & (n40 | n452);
assign n852 = n617 & (n40 | n475);
assign n853 = (n96 | n309) & (n40 | n310);
assign n854 = n853 & (n309 | n492);
assign n855 = (n258 | n538) & (n309 | n544);
assign n856 = (n219 | n504) & (n462 | n494);
assign n857 = n37 | n455;
assign n858 = n43 | n536;
assign n859 = (n37 & n53) | n547;
assign n860 = n779 & n859 & (n222 | n508);
assign n861 = n53 | (n154 & n259);
assign n862 = n861 & n860 & (n40 | n512);
assign n863 = (n53 | n538) & (n439 | n500);
assign n864 = n863 & (n100 | n543);
assign n865 = (n462 | n489) & (n100 | n510);
assign n866 = n865 & n864 & (n448 | n100);
assign n867 = (n436 | n481) & (n462 | n34);
assign n868 = (n436 | n474) & (n258 | n494);
assign n869 = n385 & n371 & n273 & n291 & n232 & n327;
endmodule

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// Benchmark "TOP" written by ABC on Mon Feb 4 17:31:57 2019
module ex5p (
i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_,
o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_,
o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_,
o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_,
o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_,
o_41_, o_42_, o_43_, o_44_, o_45_, o_46_, o_47_, o_48_, o_49_, o_50_,
o_51_, o_52_, o_53_, o_54_, o_55_, o_56_, o_57_, o_58_, o_59_, o_60_,
o_61_, o_62_ );
input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_;
output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_,
o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_,
o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_,
o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_,
o_41_, o_42_, o_43_, o_44_, o_45_, o_46_, o_47_, o_48_, o_49_, o_50_,
o_51_, o_52_, o_53_, o_54_, o_55_, o_56_, o_57_, o_58_, o_59_, o_60_,
o_61_, o_62_;
wire n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156,
n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168,
n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180,
n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192,
n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204,
n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216,
n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228,
n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252,
n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264,
n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276,
n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288,
n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300,
n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312,
n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324,
n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336,
n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360,
n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372,
n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384,
n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396,
n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408,
n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420,
n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432,
n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444,
n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456,
n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468,
n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480,
n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504,
n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516,
n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528,
n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564,
n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576,
n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597;
assign o_0_ = ~n365;
assign o_1_ = ~n361;
assign o_2_ = ~n403;
assign o_3_ = ~n370;
assign o_4_ = ~n450;
assign o_5_ = ~n357;
assign o_6_ = ~n136;
assign o_7_ = ~n180;
assign o_8_ = ~n452;
assign o_9_ = ~n491;
assign o_10_ = ~n139;
assign o_11_ = ~n179;
assign o_12_ = ~n385;
assign o_13_ = ~n471;
assign o_14_ = ~n507;
assign o_15_ = ~n138;
assign o_16_ = ~n407;
assign o_17_ = ~n354;
assign o_18_ = ~n421;
assign o_19_ = ~n420;
assign o_20_ = ~n142;
assign o_21_ = ~n145;
assign o_22_ = ~n148;
assign o_23_ = ~n352;
assign o_24_ = ~n504;
assign o_25_ = ~n200;
assign o_26_ = ~n151;
assign o_27_ = ~n260;
assign o_28_ = ~n556;
assign o_29_ = ~n506;
assign o_30_ = ~n150;
assign o_31_ = ~n347;
assign o_32_ = ~n344;
assign o_33_ = ~n340;
assign o_34_ = ~n336;
assign o_35_ = ~n332;
assign o_36_ = ~n328;
assign o_37_ = ~n321;
assign o_38_ = ~n314;
assign o_39_ = ~n308;
assign o_40_ = ~n303;
assign o_41_ = ~n296;
assign o_42_ = ~n291;
assign o_43_ = ~n284;
assign o_44_ = ~n276;
assign o_45_ = ~n274;
assign o_46_ = ~n268;
assign o_47_ = ~n264;
assign o_48_ = ~n259;
assign o_49_ = ~n257;
assign o_50_ = ~n252;
assign o_51_ = ~n245;
assign o_52_ = ~n238;
assign o_53_ = ~n232;
assign o_54_ = ~n226;
assign o_55_ = ~n220;
assign o_56_ = ~n214;
assign o_57_ = ~n205;
assign o_58_ = ~n197;
assign o_59_ = ~n189;
assign o_60_ = ~n182;
assign o_61_ = ~n173;
assign o_62_ = ~n164;
assign n134 = n155 | n439;
assign n135 = n155 | n441;
assign n136 = n134 & n135;
assign n137 = n436 | n339;
assign n138 = n445 | n339;
assign n139 = n137 & n138;
assign n140 = n462 | n152;
assign n141 = n463 | n152;
assign n142 = n140 & n141;
assign n143 = n439 | n152;
assign n144 = n441 | n152;
assign n145 = n143 & n144;
assign n146 = n434 | n152;
assign n147 = n446 | n152;
assign n148 = n146 & n147;
assign n149 = n434 | n373;
assign n150 = n434 | n369;
assign n151 = n149 & n150;
assign n152 = i_2_ | ~i_0_ | i_1_;
assign n153 = n152 | ~n381;
assign n154 = ~i_3_ | ~i_4_ | ~i_5_;
assign n155 = i_0_ | i_1_ | ~i_2_;
assign n156 = n154 | n155;
assign n157 = i_0_ | i_1_ | i_2_;
assign n158 = n157 | ~n366;
assign n159 = n373 & n338;
assign n160 = n514 & n505 & n363;
assign n161 = n515 & n339 & n269 & n195 & n496;
assign n162 = n179 & n458 & n408 & n461 & n374;
assign n163 = n150 & n516 & n517 & n176 & n454;
assign n164 = n159 & n160 & n161 & n162 & n163;
assign n165 = n398 & n533 & n535;
assign n166 = n523 & n524;
assign n167 = n412 & n503;
assign n168 = n504 & n363;
assign n169 = n450 & n556;
assign n170 = n372 & n555 & n180;
assign n171 = n254 & n243 & n400;
assign n172 = n518 & n192 & n554;
assign n173 = n165 & n166 & n167 & n168 & n169 & n170 & n171 & n172;
assign n174 = n208 & n309 & n563 & n421 & n254 & n518;
assign n175 = n410 & n560 & n192 & n165 & n457 & n461 & n150 & n516;
assign n176 = n452 & n451;
assign n177 = n362 & n552 & n454;
assign n178 = n369 | n462;
assign n179 = n436 | n409;
assign n180 = n436 | n270;
assign n181 = n369 | n463;
assign n182 = n174 & n175 & n176 & n177 & n178 & n179 & n180 & n181;
assign n183 = n411 & (n157 | ~n382) & n412;
assign n184 = n548 & n298;
assign n185 = n418 & (n239 | n409);
assign n186 = n569 & n570 & n310 & n345 & n169 & n334 & n255 & n163;
assign n187 = n265 & n573 & n170 & n203;
assign n188 = n594 & n493 & n487 & n483 & n408 & n397 & ~n383 & n387;
assign n189 = n183 & n184 & n185 & n186 & n187 & n188;
assign n190 = n576 & n575 & n532 & n451 & n414 & n140 & n297 & ~n367;
assign n191 = n493 & ~n383 & n492;
assign n192 = n405 & n550 & n404 & n145 & n551 & n549;
assign n193 = n563 & n272;
assign n194 = n421 & n485 & n487;
assign n195 = n478 & n481 & n475 & n477;
assign n196 = n351 & n158 & (n154 | n157);
assign n197 = n190 & n191 & n192 & n193 & n194 & n195 & n138 & n196;
assign n198 = n470 & n468;
assign n199 = n150 & n536;
assign n200 = n270 | n443;
assign n201 = n261 & n471 & n394;
assign n202 = n228 & n414 & (n339 | ~n382);
assign n203 = n179 & n572;
assign n204 = n221 & n215 & n422 & n185 & n423 & n300;
assign n205 = n198 & n199 & n200 & n201 & n166 & n202 & n203 & n204;
assign n206 = n578 & n579 & n554 & n169;
assign n207 = n310 & n577;
assign n208 = n496 & n562;
assign n209 = n580 & ~n395 & n491;
assign n210 = n149 & n378 & n370 & n419 & n306;
assign n211 = n501 & n563;
assign n212 = n180 & n518;
assign n213 = n228 & n171 & n467 & n196 & n594 & n376 & n534 & n471;
assign n214 = n206 & n207 & n208 & n209 & n210 & n211 & n212 & n213;
assign n215 = n563 & n183;
assign n216 = n537 & ~n367 & n451;
assign n217 = n534 & n275 & n139 & n142;
assign n218 = n570 & n571 & n184 & n581 & n337 & n582;
assign n219 = n156 & n171 & n427 & n200;
assign n220 = n215 & n216 & n180 & n166 & n217 & n218 & n219;
assign n221 = n396 & n180 & n159;
assign n222 = n474 & n247;
assign n223 = n519 & n348 & n494;
assign n224 = n472 & n470;
assign n225 = n572 & n575 & n478 & n538 & n158 & n458 & n534 & n468;
assign n226 = n209 & n219 & n193 & n221 & n222 & n223 & n224 & n225;
assign n227 = n449 & n452;
assign n228 = n525 & n526;
assign n229 = n146 & n527 & n528 & n529 & n530;
assign n230 = n391 & n392 & (n393 | n339);
assign n231 = n476 & n583 & n537 & n137 & n141 & n534;
assign n232 = n174 & n218 & n227 & n228 & n229 & n230 & n231;
assign n233 = n351 & n215;
assign n234 = n254 & n494 & n559 & n509 & n262 & n292 & n426;
assign n235 = n387 & n491;
assign n236 = n384 & n385 & (n373 | n386);
assign n237 = n510 & n548;
assign n238 = n233 & n234 & n224 & n235 & n236 & n186 & n162 & n237;
assign n239 = ~n381 & ~n382;
assign n240 = n155 | n239;
assign n241 = n255 & n240 & n389 & n387 & n584 & n491;
assign n242 = n488 & n489;
assign n243 = n421 & n482;
assign n244 = n254 & n494 & n453;
assign n245 = n175 & n212 & n227 & n233 & n241 & n242 & n243 & n244;
assign n246 = n560 & n203;
assign n247 = n408 & ((~n381 & ~n382) | n409);
assign n248 = n200 & n483 & n486;
assign n249 = n540 & n539;
assign n250 = n524 & n192 & n412 & n501 & n168 & n288 & n293;
assign n251 = n535 & n543 & n546 & n477 & n380 & n533;
assign n252 = n246 & n247 & n248 & n249 & n250 & n251;
assign n253 = n288 & n248 & n342 & n586 & n266;
assign n254 = n155 | n446;
assign n255 = n155 | n443;
assign n256 = n350 & n158 & n351 & n520;
assign n257 = n193 & n235 & n253 & n254 & n255 & n256;
assign n258 = n254 & n241 & n135 & n134;
assign n259 = n258 & n253 & n242 & n160;
assign n260 = n443 | n339;
assign n261 = n434 | n339;
assign n262 = n429 & n281 & n248;
assign n263 = n417 & n224 & (n393 | n270);
assign n264 = n260 & n190 & n139 & n261 & n262 & n250 & n263;
assign n265 = n421 & n156 & n468 & n200;
assign n266 = n210 & n585 & n345 & n207;
assign n267 = n196 & n496 & n160 & n396 & n180 & n515;
assign n268 = n265 & n191 & n206 & n263 & n266 & n267;
assign n269 = n493 & n492 & n194 & n196 & ~n383;
assign n270 = i_2_ | i_0_ | ~i_1_;
assign n271 = n260 & n261;
assign n272 = n500 & n330 & n420 & n411 & n497 & n498;
assign n273 = n577 & n206 & n210;
assign n274 = n269 & n168 & n270 & n271 & n272 & n217 & n273;
assign n275 = n530 & n568 & n146 & n529;
assign n276 = n211 & n273 & n161 & n275;
assign n277 = n567 & n530 & n482 & ~n415 & n137 & n228 & ~n395;
assign n278 = n196 & n330 & n451 & n431 & n254 & n491 & n588 & n589;
assign n279 = n484 & n363 & n486 & n502;
assign n280 = n180 & (n270 | n355);
assign n281 = n476 & n583 & n468 & n396;
assign n282 = n298 & n417 & n222;
assign n283 = n511 & n405 & n499 & n508 & n374 & n377 & n179 & n595;
assign n284 = n277 & n278 & n249 & n279 & n280 & n281 & n282 & n283;
assign n285 = n477 & n394 & n471 & n378;
assign n286 = n413 & n423 & n590 & n138 & n144 & n228;
assign n287 = n179 & n553;
assign n288 = n422 & n243;
assign n289 = n419 & n420 & n579;
assign n290 = n549 & n406 & n410 & n563 & n569 & n411 & n380 & n596;
assign n291 = n285 & n286 & n248 & n278 & n287 & n288 & n289 & n290;
assign n292 = n288 & n404 & (n152 | ~n366);
assign n293 = n326 & n426 & n258;
assign n294 = n585 & n586 & n345 & n248;
assign n295 = n547 & n405 & n560 & n542 & n543 & n546;
assign n296 = n292 & n293 & n294 & n193 & n207 & n223 & n295;
assign n297 = n458 & n246 & n247;
assign n298 = n402 & n547;
assign n299 = n356 & n550 & n564;
assign n300 = n254 & n400 & n543;
assign n301 = n405 & n318 & n473 & n536 & n476 & n469 & n474 & n409;
assign n302 = n482 & n411 & n153 & n339 & n380 & n330 & n523;
assign n303 = n275 & n297 & n298 & n299 & n300 & n279 & n301 & n302;
assign n304 = n573 & n185 & n581 & n587 & n315 & n167 & n203 & n591;
assign n305 = n153 & n531;
assign n306 = n356 & n564 & n184;
assign n307 = n470 & n142 & n145 & n194 & n261 & ~n382;
assign n308 = n277 & n285 & n304 & n305 & n306 & n258 & n307;
assign n309 = n196 & n492 & n561;
assign n310 = n142 & n275 & ~n415;
assign n311 = n149 & n298 & n419;
assign n312 = n147 & n370 & n508;
assign n313 = n327 & n503 & n363;
assign n314 = n309 & n310 & n206 & n294 & n311 & n312 & n208 & n313;
assign n315 = n575 & n576 & n457 & n454;
assign n316 = n448 & n513 & n459;
assign n317 = n447 & n512 & n136 & n145 & n526 & n495 & n460;
assign n318 = n525 & n478 & n481;
assign n319 = n405 & n562 & n578 & n230 & n532 & n371;
assign n320 = n541 & n556 & n147 & n449 & n510 & n551 & n565 & n597;
assign n321 = n315 & n316 & n317 & n211 & n234 & n318 & n319 & n320;
assign n322 = n477 & n550 & n342 & n318 & n311 & n471 & n470 & n592;
assign n323 = n146 & n590;
assign n324 = n561 & n548 & n531 & n491 & ~n382 & n387;
assign n325 = n356 & n507;
assign n326 = n242 & n256;
assign n327 = n482 & n254;
assign n328 = n322 & n323 & n193 & n324 & n325 & n326 & n327 & n194;
assign n329 = n325 & n353 & (n152 | ~n381);
assign n330 = n515 & n495;
assign n331 = n531 & n486 & n485;
assign n332 = n243 & n293 & n322 & n323 & n329 & n330 & n211 & n331;
assign n333 = n143 & (n152 | ~n382);
assign n334 = n416 & (n270 | ~n366) & n417;
assign n335 = n518 & n398 & n243 & n180 & n254 & n508;
assign n336 = n286 & n304 & n324 & n298 & n333 & n334 & n335;
assign n337 = n572 & n578 & n287;
assign n338 = n152 & n511 & n312 & n402 & n512 & n513;
assign n339 = ~i_2_ | i_0_ | ~i_1_;
assign n340 = n216 & n301 & n211 & n337 & n338 & n208 & n339 & n269;
assign n341 = n550 & n311 & n329;
assign n342 = n206 & n223;
assign n343 = n180 & n482;
assign n344 = n279 & n341 & n258 & n342 & n326 & n272 & n165 & n343;
assign n345 = n202 & n413 & n567;
assign n346 = n523 & n505 & n229 & n305 & n330 & n363 & ~n415;
assign n347 = n345 & n206 & n171 & n334 & n224 & n262 & n341 & n346;
assign n348 = n157 | n370;
assign n349 = n519 & n520;
assign n350 = n154 | n157;
assign n351 = n445 | n157;
assign n352 = n348 & n349 & n350 & n351;
assign n353 = n152 | ~n366;
assign n354 = n153 & n353;
assign n355 = n435 | n442;
assign n356 = n442 | n444;
assign n357 = n355 & n356;
assign n358 = n157 | n462;
assign n359 = n488 & n515 & n178 & n552 & n316 & n396 & n486 & n593;
assign n360 = (~n366 & ~n381) | n438;
assign n361 = n143 & n358 & n134 & n140 & n359 & n360;
assign n362 = n409 | n463;
assign n363 = n358 & n506;
assign n364 = n468 & n483 & n489 & n142 & n509 & n465;
assign n365 = n181 & n362 & n363 & n317 & n359 & n364;
assign n366 = i_3_ & i_4_ & ~i_5_;
assign n367 = ~n369 & (~n154 | n366);
assign n368 = n369 | (n356 & n378);
assign n369 = ~i_0_ | ~i_1_ | ~i_2_;
assign n370 = n438 | n444;
assign n371 = n368 & (n369 | n370);
assign n372 = n445 | n373;
assign n373 = ~i_2_ | ~i_0_ | i_1_;
assign n374 = n372 & ((n154 & ~n366) | n373);
assign n375 = n339 | n239;
assign n376 = n464 & n465;
assign n377 = n376 & (n270 | n154);
assign n378 = n440 | n444;
assign n379 = n270 | (n356 & n378);
assign n380 = n180 & (n270 | ~n381);
assign n381 = ~i_5_ & ~i_3_ & i_4_;
assign n382 = i_5_ & ~i_3_ & i_4_;
assign n383 = ~n155 & (n381 | n382);
assign n384 = n373 | n355;
assign n385 = n436 | n373;
assign n386 = n435 | n440;
assign n387 = n155 | n436;
assign n388 = n387 & (n155 | ~n381);
assign n389 = n155 | (n355 & n386);
assign n390 = ~n157 & (~n154 | n366);
assign n391 = n378 | n339;
assign n392 = n140 & n138 & n566;
assign n393 = n154 & ~n366;
assign n394 = n260 & n376 & (n393 | n270);
assign n395 = ~n339 & (n381 | n382);
assign n396 = n270 | n439;
assign n397 = n396 & (n270 | ~n382);
assign n398 = n198 & n397 & (n270 | ~n381);
assign n399 = n155 | ~n382;
assign n400 = n136 & (n239 | n155);
assign n401 = n369 | (n355 & n386);
assign n402 = n443 | n373;
assign n403 = n435 | n438;
assign n404 = n149 & n402 & (n373 | n403);
assign n405 = n236 & (n239 | n373);
assign n406 = n372 & (n393 | n373);
assign n407 = n409 | n445;
assign n408 = n459 & n460;
assign n409 = ~i_0_ | ~i_1_ | i_2_;
assign n410 = n407 & n408 & (n393 | n409);
assign n411 = n436 | n157;
assign n412 = n157 | ~n381;
assign n413 = n137 & (n339 | ~n381);
assign n414 = n391 & n565 & n534;
assign n415 = ~n339 & (~n154 | n366);
assign n416 = n271 & n377;
assign n417 = n471 & n379;
assign n418 = n407 & n455 & n456;
assign n419 = n385 & (n373 | ~n381);
assign n420 = n412 & (n157 | ~n382);
assign n421 = n155 | ~n366;
assign n422 = n421 & (n155 | n154);
assign n423 = n339 | (n239 & n393);
assign n424 = n373 | n393;
assign n425 = n155 | (n356 & n378);
assign n426 = n425 & (n155 | n370);
assign n427 = n434 | n270;
assign n428 = n270 | (n386 & n403);
assign n429 = n280 & n427 & n428;
assign n430 = n409 | (n434 & n443);
assign n431 = n386 & n355 & n430;
assign n432 = i_3_ | i_4_ | i_5_;
assign n433 = ~i_6_ | ~i_7_;
assign n434 = n432 | n433;
assign n435 = i_3_ | i_4_ | ~i_5_;
assign n436 = n433 | n435;
assign n437 = i_5_ | ~i_3_ | i_4_;
assign n438 = i_6_ | i_7_;
assign n439 = n437 | n438;
assign n440 = i_6_ | ~i_7_;
assign n441 = n437 | n440;
assign n442 = ~i_6_ | i_7_;
assign n443 = n432 | n442;
assign n444 = ~i_5_ | ~i_3_ | i_4_;
assign n445 = n433 | n444;
assign n446 = n433 | n437;
assign n447 = n369 | n441;
assign n448 = n369 | n439;
assign n449 = n369 | n446;
assign n450 = n437 | n442;
assign n451 = n447 & n448 & n449 & n450;
assign n452 = n436 | n369;
assign n453 = n369 | n445;
assign n454 = ~n367 & n453;
assign n455 = n409 | n356;
assign n456 = n409 | n378;
assign n457 = n409 | n446;
assign n458 = n457 & n418;
assign n459 = n439 | n409;
assign n460 = n441 | n409;
assign n461 = n403 & n431;
assign n462 = n432 | n438;
assign n463 = n432 | n440;
assign n464 = n339 | n462;
assign n465 = n339 | n463;
assign n466 = n403 | n339;
assign n467 = n466 & n271;
assign n468 = n270 | n441;
assign n469 = n468 & n396;
assign n470 = n270 | n446;
assign n471 = n270 | n445;
assign n472 = n270 | n370;
assign n473 = n470 & n379 & n471 & n472;
assign n474 = n270 | ~n366;
assign n475 = n474 & n473;
assign n476 = n270 | ~n382;
assign n477 = n476 & n469;
assign n478 = n377 & n467;
assign n479 = n386 | n339;
assign n480 = n355 | n339;
assign n481 = n479 & n375 & n137 & n480;
assign n482 = n155 | n445;
assign n483 = n270 | n463;
assign n484 = n427 & n200 & n483;
assign n485 = n484 & n380;
assign n486 = n270 | n462;
assign n487 = n486 & n156;
assign n488 = n155 | n462;
assign n489 = n155 | n463;
assign n490 = n255 & n242;
assign n491 = n434 | n155;
assign n492 = n387 & n491 & n490;
assign n493 = n136 & n327;
assign n494 = n446 | n157;
assign n495 = n441 | n157;
assign n496 = n494 & n495;
assign n497 = n355 | n157;
assign n498 = n386 | n157;
assign n499 = n411 & n497 & n498;
assign n500 = n403 | n157;
assign n501 = n500 & n499;
assign n502 = n434 | n157;
assign n503 = n502 & n501;
assign n504 = n443 | n157;
assign n505 = n412 & n504 & n503;
assign n506 = n157 | n463;
assign n507 = n445 | n152;
assign n508 = n378 & n325;
assign n509 = n441 | n373;
assign n510 = n439 | n373;
assign n511 = n509 & n510;
assign n512 = n373 | n463;
assign n513 = n373 | n462;
assign n514 = n157 | ~n382;
assign n515 = n439 | n157;
assign n516 = n369 | n443;
assign n517 = n393 | n409;
assign n518 = n486 & n156 & n484;
assign n519 = n378 | n157;
assign n520 = n356 | n157;
assign n521 = n584 & n491 & n255;
assign n522 = n521 & n489 & n488 & n349 & n351 & n388 & n389 & ~n390;
assign n523 = n494 & n522;
assign n524 = n514 & n330;
assign n525 = n439 | n339;
assign n526 = n441 | n339;
assign n527 = n355 | n152;
assign n528 = n386 | n152;
assign n529 = n403 | n152;
assign n530 = n443 | n152;
assign n531 = n436 | n152;
assign n532 = n141 & n229 & n305;
assign n533 = n137 & n201 & ~n395;
assign n534 = n446 | n339;
assign n535 = n230 & n532 & n534 & n228;
assign n536 = n516 & n181 & n178;
assign n537 = n239 | n369;
assign n538 = n537 & n451 & n454 & n401 & n371;
assign n539 = n407 & n455;
assign n540 = ~n366 | n409;
assign n541 = n409 | n370;
assign n542 = n540 & n408 & n539 & n456 & n541 & n457;
assign n543 = n452 & n538;
assign n544 = n369 | n403;
assign n545 = n154 | n409;
assign n546 = n544 & n545 & n199;
assign n547 = n513 & n512;
assign n548 = n154 | n152;
assign n549 = n325 & n547 & n353 & n548;
assign n550 = n147 & n378 & n370;
assign n551 = n152 | ~n382;
assign n552 = n409 | n462;
assign n553 = n239 | n409;
assign n554 = n543 & n546 & n461 & n542 & n552 & n553 & n179 & n362;
assign n555 = n373 | ~n382;
assign n556 = n446 | n373;
assign n557 = n356 | n373;
assign n558 = n378 | n373;
assign n559 = n373 | n370;
assign n560 = n511 & n169 & n406 & n557 & n558 & n559;
assign n561 = n136 & ~n383;
assign n562 = n515 & n514 & n412;
assign n563 = n502 & n168;
assign n564 = n507 & n353;
assign n565 = n339 | n370;
assign n566 = n356 | n339;
assign n567 = n138 & n566;
assign n568 = n531 & n527 & n528;
assign n569 = n153 & n333;
assign n570 = n144 & n299;
assign n571 = n149 & n419;
assign n572 = n362 & n552 & n461;
assign n573 = n326 & n571 & n524 & n168;
assign n574 = n452 & n537 & n401;
assign n575 = n517 & n199;
assign n576 = n544 & n574;
assign n577 = n153 & n333 & n144 & n147;
assign n578 = n558 & n424 & n372 & n557;
assign n579 = n509 & n510 & n555;
assign n580 = n350 & n490;
assign n581 = n169 & n579;
assign n582 = n473 & n536 & n569 & n150 & n458 & n271;
assign n583 = n270 | ~n381;
assign n584 = n155 | n403;
assign n585 = n466 & n416 & n480 & n479;
assign n586 = n429 & n281 & n263;
assign n587 = n534 & n494;
assign n588 = n457 & n261 & n470;
assign n589 = n580 & n587 & n568 & n574 & n536 & n177 & n388 & n400;
assign n590 = n142 & n530;
assign n591 = n451 & n408 & n374;
assign n592 = n145 & n339 & n474;
assign n593 = n510 & n525 & n464;
assign n594 = n239 | n270;
assign n595 = n545 & n260;
assign n596 = n151 & n402 & n427;
assign n597 = n418 & n475 & n522 & n534 & n348 & n399;
endmodule

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// Benchmark "TOP" written by ABC on Mon Feb 4 17:32:57 2019
module misex3 (
a, b, c, d, e, f, g, h, i, j, k, l, m, n,
r2, s2, t2, u2, n2, o2, p2, q2, h2, i2, j2, k2, m2, l2 );
input a, b, c, d, e, f, g, h, i, j, k, l, m, n;
output r2, s2, t2, u2, n2, o2, p2, q2, h2, i2, j2, k2, m2, l2;
wire n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69,
n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83,
n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109,
n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145,
n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157,
n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205,
n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217,
n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241,
n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253,
n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265,
n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277,
n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289,
n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301,
n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313,
n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325,
n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349,
n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361,
n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373,
n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385,
n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397,
n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409,
n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, n421,
n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, n433,
n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445,
n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469,
n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493,
n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, n505,
n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517,
n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541,
n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553,
n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565,
n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625,
n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649,
n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661,
n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685,
n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697,
n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757,
n758, n759, n760, n761, n762;
assign r2 = ~n293;
assign s2 = ~n74;
assign t2 = ~n217;
assign u2 = ~n148;
assign n2 = ~n68;
assign o2 = ~n62;
assign p2 = ~n388;
assign q2 = ~n349;
assign h2 = ~n56;
assign i2 = ~n569;
assign j2 = ~n55;
assign k2 = ~n50;
assign m2 = ~n456;
assign l2 = ~n757 | ~n759 | n46 | ~n747 | n44 | n45 | n42 | n43;
assign n42 = f & (~n680 | ~n739 | ~n740);
assign n43 = ~f & (n475 | n476 | ~n735);
assign n44 = ~n & (~n722 | ~n724 | ~n728);
assign n45 = n & (~n518 | ~n730 | ~n731);
assign n46 = n548 | ~n744 | n544 | n547 | n542 | ~n543 | ~n540 | n541;
assign n47 = n675 | n676 | n372 | i | l;
assign n48 = n438 | n549 | n189;
assign n49 = n434 & n662 & n661 & n51 & n437 & n439;
assign n50 = n49 & n47 & n48;
assign n51 = n657 & n573 & n656 & n431 & n425 & n428;
assign n52 = n443 & n442 & n440 & n441;
assign n53 = n675 | n189 | n438;
assign n54 = n179 | n480 | n550 | n551;
assign n55 = n54 & n53 & n51 & n52;
assign n56 = n579 & n578 & n577 & n576 & n575 & n574 & n572 & n573;
assign n57 = (n95 | n408) & (n409 | n88);
assign n58 = n96 | n121;
assign n59 = n648 & ~n404 & n361 & n402;
assign n60 = n83 | n317;
assign n61 = (n362 | n300) & (n363 | n426);
assign n62 = ~n416 & ~n415 & ~n414 & n61 & n60 & n59 & n57 & n58;
assign n63 = j | n243 | n119 | n591;
assign n64 = (n177 | n362) & (n684 | n409);
assign n65 = ~n297 & (n95 | n253 | n298);
assign n66 = n620 & n619 & n572 & n618 & n617 & n69 & n574 & n211;
assign n67 = ~n422 & (n591 | (n710 & n711));
assign n68 = ~n420 & ~n419 & n67 & n66 & n65 & n64 & n59 & n63;
assign n69 = n92 | n407 | n91;
assign n70 = n595 | n92;
assign n71 = n264 | ~d | n248;
assign n72 = n701 & (n236 | n79);
assign n73 = n232 & (n152 | n632);
assign n74 = ~n267 & ~n266 & ~n265 & n73 & n72 & n71 & n69 & n70;
assign n75 = ~h | ~k;
assign n76 = n75 | l;
assign n77 = n623 | ~n658;
assign n78 = ~n167 & (n77 | ~n586);
assign n79 = ~c | n459;
assign n80 = e | n521;
assign n81 = n612 & n302;
assign n82 = n81 & n79 & n80;
assign n83 = ~k | n199;
assign n84 = m | j | ~l;
assign n85 = n83 & (~n | n84);
assign n86 = n684 | n83;
assign n87 = (n192 | n605) & (n206 | n604);
assign n88 = ~g | n603;
assign n89 = n86 & n87 & (n85 | n88);
assign n90 = (n110 | n156) & (n113 | n275);
assign n91 = ~i | n538;
assign n92 = ~a | n521;
assign n93 = n90 & (n91 | n92);
assign n94 = ~g | n600;
assign n95 = n285 & n397;
assign n96 = ~k | n167;
assign n97 = n96 | n94 | n95;
assign n98 = n601 | n199;
assign n99 = ~i | n368;
assign n100 = n98 & (~n | n99);
assign n101 = ~h | n538;
assign n102 = ~n | n129;
assign n103 = h | n538;
assign n104 = (n100 | n103) & (n101 | n102);
assign n105 = ~g | n249;
assign n106 = h | n197;
assign n107 = (n100 | n106) & (n102 | n105);
assign n108 = ~k | n179;
assign n109 = n108 & (n | n84);
assign n110 = n608 & n287 & n607;
assign n111 = (n101 | n92) & (n110 | n105);
assign n112 = n135 | n119;
assign n113 = n218 & n295;
assign n114 = ~g | n393;
assign n115 = n112 & n111 & (n113 | n114);
assign n116 = (n110 | n164) & (n113 | n189);
assign n117 = e | n609;
assign n118 = n116 & (n92 | n117);
assign n119 = ~a | n271;
assign n120 = ~e | n609;
assign n121 = n118 & (n119 | n120);
assign n122 = (n110 | n106) & (n113 | n202);
assign n123 = n122 & (n92 | n103);
assign n124 = n153 | n399;
assign n125 = ~n610 | ~g | n237;
assign n126 = j | n154;
assign n127 = ~i | n609;
assign n128 = n124 & n125 & (n126 | n127);
assign n129 = n401 & n512 & n527 & n760;
assign n130 = (n106 | n99) & (n129 | n105);
assign n131 = n519 | ~i | n121;
assign n132 = (n123 | n588) & (n95 | n128);
assign n133 = ~e | n271;
assign n134 = n131 & n132 & (n130 | n133);
assign n135 = ~h | n243;
assign n136 = h | n243;
assign n137 = (n100 | n136) & (n135 | n102);
assign n138 = ~n137 & (~n625 | (b & ~n479));
assign n139 = ~n89 & (~n325 | ~n606);
assign n140 = ~n167 & (~n683 | (~n121 & ~n601));
assign n141 = ~n95 & (~n687 | (~n96 & ~n127));
assign n142 = n133 | n601 | n179 | n106;
assign n143 = n590 | n591;
assign n144 = n136 | n587 | n588;
assign n145 = ~n139 & ~n140 & (n | n134);
assign n146 = (n93 | n591) & (n104 | n616);
assign n147 = n688 & (n107 | n269);
assign n148 = n147 & n146 & n145 & n144 & n143 & n142 & n66 & ~n138;
assign n149 = n689 | n108;
assign n150 = (n372 | n193) & (n613 | n624);
assign n151 = ~f | n603;
assign n152 = n149 & n150 & (n109 | n151);
assign n153 = ~m | n611;
assign n154 = ~l | ~m;
assign n155 = n153 & (i | n154);
assign n156 = ~i | n197;
assign n157 = j | n197;
assign n158 = n156 & n157;
assign n159 = (n155 | n105) & (n158 | n589);
assign n160 = n690 & (n164 | n126);
assign n161 = n644 & n647;
assign n162 = i | n197;
assign n163 = n159 & n160 & (n161 | n162);
assign n164 = g | n249;
assign n165 = (n164 | n96) & (n | n163);
assign n166 = n75 | ~m | n;
assign n167 = ~m | n;
assign n168 = ~l | ~h | j;
assign n169 = n166 & (n167 | n168);
assign n170 = ~f | n243;
assign n171 = ~e | n196;
assign n172 = (n169 | n171) & (~n78 | n170);
assign n173 = n196 | d | n169;
assign n174 = d | n197;
assign n175 = n173 & (~n78 | n174);
assign n176 = j | n75;
assign n177 = n176 & (i | n75);
assign n178 = n299 & n300 & n76 & n177;
assign n179 = m | n;
assign n180 = j | n603;
assign n181 = ~l | n179;
assign n182 = (n180 | n181) & (n178 | n179);
assign n183 = ~e | n615;
assign n184 = ~n | n183;
assign n185 = (n99 | n184) & (n98 | n183);
assign n186 = ~n184 & ~n761 & (~n114 | ~n189);
assign n187 = ~n186 & (n185 | (n202 & n676));
assign n188 = n183 | n391;
assign n189 = g | n393;
assign n190 = n187 & (n188 | (n114 & n189));
assign n191 = (n206 | n624) & (n689 | n83);
assign n192 = k | n199;
assign n193 = ~j | n249;
assign n194 = n191 & (n192 | n193);
assign n195 = n194 & (n85 | n151);
assign n196 = ~f | g;
assign n197 = ~f | ~g;
assign n198 = (n169 | n196) & (~n78 | n197);
assign n199 = m | ~n;
assign n200 = ~l | n199;
assign n201 = (n180 | n200) & (n178 | n199);
assign n202 = h | n570;
assign n203 = (n100 | n202) & (n102 | n114);
assign n204 = n203 & (n201 | (n170 & n171));
assign n205 = n691 & n692 & (n85 | n314);
assign n206 = l | n199;
assign n207 = ~k | n393;
assign n208 = n89 & n205 & (n206 | n207);
assign n209 = ~n152 & (~n133 | ~n430);
assign n210 = n595 | n599;
assign n211 = n595 | n353;
assign n212 = n693 & (~e | n195 | n324);
assign n213 = ~n209 & (n285 | (n165 & n595));
assign n214 = n208 | n315;
assign n215 = (n172 | n119) & (n175 | n287);
assign n216 = n694 & (n182 | n302);
assign n217 = n216 & n190 & n215 & n214 & n213 & n212 & n210 & n211;
assign n218 = ~a | n560;
assign n219 = n167 | n218;
assign n220 = (n168 | n219) & (n218 | n166);
assign n221 = ~n658 | ~n586 | n623;
assign n222 = ~f & ~n538;
assign n223 = ~n219 & n221 & (n222 | ~n261);
assign n224 = e | n488;
assign n225 = e | n196;
assign n226 = ~n223 & (n220 | (n224 & n225));
assign n227 = n393 | ~j | n372;
assign n228 = (n613 | n207) & (n109 | n314);
assign n229 = n640 & n643;
assign n230 = n227 & n228 & (n229 | n108);
assign n231 = ~e | n626;
assign n232 = n190 & n226 & (n230 | n231);
assign n233 = ~n83 & (~n252 | ~n639);
assign n234 = (n192 | n322) & (n256 | n206);
assign n235 = g | n603;
assign n236 = ~n233 & n234 & (n85 | n235);
assign n237 = k | n154;
assign n238 = (i | n161) & (~j | n237);
assign n239 = ~n591 & (~n91 | (~j & ~n538));
assign n240 = ~n239 & (n | (n699 & n700));
assign n241 = n165 & n240 & (n96 | n117);
assign n242 = ~i | n243;
assign n243 = ~e | ~g;
assign n244 = n242 & (j | n243);
assign n245 = n96 | n120;
assign n246 = n697 & (n120 | n126);
assign n247 = n696 & n695 & (n244 | n589);
assign n248 = n245 & (n | (n246 & n247));
assign n249 = ~f | ~h;
assign n250 = n249 | n102 | e;
assign n251 = n629 & n88;
assign n252 = j | n609;
assign n253 = i | n602;
assign n254 = ~g | n360;
assign n255 = n254 & n253 & n251 & n252;
assign n256 = g | n75;
assign n257 = n698 & (n376 | (n628 & n649));
assign n258 = (n94 | n96) & (n629 | n630);
assign n259 = ~l | n167;
assign n260 = n257 & n258 & (n255 | n259);
assign n261 = ~f | n538;
assign n262 = (n169 | n225) & (~n78 | n261);
assign n263 = ~n260 & (~n655 | (d & ~n524));
assign n264 = a | ~b;
assign n265 = ~n201 & (~n325 | (~n261 & ~n616));
assign n266 = ~n352 & (~n262 | n263);
assign n267 = ~n526 & (~n250 | (~n100 & ~n631));
assign n268 = n344 & (n83 | n633);
assign n269 = ~b | n598;
assign n270 = n268 & (n194 | n269);
assign n271 = ~c | d;
assign n272 = n79 & (~f | n271);
assign n273 = (n100 | n634) & (n164 | n102);
assign n274 = n273 & n107;
assign n275 = ~i | n570;
assign n276 = j | n570;
assign n277 = n275 & n276;
assign n278 = (n155 | n114) & (n277 | n589);
assign n279 = n749 & (n189 | n126);
assign n280 = i | n570;
assign n281 = n278 & n279 & (n161 | n280);
assign n282 = (n96 | n189) & (n | n281);
assign n283 = n286 | g | n169;
assign n284 = n283 & (d | ~n78 | n243);
assign n285 = ~e | n264;
assign n286 = d | ~e;
assign n287 = c | ~a | ~b;
assign n288 = n285 & (n286 | n287);
assign n289 = (n236 | n635) & (n104 | n616);
assign n290 = (n260 | n288) & (n284 | ~n545);
assign n291 = n107 | n315;
assign n292 = (n182 | n272) & (n274 | n625);
assign n293 = n292 & n291 & n290 & n289 & n270 & n232;
assign n294 = n123 & (n119 | n136);
assign n295 = n596 & n594;
assign n296 = n112 & n111 & (n295 | n114);
assign n297 = ~n636 & (~n355 | (~n167 & ~n296));
assign n298 = n | n126;
assign n299 = ~h | n360;
assign n300 = ~k | n603;
assign n301 = n180 & n300 & n299 & n176;
assign n302 = ~c | n524;
assign n303 = n302 & (~c | n196);
assign n304 = (n113 | n646) & (~j | n645);
assign n305 = ~j | n197;
assign n306 = n304 & (n110 | n305);
assign n307 = n121 & (n95 | n94);
assign n308 = ~n95 & ~n644 & (~n88 | ~n660);
assign n309 = ~n308 & (n329 | n339 | n435);
assign n310 = (n118 | n126) & (n306 | n237);
assign n311 = ~l | n519;
assign n312 = n309 & n310 & (n307 | n311);
assign n313 = n183 & n390;
assign n314 = f | n603;
assign n315 = ~b | n286;
assign n316 = (n314 | n315) & (n313 | n235);
assign n317 = n633 & n316;
assign n318 = (n80 & (~n | n371)) | (n & n371);
assign n319 = (n88 | n318) & (~n | n317);
assign n320 = n393 | ~j | n315;
assign n321 = n269 | n193;
assign n322 = ~j | n609;
assign n323 = n320 & n321 & (n313 | n322);
assign n324 = b | ~c;
assign n325 = ~f | n324;
assign n326 = (n315 | n643) & (n313 | n252);
assign n327 = j | n249;
assign n328 = n326 & (n269 | n327);
assign n329 = ~h | n621;
assign n330 = n328 & (n325 | n329);
assign n331 = (n316 | n84) & (n330 | n435);
assign n332 = m | k | ~l;
assign n333 = n331 & (n323 | n332);
assign n334 = (n315 | n640) & (n313 | n639);
assign n335 = i | n249;
assign n336 = n334 & (n269 | n335);
assign n337 = ~n199 & (~n336 | (~n253 & ~n371));
assign n338 = ~n337 & (n80 | n179 | n253);
assign n339 = n303 & n637;
assign n340 = (n339 | n181) & (n325 | n200);
assign n341 = ~n318 & (~n704 | (~n332 & ~n605));
assign n342 = n243 | n490 | ~j | n119;
assign n343 = n298 | n119 | n120;
assign n344 = n633 | ~n | n84;
assign n345 = n705 & (n301 | n340);
assign n346 = n65 & (n319 | n435);
assign n347 = (n312 & (~n | n333)) | (n & n333);
assign n348 = (n682 | n641) & (n338 | n433);
assign n349 = n348 & n347 & n346 & n345 & n344 & n343 & ~n341 & n342;
assign n350 = (n113 | n280) & (i | n645);
assign n351 = n350 & (n110 | n162);
assign n352 = ~a | n324;
assign n353 = ~b | n597;
assign n354 = n353 & n287 & n352;
assign n355 = n114 | n219;
assign n356 = (n599 | n105) & (n295 | n114);
assign n357 = n112 & (n92 | (n105 & n101));
assign n358 = n355 & (n167 | (n356 & n357));
assign n359 = n707 & (n285 | n630 | n605);
assign n360 = ~j | k;
assign n361 = n359 & (n358 | n360);
assign n362 = (n339 | n179) & (n325 | n199);
assign n363 = (n339 | n108) & (n325 | n83);
assign n364 = ~n88 & (~n706 | (~n167 & ~n433));
assign n365 = ~n364 & (n629 | (n259 & n630));
assign n366 = n365 & (n96 | n322);
assign n367 = n519 | n | n121;
assign n368 = ~k | m;
assign n369 = (n253 | n318) & (~n | n336);
assign n370 = n367 & (n368 | (n369 & n319));
assign n371 = n395 & n315 & n606;
assign n372 = k | n179;
assign n373 = (n372 | n80) & (n371 | n192);
assign n374 = ~i | k | ~l | n167;
assign n375 = ~k | ~n610;
assign n376 = l | n167;
assign n377 = n374 & (n375 | (n376 & n259));
assign n378 = ~j | n603;
assign n379 = n378 & n329;
assign n380 = n644 | n587 | n627;
assign n381 = n647 | n587 | n627;
assign n382 = n351 | n | n161;
assign n383 = (n294 | n377) & (n363 | n379);
assign n384 = n373 | n605;
assign n385 = (n95 | n366) & (~j | n370);
assign n386 = n362 | n299;
assign n387 = n361 & (n323 | n192);
assign n388 = n387 & n386 & n385 & n384 & n383 & n382 & n380 & n381;
assign n389 = ~n372 & (~n303 | ~n637);
assign n390 = n635 & n638;
assign n391 = ~n | n401;
assign n392 = n188 & (n390 | n391);
assign n393 = f | ~h;
assign n394 = (n393 | n315) & (n249 | n269);
assign n395 = n616 & n625;
assign n396 = e | n324;
assign n397 = ~b | n524;
assign n398 = n397 & n396 & n395 & n315;
assign n399 = ~i | n602;
assign n400 = (n398 | n399) & (~i | n394);
assign n401 = m | n360;
assign n402 = n399 | n | n80 | n401;
assign n403 = h & n610;
assign n404 = n403 & (n389 | (~n192 & ~n325));
assign n405 = n253 | n641;
assign n406 = (n256 | n167) & (n376 | n176);
assign n407 = n | n592;
assign n408 = n405 & n406 & (n407 | n399);
assign n409 = (n108 | n80) & (n371 | n83);
assign n410 = i & ~n394;
assign n411 = n & (n410 | (~n127 & ~n313));
assign n412 = j | i;
assign n413 = n412 | ~k | n259;
assign n414 = ~n115 & (~n413 | (n77 & ~n167));
assign n415 = ~n527 & (n411 | (~n318 & ~n399));
assign n416 = ~n591 & (~n709 | (~n110 & ~n327));
assign n417 = ~n433 & (~n351 | (~n119 & ~n627));
assign n418 = ~n311 & ~n & ~n251;
assign n419 = ~n95 & (n418 | (~n376 & ~n649));
assign n420 = ~n83 & (~n328 | ~n336);
assign n421 = i & k;
assign n422 = ~n167 & (n417 | (~n294 & n421));
assign n423 = n654 | ~f | n598;
assign n424 = j | k;
assign n425 = n259 | n399 | n423 | n424;
assign n426 = ~h | n600;
assign n427 = n651 | ~n | n557;
assign n428 = n427 | n426 | n332;
assign n429 = n650 | n114 | n181;
assign n430 = ~e | n521;
assign n431 = n429 | n430;
assign n432 = ~n545 | n655;
assign n433 = ~l | ~j | ~k;
assign n434 = n399 | n167 | n432 | n433;
assign n435 = ~l | n368;
assign n436 = n170 | n526;
assign n437 = n436 | ~n403 | n435;
assign n438 = n181 | n375;
assign n439 = n438 | n231 | n105;
assign n440 = n652 | n202 | n632;
assign n441 = ~n653 | n435 | n445;
assign n442 = n181 | n202 | n430 | ~n473;
assign n443 = n712 & (n332 | n427 | n378);
assign n444 = n106 | n613 | n231 | n658;
assign n445 = h | n621;
assign n446 = m | k | l;
assign n447 = n444 & (n436 | n445 | n446);
assign n448 = n551 | n | n446;
assign n449 = n448 & (n179 | n127 | n433);
assign n450 = k | n189 | n181 | n632;
assign n451 = n332 | n651 | ~h | n224;
assign n452 = n450 & n451;
assign n453 = n641 | n654 | n660 | n477;
assign n454 = n105 | n181 | n549 | n650;
assign n455 = (n449 | n480) & (n452 | n412);
assign n456 = n455 & n454 & n453 & n49 & n52 & n447;
assign n457 = i | n179;
assign n458 = (~k | n457) & (n179 | ~n412);
assign n459 = e | ~f;
assign n460 = a | n526;
assign n461 = j & ~n630 & (n459 | n460);
assign n462 = ~n758 & (~h | n438 | ~n479);
assign n463 = f | ~c | e;
assign n464 = ~n461 & n462 & (n458 | n463);
assign n465 = b | n199;
assign n466 = n200 & n83 & n465 & n298;
assign n467 = (b | n200) & (c | n181);
assign n468 = ~n167 & (~n737 | (~b & ~n479));
assign n469 = h | j | n199;
assign n470 = (j | n83) & (~i | n663);
assign n471 = ~j | n199;
assign n472 = n469 & n470 & (~h | n471);
assign n473 = ~k & n610;
assign n474 = n473 & b & ~n199;
assign n475 = ~h & (n474 | (~i & ~n206));
assign n476 = ~n673 & (~n521 | (~e & n324));
assign n477 = f | n659;
assign n478 = n477 & (f | a | e);
assign n479 = c | d;
assign n480 = f | n479;
assign n481 = n669 | c | e;
assign n482 = b | e | ~n | n669;
assign n483 = n375 | ~n615 | ~h | n259;
assign n484 = (d | n734) & (n457 | n480);
assign n485 = n199 | n675;
assign n486 = ~n762 & n485 & n484 & n483 & n481 & n482;
assign n487 = c & ~n655;
assign n488 = f | g;
assign n489 = b | n488;
assign n490 = n | n237;
assign n491 = (j | n490) & (n199 | ~n626);
assign n492 = ~n199 & (~n741 | (~j & ~n525));
assign n493 = n742 & (n670 | n671);
assign n494 = ~n492 & ~n756 & (i | n491);
assign n495 = n493 & n494 & (n457 | n271);
assign n496 = c | n488;
assign n497 = n664 & n463;
assign n498 = (n106 | n231) & (~j | n497);
assign n499 = (n716 | n167) & (n498 | n179);
assign n500 = n496 | n372;
assign n501 = (n527 | n671) & (n719 | n613);
assign n502 = n718 & (n436 | (n206 & n192));
assign n503 = n502 & n501 & n499 & n500;
assign n504 = ~j & ~n372 & (~n271 | ~n302);
assign n505 = (b | n199) & (c | n179);
assign n506 = ~b | ~e | ~n | n666;
assign n507 = e | n505 | n650;
assign n508 = (n525 | n471) & (n457 | n479);
assign n509 = n478 | n167;
assign n510 = ~n626 | j | n192;
assign n511 = n510 & n509 & n508 & n507 & ~n504 & n506;
assign n512 = i | n368;
assign n513 = m | n603;
assign n514 = i | m;
assign n515 = n512 & n513 & (~l | n514);
assign n516 = n253 & n127;
assign n517 = (n426 | n446) & (n516 | n666);
assign n518 = n517 & (n401 | n151);
assign n519 = ~k | ~m;
assign n520 = n519 & (j | ~m);
assign n521 = c | ~d;
assign n522 = n81 & (g | n521);
assign n523 = ~n311 & n403 & (~n174 | ~n261);
assign n524 = ~e | f;
assign n525 = b | n524;
assign n526 = ~d | n615;
assign n527 = j | n368;
assign n528 = n99 & n527;
assign n529 = n717 & (h | n524 | n636);
assign n530 = (n521 | n525) & (~j | n716);
assign n531 = (i | n432) & (n254 | n665);
assign n532 = n634 & n550 & (n135 | n650);
assign n533 = n532 & n531 & n529 & n530;
assign n534 = ~c & ~n524;
assign n535 = (~n180 | ~n628) & (~n463 | n534);
assign n536 = ~j & (~n660 | (~n156 & ~n231));
assign n537 = n396 & (a | c | e);
assign n538 = e | ~g;
assign n539 = ~n162 & (~n108 | ~n181);
assign n540 = n375 | n259 | n114;
assign n541 = ~n489 & (~n206 | ~n663);
assign n542 = ~n613 & (~n497 | (~c & ~n660));
assign n543 = n438 | n101;
assign n544 = ~n231 & (n539 | (~n156 & ~n613));
assign n545 = a & ~n615;
assign n546 = n545 & ~n655 & (~n630 | ~n672);
assign n547 = ~n457 & (~n631 | (~n105 & ~n231));
assign n548 = ~n179 & (n535 | n536 | ~n715);
assign n549 = ~e | n479;
assign n550 = l | n424;
assign n551 = i | g | h;
assign n552 = n112 | n155 | n;
assign n553 = n119 | n245;
assign n554 = f | n167;
assign n555 = (n168 | n554) & (f | n166);
assign n556 = n555 | ~e | g;
assign n557 = f | n243;
assign n558 = n556 & (~n78 | n557);
assign n559 = ~n99 & ~g & n;
assign n560 = ~b | ~d;
assign n561 = (n203 | n560) & (n526 | ~n748);
assign n562 = (n175 | n287) & (n282 | n594);
assign n563 = n236 | n638;
assign n564 = (n352 | n558) & (~e | n561);
assign n565 = n608 | n172;
assign n566 = n677 & n553 & n552 & n342 & n143 & n63;
assign n567 = n226 & n270 & (n89 | n625);
assign n568 = n750 & n752 & n656 & n661 & n441 & n657 & n440 & n662;
assign n569 = n568 & n567 & n447 & n566 & n565 & n564 & n562 & n563;
assign n570 = f | ~g;
assign n571 = (g | n555) & (~n78 | n570);
assign n572 = n595 | n352;
assign n573 = n652 | n106 | n549;
assign n574 = n593 | n596;
assign n575 = n626 | ~a | n262;
assign n576 = n571 | ~d | ~n545;
assign n577 = n753 & (n654 | (n175 & n248));
assign n578 = n282 | n596;
assign n579 = n566 & (n165 | n352);
assign n580 = l | ~n421;
assign n581 = ~l | ~h | i;
assign n582 = (~l & n622) | (n603 & (l | n622));
assign n583 = ~h | n611;
assign n584 = ~l | n360;
assign n585 = ~l | n621;
assign n586 = n585 & n584 & n583 & n582 & n580 & n581;
assign n587 = n | n119;
assign n588 = ~i | n154;
assign n589 = l | n519;
assign n590 = n119 | n242;
assign n591 = n | n589;
assign n592 = j | n519;
assign n593 = n407 | n275;
assign n594 = ~a | n286;
assign n595 = n156 | n407;
assign n596 = ~e | ~a | ~c;
assign n597 = d | a;
assign n598 = ~d | e;
assign n599 = ~a | n598;
assign n600 = ~i | j;
assign n601 = ~l | n600;
assign n602 = ~g | ~h;
assign n603 = h | ~i;
assign n604 = ~g | n75;
assign n605 = ~j | n602;
assign n606 = n396 & n397;
assign n607 = n599 & n353;
assign n608 = n92 & n352;
assign n609 = g | ~h;
assign n610 = i & j;
assign n611 = ~j | l;
assign n612 = ~f | n521;
assign n613 = l | n179;
assign n614 = ~g | ~n421;
assign n615 = ~b | ~c;
assign n616 = d | n615;
assign n617 = n590 | n407;
assign n618 = n593 | n594;
assign n619 = n97 & n70 & n210;
assign n620 = (n595 | n287) & (n593 | n218);
assign n621 = i | ~j;
assign n622 = j | ~k;
assign n623 = k & ~n600;
assign n624 = ~k | n249;
assign n625 = ~b | n521;
assign n626 = ~c | ~d;
assign n627 = i | n243;
assign n628 = n614 & n605;
assign n629 = ~g | n621;
assign n630 = k | n167;
assign n631 = h | n459;
assign n632 = e | n626;
assign n633 = n269 | n151;
assign n634 = h | n196;
assign n635 = ~b | n459;
assign n636 = ~l | n412;
assign n637 = n612 & n272;
assign n638 = ~f | n560;
assign n639 = i | n609;
assign n640 = i | n393;
assign n641 = n622 | ~l | n167;
assign n642 = j | n602;
assign n643 = j | n393;
assign n644 = ~j | n154;
assign n645 = n538 | n92;
assign n646 = ~j | n570;
assign n647 = ~m | n360;
assign n648 = (n392 | n127) & (n400 | n391);
assign n649 = ~g | n622;
assign n650 = k | n600;
assign n651 = b | n626;
assign n652 = n621 | ~k | n181;
assign n653 = n222 & ~n526;
assign n654 = a | n615;
assign n655 = ~f | ~d | ~e;
assign n656 = ~n653 | n332 | n426;
assign n657 = n632 | n429;
assign n658 = k | n621;
assign n659 = d | e;
assign n660 = i | ~g | h;
assign n661 = n445 | n435 | n427;
assign n662 = n430 | n202 | n652;
assign n663 = n83 & n471;
assign n664 = ~g | n479;
assign n665 = a | n598;
assign n666 = m | n424;
assign n667 = ~h | n514;
assign n668 = k | n514;
assign n669 = h | n514;
assign n670 = m | n600;
assign n671 = n | n479;
assign n672 = h | n167;
assign n673 = g | n199;
assign n674 = h & ~n650;
assign n675 = e | n479;
assign n676 = h | n488;
assign n677 = n343 & n144 & n454 & n617 & n381 & n380;
assign n678 = (e & ~n119) | (~n92 & (~e | ~n119));
assign n679 = (n479 & n674) | (~g & (~n479 | n674));
assign n680 = n755 & (i | n466 | h);
assign n681 = ~n610 | l | n115;
assign n682 = n590 & n93;
assign n683 = n681 & (n682 | n584);
assign n684 = n642 & n253;
assign n685 = (n684 | n108) & (n109 | n88);
assign n686 = (n605 | n372) & (n604 | n613);
assign n687 = (n614 | n376) & (n88 | n259);
assign n688 = ~n141 & (n82 | (n685 & n686));
assign n689 = n335 & n327;
assign n690 = (n588 | n106) & (n237 | n305);
assign n691 = n229 | n83;
assign n692 = n393 | ~j | n192;
assign n693 = ~a | b | ~d | n198;
assign n694 = (n607 | n165) & (n204 | n625);
assign n695 = (n161 | n627) & (n155 | n135);
assign n696 = n243 | ~j | n237;
assign n697 = (n588 | n136) & (n242 | n592);
assign n698 = n256 | n167;
assign n699 = (n155 | n101) & (n238 | n538);
assign n700 = (n588 | n103) & (n117 | n126);
assign n701 = (n182 | n612) & (n241 | n92);
assign n702 = ~n294 & (~n585 | (l & n610));
assign n703 = ~n95 & (~n252 | ~n254 | ~n256);
assign n704 = (n84 | n88) & (n642 | n435);
assign n705 = (n167 | ~n702) & (n259 | ~n703);
assign n706 = n490 & (n96 | n611);
assign n707 = n354 | n360 | n167 | n105;
assign n708 = ~h | j;
assign n709 = (n113 | n643) & (~n678 | n708);
assign n710 = (n95 | n88) & (j | n645);
assign n711 = (n110 | n157) & (n113 | n276);
assign n712 = n167 | n127 | n584 | n423;
assign n713 = (d | n525) & (j | n436);
assign n714 = (b | c) & (n127 | n433);
assign n715 = (n253 | n463) & (n103 | ~n473);
assign n716 = n676 & n478;
assign n717 = a | b;
assign n718 = n433 | n487 | ~h | n199;
assign n719 = n496 & ~n534;
assign n720 = n478 & n665 & n432;
assign n721 = ~n523 & (g | n520 | n720);
assign n722 = n721 & (n670 | (n496 & n480));
assign n723 = (n522 | n669) & (n164 | n666);
assign n724 = n723 & (n668 | (n202 & n664));
assign n725 = n231 | n156 | n401;
assign n726 = n592 | n432;
assign n727 = n725 & n726 & (n719 | n667);
assign n728 = n518 & n727 & (n496 | n515);
assign n729 = (n436 | n667) & (n525 | n528);
assign n730 = n729 & (n515 | n436);
assign n731 = (n669 | n397) & (n525 | n668);
assign n732 = n526 | e | n472;
assign n733 = n672 | ~n597 | n636;
assign n734 = n754 & (~h | n438);
assign n735 = n732 & n733 & (~c | n734);
assign n736 = n | a | ~g;
assign n737 = (i | n665) & (~n545 | n659);
assign n738 = ~n468 & (n311 | ~n403 | n736);
assign n739 = n738 & (n665 | (n672 & n96));
assign n740 = (n549 | n673) & (n179 | ~n679);
assign n741 = n489 & (e | n254);
assign n742 = ~n629 | k | n206;
assign n743 = ~n546 & (n537 | n554);
assign n744 = n743 & (n199 | (n714 & n713));
assign n745 = (n720 | n376) & (n533 | n167);
assign n746 = (n192 | n327) & (~i | n503);
assign n747 = n745 & n746 & (n591 | n445);
assign n748 = ~h & (n559 | (~n601 & ~n673));
assign n749 = (n588 | n202) & (n237 | n646);
assign n750 = n53 & n47 & n618;
assign n751 = n526 | n102 | n120;
assign n752 = n751 & (n651 | (n104 & n195));
assign n753 = n449 | n480;
assign n754 = ~n473 | h | n179;
assign n755 = n467 | ~h | n375;
assign n756 = i & ~k & (~n376 | ~n613);
assign n757 = (n495 & (~h | n511)) | (h & n511);
assign n758 = ~h & (~n96 | (c & ~n457));
assign n759 = (n464 & (~g | n486)) | (g & n486);
assign n760 = l | n368;
assign n761 = n760 & n512 & n527;
assign n762 = n674 & ~n167 & n460;
endmodule

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// Benchmark "s298.bench" written by ABC on Tue Mar 5 10:03:54 2019
module s298 ( clock,
G0, G1, G2,
G117, G132, G66, G118, G133, G67 );
input G0, G1, G2, clock;
output G117, G132, G66, G118, G133, G67;
reg G10, G11, G12, G13, G14, G15, G16, G17, G18, G19, G20, G21, G22, G23;
wire n57, n59, n64, n66, n21_1, n26_1, n31_1, n36_1, n41_1, n46_1, n51_1,
n56_1, n61_1, n66_2, n71_1, n76_1, n81_1, n86_1;
assign n21_1 = ~G0 & ~G10;
assign n26_1 = ~G0 & (G10 ? (~G11 & (G12 | ~G13)) : G11);
assign n31_1 = ~G0 & ((G12 & (~G10 | ~G11)) | (G10 & G11 & ~G12));
assign n36_1 = ~G0 & ((G11 & ((~G12 & G13) | (G10 & G12 & ~G13))) | (G13 & (~G10 | (~G11 & G12))));
assign n41_1 = ~G0 & (G14 ^ (G23 | (G10 & G13 & n57)));
assign n57 = ~G11 & ~G12;
assign n46_1 = ~G0 & ~n59;
assign n59 = (G11 & (~G15 | (~G12 & G13 & ~G14 & ~G22))) | (~G15 & (G12 | ~G13 | G14 | ~G22));
assign n51_1 = n59 & ((G13 & (~G14 | G16)) | (G12 & G14 & G16));
assign n56_1 = n59 & ((~G13 & (G11 ? ~G12 : ~G14)) | (G14 & G17 & (G12 | G13)));
assign n61_1 = n59 & ((G14 & G18 & (G12 | G13)) | (~G13 & (~G14 | (G11 & ~G12))));
assign n66_2 = n59 ? n64 : ~G10;
assign n64 = (G13 & (~G14 | G19)) | (G14 & ((~G11 & ~G12 & ~G13) | (G12 & G19)));
assign n71_1 = n59 ? (n66 & (G20 | (~G12 & ~G13))) : ~G10;
assign n66 = G14 & (~G11 | G12 | G13);
assign n76_1 = n59 & ((G12 & ((G11 & ~G13 & ~G14) | (G14 & G21))) | (G13 & G14 & G21));
assign n81_1 = ~G0 & (G2 ^ G22);
assign n86_1 = ~G0 & (G1 ^ G23);
assign G117 = G18;
assign G132 = G20;
assign G66 = G16;
assign G118 = G19;
assign G133 = G21;
assign G67 = G17;
always @ (posedge clock) begin
G10 <= n21_1;
G11 <= n26_1;
G12 <= n31_1;
G13 <= n36_1;
G14 <= n41_1;
G15 <= n46_1;
G16 <= n51_1;
G17 <= n56_1;
G18 <= n61_1;
G19 <= n66_2;
G20 <= n71_1;
G21 <= n76_1;
G22 <= n81_1;
G23 <= n86_1;
end
initial begin
G10 <= 1'b0;
G11 <= 1'b0;
G12 <= 1'b0;
G13 <= 1'b0;
G14 <= 1'b0;
G15 <= 1'b0;
G16 <= 1'b0;
G17 <= 1'b0;
G18 <= 1'b0;
G19 <= 1'b0;
G20 <= 1'b0;
G21 <= 1'b0;
G22 <= 1'b0;
G23 <= 1'b0;
end
endmodule

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i_0_ 0.507200 0.496600
i_1_ 0.506400 0.501400
i_2_ 0.497600 0.493200
i_3_ 0.503800 0.496600
i_4_ 0.499400 0.493000
i_5_ 0.498600 0.493600
i_6_ 0.492000 0.500800
i_7_ 0.487800 0.500000
i_8_ 0.501800 0.499000
i_9_ 0.497000 0.485000
i_10_ 0.504400 0.496800
i_11_ 0.500000 0.509800
i_12_ 0.493800 0.498400
i_13_ 0.510600 0.493800
o_0_ 0.577000 0.077506
n26 0.244400 0.093513
n27 0.500400 0.124004
n28 0.254600 0.047930
n29 0.250000 0.047867
n30 0.255400 0.091568
n31 0.250000 0.092368
o_1_ 0.500400 0.069873
n33 0.238400 0.089851
n34 0.249800 0.092215
n35 0.255000 0.093733
n36 0.249800 0.095452
n37 0.556200 0.095165
n38 0.403200 0.012210
n39 0.584600 0.062239
n40 0.262200 0.012861
n41 0.115800 0.171124
n42 0.130400 0.028422
n43 0.752200 0.034713
n44 0.724000 0.037365
n45 0.601000 0.024813
n46 0.143000 0.010267
n47 0.877200 0.010296
n48 0.248000 0.091201
n49 0.120800 0.027593
n50 0.247600 0.091740
n51 0.271600 0.150050
n52 0.269800 0.009377
n53 0.243800 0.092109
n54 0.124200 0.027951
n55 0.365400 0.170839
n56 0.262000 0.094371
n57 0.131200 0.028875
n58 0.922200 0.000356
n59 0.030400 0.001891
n60 0.123000 0.027067
n61 0.498000 0.093083
n62 0.032000 0.002001
n63 0.865800 0.000135
n64 0.061600 0.008662
n65 0.758400 0.046641
n66 0.065400 0.003573
n67 0.189200 0.032110
n68 0.074400 0.007264
n69 0.853000 0.021911
n70 0.123200 0.027710
n71 0.485800 0.048827
n72 0.036200 0.098032
n73 0.254400 0.088467
n74 0.029400 0.001820
n75 0.919200 0.004880
n76 0.053200 0.001600
n77 0.060200 0.003685
n78 0.939800 0.003588
n79 0.016800 0.000456
n80 0.181400 0.102631
n81 0.831000 0.000179
n82 0.239000 0.087621
n83 0.752600 0.023589
n84 0.035600 0.000252
n85 0.104000 0.009532
n86 0.974000 0.006689
n87 0.059600 0.007073
n88 0.125600 0.028479
n89 0.026800 0.005350
n90 0.843800 0.008255
n91 0.121400 0.026749
n92 0.133600 0.028186
n93 0.118400 0.027428
n94 0.249000 0.095561
n95 0.011400 0.274997
n96 0.245600 0.096233
n97 0.015600 0.000441
n98 0.764400 0.030492
n99 0.124000 0.026156
n100 0.013800 0.000142
n101 0.259200 0.092453
n102 0.761600 0.031276
n103 0.256600 0.095668
n104 0.127800 0.027847
n105 0.248200 0.092109
n106 0.926600 0.000447
n107 0.061400 0.006883
n108 0.125600 0.026902
n109 0.049600 0.002378
n110 0.125800 0.025851
n111 0.132000 0.025796
n112 0.117400 0.025304
n113 0.243000 0.090668
n114 0.954000 0.000523
n115 0.029600 0.001893
n116 0.046200 0.000537
n117 0.870200 0.013837
n118 0.972800 0.002734
n119 0.021600 0.168817
n120 0.693600 0.019730
n121 0.059000 0.007010
n122 0.894800 0.009692
n123 0.249800 0.090699
n124 0.230000 0.091866
n125 0.008200 0.000048
n126 0.028400 0.001814
n127 0.030000 0.001791
n128 0.249200 0.090461
n129 0.246400 0.089906
n130 0.005800 0.000000
n131 0.123800 0.026488
n132 0.844800 0.001778
n133 0.013600 0.000463
n134 0.975400 0.022212
n135 0.012000 0.000465
n136 0.032400 0.001740
n137 0.013400 0.000483
n138 0.010400 0.000524
n139 0.250600 0.096640
n140 0.253200 0.093930
n141 0.156000 0.027293
n142 0.013400 0.000451
n143 0.017600 0.000499
n144 0.009200 0.000005
n145 0.009200 0.222476
n146 0.012600 0.000443
n147 0.115600 0.026365
n148 0.682200 0.142413
n149 0.169400 0.000048
n150 0.660800 0.002077
n151 0.248800 0.094647
n152 0.278000 0.117457
n153 0.013200 0.000495
n154 0.130000 0.026721
n155 0.258000 0.093998
n156 0.775600 0.032205
n157 0.035400 0.056403
n158 0.121600 0.025516
n159 0.251800 0.096842
n160 0.057200 0.007075
n161 0.016000 0.000451
n162 0.021600 0.165889
n163 0.037000 0.000004
n164 0.849200 0.000008
n165 0.042000 0.076864
n166 0.075600 0.175072
n167 0.249400 0.093538
n168 0.255400 0.092782
n169 0.123600 0.026761
n170 0.017800 0.128969
n171 0.130800 0.025177
n172 0.886000 0.009532
n173 0.976600 0.017711
n174 0.895000 0.008650
n175 0.012400 0.001407
n176 0.246400 0.090668
n177 0.285600 0.012522
n178 0.395200 0.030715
n179 0.016200 0.000487
n180 0.859200 0.148776
n181 0.014200 0.000470
n182 0.259400 0.088136
n183 0.071000 0.007397
n184 0.696600 0.093048
n185 0.046200 0.002075
n186 0.920200 0.000007
n187 0.063000 0.057916
n188 0.028800 0.013875
n189 0.970600 0.000859
n190 0.937000 0.003505
n191 0.872000 0.091162
n192 0.066400 0.009362
n193 0.934400 0.010902
n194 0.641000 0.091467
n195 0.904800 0.028943
n196 0.783800 0.029159
n197 0.790000 0.055221
n198 0.840000 0.024270
n199 0.229800 0.033381
n200 0.906400 0.016808
n201 0.312000 0.002321
n202 0.852200 0.093593
n203 0.820400 0.145265
n204 0.903000 0.000927
n205 0.900600 0.009143
n206 0.921400 0.031099
n207 0.125000 0.025885
n208 0.105600 0.010699
n209 0.022600 0.005495
n210 0.969600 0.027547
n211 0.254800 0.093022
n212 0.345600 0.023938
n213 0.661000 0.004096
n214 0.016000 0.000289
n215 0.061600 0.008226
n216 0.251800 0.096233
n217 0.753800 0.016062
n218 0.727400 0.095865
n219 0.112600 0.184403
n220 0.022200 0.029346
n221 0.105400 0.000041
n222 0.190200 0.064251
n223 0.037800 0.002414
n224 0.851000 0.004439
n225 0.677600 0.003756
n226 0.023600 0.001085
n227 0.129600 0.029253
n228 0.012800 0.000019
n229 0.034000 0.036995
n230 0.129200 0.026492
n231 0.037000 0.000119
n232 0.009000 0.000226
n233 0.012600 0.009536
n234 0.922400 0.000458
n235 0.943400 0.086745
n236 0.049400 0.000454
n237 0.013600 0.000453
n238 0.030200 0.001828
n239 0.014200 0.004049
n240 0.498600 0.003736
n241 0.018800 0.010133
n242 0.020600 0.000541
n243 0.117400 0.027569
n244 0.125800 0.027392
n245 0.950000 0.001390
n246 0.017400 0.000497
n247 0.951600 0.001381
n248 0.002000 0.000016
n249 0.992400 0.026955
n250 0.126600 0.027428
n251 0.127600 0.029646
n252 0.015000 0.000487
n253 0.018000 0.000425
n254 0.006800 0.000118
n255 0.126200 0.025692
n256 0.005200 0.000029
n257 0.122600 0.026156
n258 0.001600 0.000002
n259 0.123400 0.027569
n260 0.053000 0.006742
n261 0.131000 0.026156
n262 0.129200 0.029253
n263 0.035000 0.000872
n264 0.051200 0.002442
n265 0.045400 0.003988
n266 0.246800 0.091866
n267 0.983200 0.000000
n268 0.016600 0.000233
n269 0.123400 0.028069
n270 0.064600 0.007073
n271 0.912000 0.006231
n272 0.012200 0.000162
n273 0.003200 0.000029
n274 0.925600 0.028384
n275 0.030800 0.002138
n276 0.121400 0.027550
n277 0.014400 0.000455
n278 0.251400 0.092392
n279 0.030800 0.001886
n280 0.992600 0.000044
n281 0.012400 0.000000
n282 0.017000 0.000517
n283 0.877400 0.059738
n284 0.121200 0.029253
n285 0.952800 0.001476
n286 0.003400 0.000721
n287 0.986200 0.027652
n288 0.065600 0.007314
n289 0.013400 0.000446
n290 0.934000 0.062027
n291 0.738200 0.147156
n292 0.992600 0.044684
n293 0.036200 0.002105
n294 0.031600 0.001876
n295 0.128200 0.026813
n296 0.013000 0.000487
n297 0.922800 0.002099
n298 0.610200 0.023513
n299 0.949200 0.028723
n300 0.984800 0.003947
n301 0.063000 0.007268
n302 0.957400 0.001338
n303 0.988000 0.004227
n304 0.063600 0.006975
n305 0.875600 0.010050
n306 0.008600 0.001044
n307 0.001800 0.004268
n308 0.985000 0.024177
n309 0.122000 0.026706
n310 0.061600 0.007346
n311 0.016200 0.000460
n312 0.127800 0.014131
n313 0.035800 0.002065
n314 0.001000 0.000017
n315 0.001200 0.000002
n316 0.001000 0.000001
n317 0.014000 0.000507
n318 0.003800 0.000029
n319 0.890400 0.009678
n320 0.962600 0.000001
n321 0.253600 0.090668
n322 0.030800 0.002077
n323 0.123400 0.027838
n324 0.133000 0.027838
n325 0.005400 0.000034
n326 0.002600 0.000009
n327 0.034400 0.001873
n328 0.992800 0.000057
n329 0.007200 0.000000
n330 0.006200 0.000050
n331 0.001800 0.000072
n332 0.001600 0.028311
n333 0.991600 0.049013
n334 0.994000 0.023346
n335 0.993200 0.000023
n336 0.990400 0.024989
n337 0.001400 0.000004
n338 0.014200 0.061698
n339 0.729000 0.037530
n340 0.910600 0.084521
n341 0.641200 0.013178
o_3_ 0.505400 0.099316
n343 0.328200 0.024360
n344 0.959800 0.003228
n345 0.373000 0.023259
n346 0.945800 0.000003
n347 0.051000 0.006230
n348 0.765800 0.137143
n349 0.033200 0.000847
n350 0.402000 0.011652
n351 0.436400 0.024182
n352 0.013400 0.007911
n353 0.222000 0.015781
n354 0.992200 0.000052
n355 0.936000 0.000087
n356 0.132600 0.085254
n357 0.145400 0.033973
n358 0.011000 0.000156
n359 0.063000 0.007116
n360 0.253000 0.015271
n361 0.294800 0.023465
n362 0.027200 0.006307
n363 0.312200 0.023937
n364 0.345800 0.017249
n365 0.833400 0.051311
n366 0.825400 0.034122
n367 0.223000 0.042498
n368 0.965200 0.001881
n369 0.014800 0.000445
n370 0.989000 0.239725
n371 0.120400 0.009204
n372 0.978800 0.000544
n373 0.652400 0.031285
n374 0.636400 0.152149
n375 0.931200 0.002467
n376 0.785200 0.137981
n377 0.415200 0.097289
n378 0.807600 0.030338
o_6_ 0.496800 0.138220
n380 0.516600 0.079201
n381 0.779000 0.000037
o_5_ 0.493000 0.128897
n383 0.155000 0.001954
n384 0.518600 0.039542
n385 0.624800 0.070955
n386 0.269400 0.164373
n387 0.143600 0.014543
n388 0.120200 0.098574
n389 0.941000 0.068389
n390 0.977600 0.088518
n391 0.861400 0.005270
n392 0.143600 0.026406
n393 0.811400 0.000941
n394 0.287400 0.057846
n395 0.985400 0.016065
o_7_ 0.133200 0.268048
n397 0.818400 0.000280
n398 0.973400 0.158761
n399 0.382000 0.045447
n400 0.949800 0.047076
n401 0.031400 0.002013
n402 0.018800 0.000245
n403 0.023800 0.000712
n404 0.930600 0.204221
n405 0.363400 0.040311
n406 0.009200 0.006631
n407 0.002800 0.000249
n408 0.073800 0.008696
n409 0.996400 0.000020
n410 0.010800 0.017350
n411 0.009600 0.007951
n412 0.008000 0.000017
n413 0.651200 0.036093
n414 0.984400 0.030970
n415 0.011800 0.000155
n416 0.581200 0.026865
n417 0.623000 0.027332
n418 0.016800 0.021673
n419 0.982600 0.000425
n420 0.957600 0.045049
n421 0.996600 0.002363
n422 0.991400 0.006621
n423 0.503000 0.090886
n424 0.002200 0.075540
n425 0.992000 0.166252
n426 0.982200 0.000305
n427 0.664600 0.000799
n428 0.700000 0.021303
o_2_ 0.583600 0.023724
n430 0.107200 0.003705
n431 0.946400 0.019926
n432 0.877600 0.000360
n433 0.987200 0.003971
n434 0.836800 0.005233
o_4_ 0.507000 0.223870
n436 0.046800 0.002377
n437 0.029000 0.112624
n438 0.963600 0.016971
n439 0.221000 0.068298
n440 0.097000 0.036002
n441 0.938400 0.000715
n442 0.909200 0.040030
n443 0.946000 0.001650
n444 0.833200 0.004141
n445 0.915400 0.000387
n446 0.577400 0.219264
n447 0.268200 0.172298
n448 0.280400 0.027999
n449 0.316800 0.052897
n450 0.926000 0.023917
n451 0.111200 0.011004
n452 0.071000 0.005452
n453 0.125400 0.077442
n454 0.182800 0.156557
n455 0.938000 0.000153
n456 0.078800 0.000481
n457 0.998000 0.000135
n458 0.938800 0.000000
n459 0.992000 0.000072
n460 0.998000 0.003630
n461 0.983800 0.120489
n462 0.998000 0.191415
n463 0.968000 0.000008

1360
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/* Generated by Yosys 0.8+133 (git sha1 2a2e0a4, gcc 7.3.0 -fPIC -Os) */
module alu4(i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_, i_11_, i_12_, i_13_, o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_);
input i_0_;
input i_10_;
input i_11_;
input i_12_;
input i_13_;
input i_1_;
input i_2_;
input i_3_;
input i_4_;
input i_5_;
input i_6_;
input i_7_;
input i_8_;
input i_9_;
wire n100;
wire n101;
wire n102;
wire n103;
wire n104;
wire n105;
wire n106;
wire n107;
wire n108;
wire n109;
wire n110;
wire n111;
wire n112;
wire n113;
wire n114;
wire n115;
wire n116;
wire n117;
wire n118;
wire n119;
wire n120;
wire n121;
wire n122;
wire n123;
wire n124;
wire n125;
wire n126;
wire n127;
wire n128;
wire n129;
wire n130;
wire n131;
wire n132;
wire n133;
wire n134;
wire n135;
wire n136;
wire n137;
wire n138;
wire n139;
wire n140;
wire n141;
wire n142;
wire n143;
wire n144;
wire n145;
wire n146;
wire n147;
wire n148;
wire n149;
wire n150;
wire n151;
wire n152;
wire n153;
wire n154;
wire n155;
wire n156;
wire n157;
wire n158;
wire n159;
wire n160;
wire n161;
wire n162;
wire n163;
wire n164;
wire n165;
wire n166;
wire n167;
wire n168;
wire n169;
wire n170;
wire n171;
wire n172;
wire n173;
wire n174;
wire n175;
wire n176;
wire n177;
wire n178;
wire n179;
wire n180;
wire n181;
wire n182;
wire n183;
wire n184;
wire n185;
wire n186;
wire n187;
wire n188;
wire n189;
wire n190;
wire n191;
wire n192;
wire n193;
wire n194;
wire n195;
wire n196;
wire n197;
wire n198;
wire n199;
wire n200;
wire n201;
wire n202;
wire n203;
wire n204;
wire n205;
wire n206;
wire n207;
wire n208;
wire n209;
wire n210;
wire n211;
wire n212;
wire n213;
wire n214;
wire n215;
wire n216;
wire n217;
wire n218;
wire n219;
wire n220;
wire n221;
wire n222;
wire n223;
wire n224;
wire n225;
wire n226;
wire n227;
wire n228;
wire n229;
wire n230;
wire n231;
wire n232;
wire n233;
wire n234;
wire n235;
wire n236;
wire n237;
wire n238;
wire n239;
wire n240;
wire n241;
wire n242;
wire n243;
wire n244;
wire n245;
wire n246;
wire n247;
wire n248;
wire n249;
wire n250;
wire n251;
wire n252;
wire n253;
wire n254;
wire n255;
wire n256;
wire n257;
wire n258;
wire n259;
wire n26;
wire n260;
wire n261;
wire n262;
wire n263;
wire n264;
wire n265;
wire n266;
wire n267;
wire n268;
wire n269;
wire n27;
wire n270;
wire n271;
wire n272;
wire n273;
wire n274;
wire n275;
wire n276;
wire n277;
wire n278;
wire n279;
wire n28;
wire n280;
wire n281;
wire n282;
wire n283;
wire n284;
wire n285;
wire n286;
wire n287;
wire n288;
wire n289;
wire n29;
wire n290;
wire n291;
wire n292;
wire n293;
wire n294;
wire n295;
wire n296;
wire n297;
wire n298;
wire n299;
wire n30;
wire n300;
wire n301;
wire n302;
wire n303;
wire n304;
wire n305;
wire n306;
wire n307;
wire n308;
wire n309;
wire n31;
wire n310;
wire n311;
wire n312;
wire n313;
wire n314;
wire n315;
wire n316;
wire n317;
wire n318;
wire n319;
wire n320;
wire n321;
wire n322;
wire n323;
wire n324;
wire n325;
wire n326;
wire n327;
wire n328;
wire n329;
wire n33;
wire n330;
wire n331;
wire n332;
wire n333;
wire n334;
wire n335;
wire n336;
wire n337;
wire n338;
wire n339;
wire n34;
wire n340;
wire n341;
wire n343;
wire n344;
wire n345;
wire n346;
wire n347;
wire n348;
wire n349;
wire n35;
wire n350;
wire n351;
wire n352;
wire n353;
wire n354;
wire n355;
wire n356;
wire n357;
wire n358;
wire n359;
wire n36;
wire n360;
wire n361;
wire n362;
wire n363;
wire n364;
wire n365;
wire n366;
wire n367;
wire n368;
wire n369;
wire n37;
wire n370;
wire n371;
wire n372;
wire n373;
wire n374;
wire n375;
wire n376;
wire n377;
wire n378;
wire n38;
wire n380;
wire n381;
wire n383;
wire n384;
wire n385;
wire n386;
wire n387;
wire n388;
wire n389;
wire n39;
wire n390;
wire n391;
wire n392;
wire n393;
wire n394;
wire n395;
wire n397;
wire n398;
wire n399;
wire n40;
wire n400;
wire n401;
wire n402;
wire n403;
wire n404;
wire n405;
wire n406;
wire n407;
wire n408;
wire n409;
wire n41;
wire n410;
wire n411;
wire n412;
wire n413;
wire n414;
wire n415;
wire n416;
wire n417;
wire n418;
wire n419;
wire n42;
wire n420;
wire n421;
wire n422;
wire n423;
wire n424;
wire n425;
wire n426;
wire n427;
wire n428;
wire n43;
wire n430;
wire n431;
wire n432;
wire n433;
wire n434;
wire n436;
wire n437;
wire n438;
wire n439;
wire n44;
wire n440;
wire n441;
wire n442;
wire n443;
wire n444;
wire n445;
wire n446;
wire n447;
wire n448;
wire n449;
wire n45;
wire n450;
wire n451;
wire n452;
wire n453;
wire n454;
wire n455;
wire n456;
wire n457;
wire n458;
wire n459;
wire n46;
wire n460;
wire n461;
wire n462;
wire n463;
wire n47;
wire n48;
wire n49;
wire n50;
wire n51;
wire n52;
wire n53;
wire n54;
wire n55;
wire n56;
wire n57;
wire n58;
wire n59;
wire n60;
wire n61;
wire n62;
wire n63;
wire n64;
wire n65;
wire n66;
wire n67;
wire n68;
wire n69;
wire n70;
wire n71;
wire n72;
wire n73;
wire n74;
wire n75;
wire n76;
wire n77;
wire n78;
wire n79;
wire n80;
wire n81;
wire n82;
wire n83;
wire n84;
wire n85;
wire n86;
wire n87;
wire n88;
wire n89;
wire n90;
wire n91;
wire n92;
wire n93;
wire n94;
wire n95;
wire n96;
wire n97;
wire n98;
wire n99;
output o_0_;
output o_1_;
output o_2_;
output o_3_;
output o_4_;
output o_5_;
output o_6_;
output o_7_;
assign o_0_ = 64'hfffefffefffefefe >> { n30, n31, i_3_, n28, n29, n26 };
assign n34 = 4'h8 >> { i_8_, i_12_ };
assign n124 = 4'h2 >> { i_13_, i_12_ };
assign n125 = 8'ha8 >> { n127, n126, n49 };
assign n126 = 32'd128 >> { i_3_, i_13_, i_5_, i_4_, i_12_ };
assign n127 = 32'd8 >> { i_3_, i_5_, i_13_, i_4_, i_11_ };
assign n128 = 4'h8 >> { i_8_, i_7_ };
assign n129 = 4'h8 >> { i_9_, i_12_ };
assign n130 = 64'h0800080008080800 >> { n132, n131, n133, i_5_, i_6_, i_8_ };
assign n131 = 8'h02 >> { i_9_, i_13_, i_11_ };
assign n132 = 32'd4025479150 >> { i_3_, i_12_, i_4_, i_2_, i_0_ };
assign n133 = 64'h0000000000008000 >> { i_0_, i_11_, i_2_, i_3_, i_12_, i_9_ };
assign n35 = 4'h2 >> { i_8_, i_11_ };
assign n134 = 64'h0015151515151515 >> { i_9_, n42, n91, n67, n136, n135 };
assign n135 = 64'h0000000000000080 >> { i_10_, i_9_, i_13_, i_5_, i_4_, i_12_ };
assign n136 = 32'd8 >> { i_10_, i_13_, i_12_, i_7_, i_11_ };
assign n137 = 64'h0000000000000080 >> { i_8_, i_0_, i_12_, i_2_, i_1_, i_11_ };
assign n138 = 64'h0000008000080088 >> { i_11_, i_12_, i_3_, i_8_, n99, n139 };
assign n139 = 4'h1 >> { i_9_, i_13_ };
assign n140 = 4'h8 >> { i_9_, i_1_ };
assign n141 = 32'd2290122880 >> { i_8_, i_3_, i_7_, i_2_, i_0_ };
assign n142 = 64'h0000000000000002 >> { i_2_, i_1_, i_0_, i_13_, i_11_, i_12_ };
assign n143 = 64'h0000000000000080 >> { i_0_, i_4_, i_12_, i_1_, i_3_, i_11_ };
assign n36 = 4'h1 >> { i_6_, i_5_ };
assign n144 = 32'd269488400 >> { i_9_, n87, n142, i_8_, i_3_ };
assign n145 = 32'd2290657416 >> { i_0_, i_2_, n88, n146, n101 };
assign n146 = 64'h0000000000000008 >> { i_3_, i_10_, i_0_, i_13_, i_4_, i_12_ };
assign n147 = 8'h02 >> { i_10_, i_13_, i_12_ };
assign n148 = 8'h15 >> { i_12_, n71, n99 };
assign n149 = 64'h4544454455554544 >> { n156, n154, n155, n150, n152, i_0_ };
assign n150 = 32'd1162151237 >> { i_8_, i_3_, n151, i_7_, n56 };
assign n151 = 4'h8 >> { i_2_, i_1_ };
assign n152 = 64'he4e4e4e4e4e4e4e6 >> { i_11_, i_6_, i_1_, n153, i_13_, i_12_ };
assign n153 = 64'h0000000000000001 >> { i_10_, i_6_, i_7_, i_2_, i_13_, i_11_ };
assign n37 = 16'hdd0d >> { i_5_, i_1_, i_6_, i_0_ };
assign n154 = 8'h01 >> { i_8_, i_6_, i_7_ };
assign n155 = 4'h2 >> { i_12_, i_10_ };
assign n156 = 64'hbfff9dddafafafad >> { i_4_, i_13_, i_3_, i_11_, i_10_, i_12_ };
assign n157 = 32'd134785544 >> { i_1_, i_6_, i_2_, n54, n108 };
assign n158 = 8'h80 >> { i_8_, i_6_, i_7_ };
assign n159 = 4'h8 >> { i_3_, i_1_ };
assign n160 = 16'h0008 >> { i_9_, i_13_, i_4_, i_11_ };
assign n161 = 64'h0000000000000002 >> { i_2_, i_1_, i_0_, i_13_, i_12_, i_11_ };
assign n162 = 32'd2829626024 >> { n61, n60, n59, n62, n113 };
assign n163 = 32'd1145328708 >> { i_9_, n108, n50, n160, i_10_ };
assign n38 = 64'h4555055544550455 >> { i_7_, n37, i_3_, i_2_, n39, i_12_ };
assign n164 = 64'h0002000000020002 >> { n93, n90, n170, n165, n166, n173 };
assign n165 = 32'd134776840 >> { i_8_, i_3_, i_7_, i_10_, n42 };
assign n166 = 32'd2155915904 >> { i_6_, n168, n167, n169, i_1_ };
assign n167 = 4'h8 >> { i_3_, i_2_ };
assign n168 = 4'h2 >> { i_11_, i_10_ };
assign n169 = 8'h02 >> { i_8_, i_11_, i_10_ };
assign n170 = 32'd1426326532 >> { n171, i_8_, i_10_, n33, n172 };
assign n171 = 8'h01 >> { i_10_, i_13_, i_12_ };
assign n172 = 64'hfffdfffdfffddddd >> { i_7_, i_1_, i_6_, i_2_, i_3_, i_0_ };
assign n173 = 64'h0ddddddddddddddd >> { n92, i_6_, i_2_, i_12_, n174, n160 };
assign n39 = 4'h1 >> { n36, n40 };
assign n174 = 64'hffefffefeeeeffef >> { i_1_, i_8_, i_3_, i_6_, i_2_, i_0_ };
assign n175 = 64'h0000000800080008 >> { i_12_, i_8_, i_3_, i_6_, n73, n176 };
assign n176 = 4'h1 >> { i_13_, i_11_ };
assign n177 = 64'h0001000100010000 >> { i_4_, n180, n179, n153, i_5_, n178 };
assign n178 = 64'haa20aa24aa21aa25 >> { i_11_, i_12_, i_13_, i_1_, i_6_, i_10_ };
assign n179 = 64'h0000000000000002 >> { i_10_, i_8_, i_6_, i_7_, i_13_, i_4_ };
assign n180 = 64'h7f7f7f7f7f7f7f77 >> { i_7_, i_8_, i_6_, i_12_, i_10_, i_11_ };
assign n181 = 64'h0000000000000008 >> { i_8_, i_9_, i_13_, i_11_, i_6_, i_7_ };
assign n182 = 4'h1 >> { i_13_, i_12_ };
assign n183 = 64'h8080008000800080 >> { i_8_, i_3_, i_4_, i_9_, i_12_, i_11_ };
assign n40 = 32'd1079002196 >> { i_5_, i_6_, i_0_, i_1_, i_7_ };
assign n184 = 32'd2012686247 >> { i_13_, i_3_, i_4_, i_12_, i_9_ };
assign n185 = 64'h8000800080000000 >> { i_11_, i_6_, i_7_, i_2_, i_12_, i_9_ };
assign n186 = 32'd1431655764 >> { i_2_, i_13_, n65, i_9_, n187 };
assign n187 = 8'h02 >> { i_10_, i_9_, n33 };
assign n188 = 32'd1360072977 >> { i_5_, n111, i_6_, n189, i_1_ };
assign n189 = 64'hfffffffd7fff7ffd >> { i_9_, i_10_, i_8_, i_7_, i_5_, n33 };
assign n190 = 64'hfffffffeff7fff7e >> { i_9_, i_10_, i_13_, i_7_, i_5_, i_6_ };
assign n191 = 32'd2004309879 >> { i_11_, n67, n182, i_10_, n140 };
assign n192 = 32'd1 >> { n34, n35, i_10_, i_9_, i_13_ };
assign n193 = 64'h7ff7fff77fffffff >> { i_11_, i_12_, i_6_, i_7_, i_10_, i_9_ };
assign n41 = 32'd2863311522 >> { i_3_, n34, n35, n27, n42 };
assign n194 = 64'h8088828a828a828a >> { i_3_, n31, n70, i_13_, i_11_, n195 };
assign n195 = 32'd2004317959 >> { i_4_, i_11_, n34, n108, n50 };
assign n196 = 64'heeffeef5e6f7e6f5 >> { i_10_, i_3_, i_11_, i_13_, i_4_, i_12_ };
assign n197 = 64'hffef0000ffe70000 >> { i_13_, n198, i_2_, i_3_, i_4_, i_11_ };
assign n198 = 64'hffbfffbfdd9dffbf >> { n70, i_3_, n31, n33, i_11_, i_10_ };
assign n199 = 64'hfd00fd00fd00ff00 >> { i_7_, n200, i_2_, n201, n187, n202 };
assign n200 = 64'heeeeeeefeefeeeff >> { n182, n176, n33, i_8_, i_10_, i_3_ };
assign n201 = 32'd286331152 >> { i_13_, n35, n34, n33, n27 };
assign n202 = 64'h7f7f7f7f7f7f7f7e >> { i_13_, i_12_, i_11_, i_3_, i_10_, i_9_ };
assign n203 = 64'h0080a2a200a2a2a2 >> { n53, n124, n70, n204, i_2_, n205 };
assign n42 = 8'h80 >> { i_2_, i_1_, i_0_ };
assign n204 = 64'hddffdddfddfddddd >> { i_11_, i_12_, i_4_, i_8_, i_3_, n139 };
assign n205 = 64'hfffdfffd7f7dfffd >> { i_13_, i_8_, i_12_, i_2_, i_4_, i_3_ };
assign n206 = 32'd2004289399 >> { i_12_, i_3_, n207, n105, n26 };
assign n207 = 8'h80 >> { i_8_, i_9_, i_7_ };
assign n208 = 16'h5515 >> { n77, n78, n81, i_13_ };
assign n209 = 32'd526344 >> { i_12_, i_8_, i_6_, n73, n176 };
assign n210 = 8'h15 >> { n111, n158, n181 };
assign n211 = 4'h8 >> { i_10_, i_9_ };
assign n212 = 64'hfa50fa50c800c040 >> { i_13_, i_7_, i_9_, i_10_, i_2_, i_6_ };
assign n213 = 32'd33685506 >> { n217, n216, n214, n215, n218 };
assign n43 = 32'd1467441023 >> { i_1_, i_0_, i_6_, i_5_, i_2_ };
assign n214 = 64'h0800080008000808 >> { i_3_, i_11_, i_4_, i_8_, n73, n124 };
assign n215 = 8'h08 >> { i_7_, n155, i_2_ };
assign n216 = 4'h2 >> { i_12_, i_11_ };
assign n217 = 64'hfdd0fdddffd0ffdd >> { i_10_, i_2_, i_4_, i_8_, i_7_, i_3_ };
assign n218 = 32'd3149642681 >> { i_7_, i_2_, i_11_, i_13_, i_12_ };
assign n219 = 4'h2 >> { i_11_, n124 };
assign n220 = 64'haa08aa00aa08aa08 >> { i_2_, n73, n74, i_1_, n53, n124 };
assign n221 = 64'h5454545455545454 >> { i_4_, n227, n216, n226, n222, i_1_ };
assign n222 = 32'd1157973317 >> { n224, n223, n225, i_7_, i_6_ };
assign n223 = 32'd2155905160 >> { i_3_, i_12_, i_4_, n131, i_8_ };
assign n26 = 4'h2 >> { n27, i_2_ };
assign n44 = 32'd1465341951 >> { i_5_, i_0_, i_6_, i_1_, i_7_ };
assign n224 = 64'h7077f0ff70777077 >> { i_4_, n31, n108, i_2_, n96, i_3_ };
assign n225 = 32'd3104422667 >> { n53, n90, i_2_, i_13_, i_11_ };
assign n226 = 32'd134744064 >> { i_2_, i_7_, i_11_, n103, n34 };
assign n227 = 8'h02 >> { i_8_, i_7_, i_6_ };
assign n228 = 64'h0200020002020200 >> { i_3_, n108, n160, i_2_, i_1_, i_8_ };
assign n229 = 64'h2200222022202220 >> { i_2_, i_7_, n230, n35, i_10_, n33 };
assign n230 = 8'h02 >> { i_3_, i_2_, i_1_ };
assign n231 = 64'h0800080008080800 >> { i_4_, i_11_, i_3_, i_8_, n151, i_10_ };
assign n232 = 64'h8000800080008808 >> { i_3_, i_11_, i_4_, i_8_, n54, n124 };
assign n233 = 32'd572662434 >> { i_8_, i_6_, n110, n234, n230 };
assign n45 = 64'hff3f5f0f77335501 >> { i_6_, i_7_, i_5_, i_1_, i_2_, i_0_ };
assign n234 = 64'hfdfffdfffdfdfdff >> { i_12_, i_8_, i_4_, i_13_, i_9_, i_6_ };
assign n235 = 64'h1555555555555555 >> { i_3_, i_7_, i_12_, n56, n30, n236 };
assign n236 = 64'h0008000000080008 >> { i_7_, i_9_, i_6_, i_11_, i_2_, i_10_ };
assign n237 = 64'h0000000000000080 >> { i_10_, i_9_, i_13_, i_6_, i_4_, i_12_ };
assign n238 = 64'h8880080008000800 >> { n105, i_1_, i_2_, i_12_, i_9_, n82 };
assign n239 = 16'h0080 >> { i_6_, i_7_, n34, n168 };
assign n240 = 32'd1431393360 >> { i_11_, i_12_, i_1_, i_6_, n28 };
assign n241 = 64'h2000200022222000 >> { i_2_, n70, n27, n53, i_1_, n124 };
assign n242 = 32'd2861206154 >> { n243, n49, n245, n54, n244 };
assign n243 = 8'h08 >> { i_8_, i_6_, i_7_ };
assign n46 = 64'h8888880080808000 >> { i_6_, i_0_, i_5_, i_1_, i_3_, i_7_ };
assign n244 = 8'h80 >> { i_3_, i_5_, i_4_ };
assign n245 = 64'hfffffffffffffbd7 >> { i_8_, i_0_, i_6_, i_7_, i_2_, i_1_ };
assign n246 = 64'h0000000080000000 >> { i_9_, i_3_, i_7_, i_1_, i_0_, i_4_ };
assign n247 = 64'hfffffffffdfff77f >> { i_8_, i_2_, i_6_, i_1_, i_7_, i_0_ };
assign n248 = 64'h2222222222222202 >> { n258, n254, n256, n249, i_5_, n105 };
assign n249 = 64'h00110fff01110fff >> { n171, n251, n250, n252, n161, n253 };
assign n250 = 8'h08 >> { i_2_, i_1_, i_0_ };
assign n251 = 8'h08 >> { i_6_, i_8_, i_7_ };
assign n252 = 64'h0000000000000002 >> { i_10_, i_6_, i_7_, i_13_, i_11_, i_8_ };
assign n253 = 64'h0000000000000008 >> { i_10_, i_1_, i_13_, i_11_, i_2_, i_0_ };
assign n47 = 64'h777f7f7f77ff7fff >> { i_1_, i_0_, i_6_, i_5_, i_3_, i_2_ };
assign n254 = 16'ha888 >> { n171, n255, n107, n158 };
assign n255 = 8'h08 >> { i_1_, i_2_, i_0_ };
assign n256 = 32'd2290122880 >> { i_10_, i_6_, n158, n108, n257 };
assign n257 = 8'h02 >> { i_1_, i_0_, i_2_ };
assign n258 = 8'h80 >> { n99, n87, n259 };
assign n259 = 8'h08 >> { i_7_, i_6_, i_8_ };
assign n260 = 16'h0008 >> { i_13_, i_11_, i_12_, i_10_ };
assign n261 = 8'h02 >> { i_2_, i_0_, i_1_ };
assign n262 = 8'h02 >> { i_6_, i_7_, i_8_ };
assign n263 = 64'haaa8a8a8a8a8a8a8 >> { i_8_, i_5_, n82, n265, n264, n266 };
assign n48 = 4'h1 >> { i_3_, i_2_ };
assign n264 = 64'h8888800080008000 >> { i_1_, i_5_, i_6_, i_0_, i_10_, n167 };
assign n265 = 32'd134742024 >> { i_5_, i_0_, i_11_, i_6_, n48 };
assign n266 = 4'h2 >> { i_12_, i_13_ };
assign n267 = 64'h5555555515555555 >> { i_2_, n270, n36, n128, n105, n268 };
assign n268 = 64'h0000008000080088 >> { i_11_, i_12_, i_4_, i_5_, n269, i_10_ };
assign n269 = 8'h80 >> { i_3_, i_2_, i_1_ };
assign n270 = 16'h0002 >> { i_10_, i_13_, i_12_, i_11_ };
assign n271 = 64'h0002020202020202 >> { i_6_, n279, n278, n272, n273, n274 };
assign n272 = 64'h0000080000000880 >> { i_13_, i_5_, i_10_, i_4_, n154, i_3_ };
assign n273 = 8'h80 >> { n158, n139, n244 };
assign n49 = 8'h01 >> { i_2_, i_1_, i_0_ };
assign n274 = 64'h0000777077707770 >> { n275, n276, n202, i_4_, n243, n277 };
assign n275 = 32'd128 >> { i_7_, i_12_, i_10_, i_13_, i_8_ };
assign n276 = 8'h01 >> { i_3_, i_6_, i_5_ };
assign n277 = 64'h0000000000000080 >> { i_3_, i_9_, i_13_, i_5_, i_4_, i_11_ };
assign n278 = 4'h2 >> { i_3_, i_5_ };
assign n279 = 32'd128 >> { i_8_, i_11_, i_7_, i_13_, i_9_ };
assign n280 = 32'd4278189309 >> { n210, n209, i_3_, i_4_, i_5_ };
assign n281 = 64'h2020202020202022 >> { i_13_, n283, i_10_, n282, i_9_, i_4_ };
assign n282 = 64'h8000800080808000 >> { i_10_, i_1_, i_6_, n128, n124, i_5_ };
assign n283 = 32'd125269879 >> { i_2_, i_0_, n159, n40, n35 };
assign n50 = 4'h2 >> { i_3_, i_8_ };
assign n284 = 8'h02 >> { i_8_, i_6_, i_7_ };
assign n285 = 64'hfff7ffffffff7ff7 >> { i_6_, i_1_, i_7_, i_2_, i_8_, i_0_ };
assign n286 = 64'h0082000200800000 >> { n108, n131, i_5_, i_3_, i_4_, n262 };
assign n287 = 64'h0000077707770777 >> { n288, n276, n243, n289, n154, n127 };
assign n288 = 16'h0002 >> { i_8_, i_7_, i_11_, i_13_ };
assign n289 = 64'h0000000000000008 >> { i_3_, i_13_, i_4_, i_11_, i_12_, i_5_ };
assign n290 = 64'h0ddddddddddddddd >> { n129, n91, n259, n176, n291, n266 };
assign n291 = 64'haeeeeeeeeeeeeeee >> { i_7_, i_5_, i_8_, i_6_, i_11_, i_3_ };
assign n292 = 32'd2105540095 >> { n294, n293, i_6_, i_5_, i_3_ };
assign n293 = 32'd128 >> { i_7_, i_11_, i_8_, i_13_, i_9_ };
assign n51 = 32'd1381653 >> { i_5_, i_0_, i_6_, i_1_, i_3_ };
assign n294 = 32'd128 >> { i_8_, i_12_, i_7_, i_13_, i_10_ };
assign n295 = 8'h08 >> { i_11_, i_9_, i_8_ };
assign n296 = 64'h0000000000000002 >> { i_3_, i_6_, i_2_, i_5_, i_11_, i_10_ };
assign n297 = 32'd2004289399 >> { n298, n31, i_10_, n92, n51 };
assign n298 = 64'h015533770f5f3fff >> { i_6_, i_7_, i_5_, i_1_, i_2_, i_0_ };
assign n299 = 64'hddcdefcdffefefef >> { n295, i_6_, i_1_, n169, i_2_, i_5_ };
assign n300 = 64'h0000dd0ddd0ddd0d >> { n262, n270, n302, n301, n247, n87 };
assign n301 = 16'h0002 >> { i_9_, i_13_, i_12_, i_11_ };
assign n302 = 64'hffffffff7dffff7f >> { i_0_, i_6_, i_1_, i_2_, i_7_, i_8_ };
assign n303 = 64'h0000dd0ddd0ddd0d >> { n181, i_12_, n285, n301, n245, n87 };
assign n52 = 32'd1162149957 >> { i_5_, i_0_, i_1_, i_6_, i_3_ };
assign n304 = 16'h0002 >> { i_10_, i_9_, i_13_, i_11_ };
assign n305 = 64'hdddfdfdfddffdfff >> { i_1_, i_3_, i_6_, i_8_, i_9_, i_7_ };
assign n306 = 32'd8 >> { i_10_, i_7_, i_13_, n36, n35 };
assign n307 = 64'haaaaaaaaaaaaaaa2 >> { n316, n318, n314, n315, n308, n257 };
assign n308 = 64'h0000077707770777 >> { n312, n310, n311, n284, n309, n313 };
assign n309 = 8'h80 >> { i_3_, i_6_, i_5_ };
assign n310 = 16'h0080 >> { i_11_, i_7_, i_13_, i_9_ };
assign n311 = 64'h0000000000000008 >> { i_3_, i_9_, i_5_, i_13_, i_4_, i_11_ };
assign n312 = 16'h0009 >> { i_6_, i_5_, i_3_, i_8_ };
assign n313 = 32'd8 >> { i_8_, i_7_, i_12_, i_13_, i_10_ };
assign n53 = 4'h2 >> { i_3_, i_4_ };
assign n314 = 32'd32768 >> { i_5_, n105, n113, n227, n155 };
assign n315 = 16'h8000 >> { n176, n91, n129, n251 };
assign n316 = 4'h8 >> { n260, n317 };
assign n317 = 64'h0000000000000008 >> { i_8_, i_6_, i_7_, i_4_, i_5_, i_3_ };
assign n318 = 8'h80 >> { n278, n275, i_6_ };
assign n319 = 64'hffdfffdfddddffdf >> { i_7_, i_1_, i_6_, i_2_, i_4_, i_0_ };
assign n320 = 32'd1431639381 >> { i_7_, n36, n321, n30, n322 };
assign n321 = 4'h2 >> { i_11_, i_13_ };
assign n322 = 32'd128 >> { i_12_, i_11_, i_13_, i_10_, i_9_ };
assign n323 = 8'h02 >> { i_3_, i_5_, i_6_ };
assign n27 = 8'h1b >> { i_9_, i_10_, i_7_ };
assign n54 = 8'h08 >> { i_9_, i_6_, i_7_ };
assign n324 = 8'h02 >> { i_3_, i_6_, i_5_ };
assign n325 = 16'h8000 >> { n128, n266, n324, i_10_ };
assign n326 = 4'h8 >> { n227, n311 };
assign n327 = 32'd8 >> { i_9_, i_13_, i_4_, i_3_, i_5_ };
assign n328 = 64'hffff7fff7fffffff >> { i_3_, i_8_, n36, i_10_, n266, i_7_ };
assign n329 = 32'd1414813012 >> { n58, n112, n331, n330, i_5_ };
assign n330 = 64'h0080008088880080 >> { i_8_, n151, i_6_, n167, n304, i_4_ };
assign n331 = 32'd128 >> { i_7_, i_11_, n269, n30, n103 };
assign n332 = 16'h2aaa >> { n333, n334, n335, n93 };
assign n333 = 64'he7f7efffefffefff >> { n207, n321, n275, i_5_, i_6_, i_3_ };
assign n55 = 4'h2 >> { n56, i_5_ };
assign n334 = 16'h0777 >> { n279, n323, n243, n311 };
assign n335 = 64'h7777777707777777 >> { i_6_, i_3_, n313, i_5_, n155, n317 };
assign n336 = 64'h0000077707770777 >> { n323, n275, n279, n324, n284, n277 };
assign n337 = 32'd2860548224 >> { n155, n227, n101, n169, n327 };
assign n338 = 64'h8000800080008888 >> { n45, i_8_, n36, n167, n321, n211 };
assign n339 = 64'h5f4c0f0c5d4c0d0c >> { i_7_, n37, n45, n26, i_8_, n36 };
assign n340 = 64'h0222022213330222 >> { n62, n58, n71, n70, n84, i_5_ };
assign n341 = 64'h0000000000000080 >> { n68, n72, n80, n63, n75, n69 };
assign o_3_ = 16'h7fff >> { n340, n344, n341, o_2_ };
assign n343 = 64'h5707130355051101 >> { i_8_, i_6_, i_7_, i_2_, i_1_, i_3_ };
assign n56 = 4'h2 >> { i_6_, i_1_ };
assign n344 = 16'hff7f >> { i_9_, n343, i_5_, i_4_ };
assign n345 = 64'h2030253522322737 >> { i_2_, i_10_, i_3_, i_7_, i_9_, i_8_ };
assign n346 = 32'd1431655701 >> { i_1_, i_0_, i_4_, n345, n79 };
assign n347 = 64'ha2a2eea2a0a0eca0 >> { n49, n148, n139, n85, i_8_, n147 };
assign n348 = 64'h55005d085d085d08 >> { i_4_, n347, n164, n149, n444, i_5_ };
assign n349 = 64'hfaaaf888f888f888 >> { i_10_, n42, n109, n108, n107, n105 };
assign n350 = 64'h5555454d5555004c >> { i_1_, i_5_, i_6_, i_4_, i_3_, i_8_ };
assign n351 = 64'h0f008f881f119f99 >> { i_11_, i_12_, i_4_, i_3_, i_5_, i_7_ };
assign n352 = 64'h0000000800800088 >> { i_9_, i_10_, i_13_, i_5_, n351, n99 };
assign n353 = 64'h0081008188891191 >> { i_2_, i_6_, i_1_, i_7_, i_8_, i_5_ };
assign n57 = 8'h01 >> { i_9_, i_7_, i_11_ };
assign n354 = 64'hff77fff7ff7fffff >> { n110, n111, i_3_, i_8_, i_0_, n353 };
assign n355 = 64'h0808080808088808 >> { n76, n84, n346, n112, n114, n354 };
assign n356 = 64'h4602020244000002 >> { i_4_, i_3_, i_11_, i_13_, i_10_, i_12_ };
assign n357 = 64'h80aa008080800080 >> { i_6_, i_3_, i_4_, i_1_, i_8_, i_5_ };
assign n358 = 16'h8000 >> { n357, i_7_, i_0_, n129 };
assign n359 = 16'h0008 >> { i_3_, i_13_, i_0_, i_4_ };
assign n360 = 64'h058045c405004544 >> { i_11_, i_1_, i_6_, i_2_, i_7_, i_9_ };
assign n361 = 64'he8a8c888e0a0c000 >> { i_8_, i_7_, i_6_, i_3_, i_2_, i_1_ };
assign n362 = 64'h5444444444444444 >> { i_9_, i_0_, i_12_, n361, n137, i_4_ };
assign n363 = 64'hd8d85058c8884008 >> { i_2_, i_4_, i_3_, i_12_, i_8_, i_11_ };
assign n58 = 8'h51 >> { n61, n60, n59 };
assign n364 = 64'h9999b9999888a888 >> { n140, i_9_, i_7_, n363, i_13_, i_11_ };
assign n365 = 32'd2867571439 >> { i_6_, n157, i_13_, n364, i_0_ };
assign n366 = 64'hdf7fdf7f5777df7f >> { i_6_, i_3_, i_8_, i_1_, i_0_, i_2_ };
assign n367 = 64'h55d5f5f54480f5f5 >> { n158, n366, i_7_, i_10_, n159, i_0_ };
assign n368 = 32'd4286447487 >> { i_12_, i_4_, i_0_, i_11_, n367 };
assign n369 = 64'h0000000000000008 >> { i_3_, i_9_, i_0_, i_13_, i_4_, i_11_ };
assign n370 = 32'd926381879 >> { i_6_, i_1_, n369, i_7_, n161 };
assign n371 = 64'h2050205022722050 >> { i_11_, n182, i_8_, n33, i_9_, i_6_ };
assign n372 = 32'd4286578557 >> { i_10_, i_2_, i_6_, i_5_, n371 };
assign n373 = 32'd1434408318 >> { i_11_, i_13_, i_1_, i_6_, i_9_ };
assign n59 = 32'd2 >> { i_10_, i_8_, i_7_, i_1_, i_4_ };
assign n374 = 32'd2863311522 >> { i_2_, i_13_, i_12_, n54, n373 };
assign n375 = 32'd1997010695 >> { i_2_, n190, n53, n129, n94 };
assign n376 = 32'd2147518472 >> { n192, n193, i_3_, n375, n191 };
assign n377 = 64'hfa52aa02fa72aa22 >> { n30, n33, i_12_, i_3_, i_13_, i_7_ };
assign n378 = 64'hfbddeaccf9dde8cc >> { n196, n194, n377, i_8_, i_2_, i_7_ };
assign o_6_ = 64'hff77fff7ff7fffff >> { n197, n203, n199, i_7_, n378, n206 };
assign n380 = 64'h92b293b312321333 >> { i_9_, n219, n155, i_3_, i_8_, i_2_ };
assign n381 = 64'h1150554011105540 >> { i_12_, n380, i_1_, n213, i_8_, n220 };
assign o_5_ = 64'hfff5fffdfff7ffff >> { n391, n381, n386, n221, i_6_, n393 };
assign n383 = 32'd538976290 >> { i_7_, i_8_, i_12_, i_4_, i_11_ };
assign n60 = 8'h02 >> { i_10_, i_2_, i_4_ };
assign n384 = 64'h6e6e6e6e446e6e6e >> { n53, i_12_, n207, i_9_, n383, i_6_ };
assign n385 = 16'h2131 >> { i_10_, n384, n212, i_6_ };
assign n386 = 32'd2863311402 >> { n208, n388, n385, n186, i_1_ };
assign n387 = 64'he444e040e040e040 >> { i_6_, n31, i_12_, n211, i_11_, i_7_ };
assign n388 = 32'd3722304909 >> { n192, n209, n210, n387, i_3_ };
assign n389 = 64'h1113131313131313 >> { i_12_, i_7_, i_3_, n167, n231, n169 };
assign n390 = 64'h9dddbfffbfffbfff >> { n94, n105, n53, n131, i_7_, i_1_ };
assign n391 = 32'd8 >> { n163, n228, n229, n390, n389 };
assign n392 = 64'hffaeaeaeaeaeaeae >> { n34, i_2_, n28, n240, n167, n239 };
assign n393 = 64'h0008000800000008 >> { i_4_, n392, n232, n233, n450, n235 };
assign n61 = 16'heac8 >> { i_1_, i_8_, i_3_, i_6_ };
assign n394 = 64'hff81ff01ff80ff00 >> { n30, n31, n211, i_5_, i_7_, i_6_ };
assign n395 = 64'h55d5d5d5d5d5d5d5 >> { i_13_, i_3_, n394, n280, n271, n42 };
assign o_7_ = 64'hffffffff7fffffff >> { n403, n398, n395, n455, n458, n463 };
assign n397 = 64'h2222222202222222 >> { i_9_, i_4_, i_5_, n343, n72, n69 };
assign n398 = 32'd232588629 >> { n75, n452, n147, n397, n112 };
assign n399 = 64'ha8cca0cc88cc80cc >> { i_8_, i_6_, i_5_, i_1_, i_3_, i_2_ };
assign n400 = 64'h00ff007f00f70077 >> { n247, i_9_, n246, i_5_, n399, i_4_ };
assign n401 = 32'd2726330496 >> { n87, n261, n42, i_6_, i_8_ };
assign n402 = 64'hf970b920d9509900 >> { n49, n257, n401, n260, i_7_, i_6_ };
assign n403 = 64'hff00fd00fd00fd00 >> { n91, n402, i_9_, n248, n263, n267 };
assign n62 = 32'd2 >> { i_10_, i_8_, i_6_, i_7_, i_4_ };
assign n404 = 64'h7f7f7f7f557f7f7f >> { i_11_, i_7_, n52, n46, i_10_, i_9_ };
assign n405 = 64'h64ec74fc44cc54dc >> { n73, i_2_, n285, i_1_, i_5_, i_4_ };
assign n406 = 64'h88a8002000200020 >> { n99, n284, i_0_, n243, i_5_, n155 };
assign n407 = 32'd2155905024 >> { i_4_, n406, i_3_, n405, n131 };
assign n408 = 64'h0042004000400040 >> { i_10_, i_11_, i_13_, i_4_, i_12_, i_3_ };
assign n409 = 64'hfffffff77fffffff >> { i_3_, i_8_, i_6_, i_5_, i_7_, n408 };
assign n410 = 64'haaaaaaaa2aaaaaaa >> { n286, n409, n287, n290, n292, n49 };
assign n411 = 64'h2202020202020202 >> { i_7_, i_1_, i_0_, n43, i_9_, n87 };
assign n412 = 64'h0500454415115555 >> { n300, n303, n411, i_8_, i_5_, i_4_ };
assign n413 = 64'hae2eae2eff7fae2e >> { i_7_, i_3_, i_9_, i_8_, i_2_, i_6_ };
assign n63 = 16'h1011 >> { n67, n65, n66, n64 };
assign n414 = 64'hdd7f5d5fff7f5f5f >> { n304, n305, n413, n147, i_6_, i_0_ };
assign n415 = 8'ha2 >> { n306, n414, i_4_ };
assign n416 = 64'h7745774577557745 >> { i_1_, i_6_, i_4_, i_2_, i_5_, i_3_ };
assign n417 = 64'h5d5d5d5d595d5d5d >> { i_9_, n227, n260, i_4_, i_5_, i_2_ };
assign n418 = 16'h0080 >> { i_12_, i_1_, i_6_, n207 };
assign n419 = 16'hfff7 >> { i_7_, n37, n211, n321 };
assign n420 = 64'h0880aaaa8880aaaa >> { n418, i_3_, n417, i_2_, n419, n320 };
assign n421 = 64'h15373737153f3f3f >> { n168, n243, n155, n277, n227, n327 };
assign n422 = 64'hf5fdf7fff7fff7ff >> { i_9_, n288, n293, i_6_, i_3_, i_5_ };
assign n423 = 64'h929ab2ba828aa2aa >> { n288, n293, n294, i_6_, i_5_, i_3_ };
assign n28 = 16'ha820 >> { i_9_, i_10_, i_6_, i_1_ };
assign n64 = 32'd1 >> { n34, n35, i_3_, i_10_, i_9_ };
assign n424 = 64'haaaaaa28aaaaaa20 >> { i_9_, n326, n325, i_3_, n423, n261 };
assign n425 = 64'hd7f7dfffdfffdfff >> { i_8_, n310, n313, i_6_, i_5_, i_3_ };
assign n426 = 32'd286347537 >> { n337, n336, n425, n255, n338 };
assign n427 = 64'h2022202000220020 >> { n44, n27, i_8_, n43, n46, n47 };
assign n428 = 64'h555d050d557f050f >> { i_11_, n427, i_0_, i_12_, i_5_, n28 };
assign o_2_ = 64'hfdfdfffdfffdfffd >> { n38, n339, i_11_, n41, n29, n428 };
assign n430 = 64'h3120312075753120 >> { i_10_, n33, n110, n108, i_3_, i_8_ };
assign n431 = 64'h0022202202222222 >> { n99, n49, n430, i_8_, n163, n370 };
assign n432 = 32'd2863327914 >> { n162, n431, n365, n368, i_5_ };
assign n433 = 64'hfdf5fff7fff7fff7 >> { i_0_, n94, n86, i_7_, i_5_, n350 };
assign n65 = 16'hfdec >> { i_11_, i_12_, i_10_, i_7_ };
assign n434 = 64'h0000000000008000 >> { n95, n352, n438, n118, n355, n441 };
assign o_4_ = 64'hffffffffffff7fff >> { n89, n447, n434, n348, n433, n432 };
assign n436 = 64'h0000200000002008 >> { i_13_, i_11_, i_3_, i_9_, i_5_, i_12_ };
assign n437 = 64'ha0e02060a0f12071 >> { n106, i_6_, i_0_, n436, i_1_, i_5_ };
assign n438 = 64'h0000aa2a0000bf7f >> { n349, n100, i_8_, n437, i_7_, i_5_ };
assign n439 = 64'ha8982010a898a898 >> { i_4_, i_3_, i_10_, n356, i_0_, i_2_ };
assign n440 = 64'h8006000680040004 >> { n94, n129, i_6_, i_8_, i_5_, i_0_ };
assign n441 = 64'h0000000200020002 >> { n440, n439, n125, n130, n358, n134 };
assign n442 = 64'ha2aab3bfb3bfb3bf >> { i_6_, n140, n359, i_9_, n360, i_12_ };
assign n443 = 32'd11250603 >> { n141, n140, n143, n142, i_7_ };
assign n66 = 64'h0000000200010003 >> { i_11_, i_12_, i_1_, i_5_, i_10_, i_6_ };
assign n444 = 64'h0000000000000008 >> { n138, n144, n145, n362, n442, n443 };
assign n445 = 64'h4455000544550405 >> { n111, i_3_, n158, n181, n184, n185 };
assign n446 = 64'h22222222f2222222 >> { n183, i_5_, n445, n374, n175, n177 };
assign n447 = 64'haaaaaaaa2aaaaaaa >> { n188, n186, n446, n372, n376, i_0_ };
assign n448 = 64'h0000ff080008ff08 >> { i_2_, i_7_, i_3_, i_10_, i_8_, n182 };
assign n449 = 64'h51115111d9995111 >> { i_12_, n31, i_1_, n30, i_3_, i_6_ };
assign n450 = 64'h0011011101110111 >> { n449, n448, i_11_, n241, n238, n237 };
assign n451 = 64'h0100044002200880 >> { i_6_, i_7_, i_0_, i_5_, i_2_, i_1_ };
assign n452 = 32'd4223384507 >> { n53, i_8_, n451, n400, n242 };
assign n453 = 64'h9810fa50fc30fe70 >> { i_2_, i_1_, n295, n169, i_6_, i_7_ };
assign n67 = 16'h0111 >> { i_1_, i_6_, i_2_, i_5_ };
assign n454 = 64'hff7fff7fffffff7f >> { i_0_, n453, n296, n297, n299, n404 };
assign n455 = 32'd65793 >> { n266, n454, n281, n407, n410 };
assign n456 = 64'h0200020002020200 >> { i_12_, i_8_, i_3_, i_13_, i_9_, i_11_ };
assign n457 = 64'hfffd77fdfdfd75fd >> { n319, n302, n416, i_10_, i_3_, n456 };
assign n458 = 64'h0008000000080008 >> { n412, i_3_, n307, n415, n457, n420 };
assign n459 = 64'h77f77fff7fff7fff >> { i_9_, n288, n293, i_3_, i_6_, i_5_ };
assign n460 = 16'hd555 >> { n459, n328, n421, n250 };
assign n461 = 64'h7fff7fff6eee7fff >> { i_6_, n277, i_10_, n323, i_7_, i_8_ };
assign n462 = 64'h22ffa2ff20ffa0ff >> { i_8_, n97, n99, n461, n266, n422 };
assign n463 = 64'h0000000000000080 >> { n329, n332, n424, n462, n426, n460 };
assign n68 = 64'h0101010111010101 >> { i_12_, i_7_, n55, n65, i_2_, i_9_ };
assign n69 = 32'd4160223061 >> { i_10_, i_9_, i_3_, n49, i_4_ };
assign n70 = 8'h08 >> { i_9_, i_8_, i_4_ };
assign n71 = 16'h8cae >> { i_1_, i_2_, i_6_, i_7_ };
assign n72 = 64'h5500554055405540 >> { i_1_, i_6_, n74, n53, n73, i_5_ };
assign n73 = 4'h1 >> { i_10_, i_7_ };
assign n29 = 16'ha820 >> { i_9_, i_10_, i_5_, i_0_ };
assign n74 = 32'd2 >> { i_10_, i_8_, i_2_, i_1_, i_4_ };
assign n75 = 4'h2 >> { n76, n346 };
assign n76 = 8'h45 >> { n78, n77, i_0_ };
assign n77 = 64'h0000000200800082 >> { i_9_, i_10_, i_2_, i_6_, i_8_, i_4_ };
assign n78 = 64'hfffffffdff7fff7d >> { i_9_, i_10_, i_3_, i_6_, i_7_, i_4_ };
assign n79 = 64'h0000000000000008 >> { i_3_, i_9_, i_2_, i_0_, i_6_, i_4_ };
assign n80 = 64'h0055045501550555 >> { i_11_, i_12_, n81, i_1_, i_6_, i_0_ };
assign n81 = 32'd353703168 >> { i_2_, n83, n70, n82, n62 };
assign n82 = 4'h8 >> { i_6_, i_7_ };
assign n83 = 64'hfffffd75febafc30 >> { i_11_, i_12_, i_9_, i_10_, i_6_, i_7_ };
assign n30 = 4'h2 >> { i_8_, i_10_ };
assign n84 = 32'd538976800 >> { i_8_, n49, n85, i_10_, i_4_ };
assign n85 = 64'h0001000100011111 >> { i_7_, i_1_, i_6_, i_2_, i_3_, i_0_ };
assign n86 = 64'hf5f7fcfff7f7feff >> { i_4_, n88, n87, i_0_, i_1_, i_3_ };
assign n87 = 16'h0002 >> { i_10_, i_13_, i_11_, i_12_ };
assign n88 = 8'h08 >> { i_12_, i_10_, i_11_ };
assign n89 = 32'd572662274 >> { n92, n91, n90, i_12_, n93 };
assign n90 = 32'd3722436575 >> { i_8_, i_3_, i_7_, i_11_, i_9_ };
assign n91 = 8'h08 >> { i_4_, i_5_, i_3_ };
assign n92 = 8'h02 >> { i_7_, i_11_, i_10_ };
assign n93 = 8'h08 >> { i_0_, i_1_, i_2_ };
assign n31 = 4'h8 >> { i_8_, i_9_ };
assign n94 = 4'h8 >> { i_10_, i_11_ };
assign n95 = 64'h88888888888888a8 >> { i_4_, n98, i_5_, i_6_, n97, n96 };
assign n96 = 4'h2 >> { i_11_, i_12_ };
assign n97 = 64'h0000000000008000 >> { i_8_, i_5_, i_3_, i_6_, i_7_, i_10_ };
assign n98 = 64'h00f7f7f7f7f7f7f7 >> { i_7_, i_10_, i_8_, i_0_, i_2_, i_3_ };
assign n99 = 8'h02 >> { i_2_, i_1_, i_0_ };
assign n100 = 64'haa20202020202020 >> { n31, n101, i_3_, n103, n102, n104 };
assign n101 = 4'h1 >> { i_6_, i_7_ };
assign n102 = 64'hf7f7f7f7f7f700f7 >> { i_7_, i_8_, i_9_, i_0_, i_2_, i_3_ };
assign n103 = 4'h1 >> { i_6_, i_4_ };
assign o_1_ = 64'h666566656665aaa9 >> { n30, n31, n34, n35, i_3_, n33 };
assign n104 = 8'h08 >> { i_12_, i_5_, i_11_ };
assign n105 = 4'h2 >> { i_4_, i_3_ };
assign n106 = 64'hfdfffdfffdfffdfd >> { i_3_, i_12_, i_4_, i_9_, i_13_, i_11_ };
assign n107 = 16'h0008 >> { i_0_, i_11_, i_2_, i_1_ };
assign n108 = 8'h02 >> { i_13_, i_12_, i_11_ };
assign n109 = 64'h0000000200020002 >> { i_1_, i_6_, i_3_, i_7_, i_10_, i_8_ };
assign n110 = 8'h01 >> { i_10_, i_13_, i_11_ };
assign n111 = 8'h01 >> { i_9_, i_13_, i_12_ };
assign n112 = 4'h8 >> { n113, i_12_ };
assign n113 = 4'h2 >> { i_13_, i_11_ };
assign n33 = 4'h2 >> { i_13_, i_4_ };
assign n114 = 64'hdddfdddf5555dddf >> { n117, i_2_, n116, n115, i_5_, i_0_ };
assign n115 = 32'd32768 >> { i_8_, i_10_, i_3_, i_12_, i_11_ };
assign n116 = 64'h0080008000000080 >> { i_12_, i_6_, i_7_, i_2_, i_10_, i_11_ };
assign n117 = 32'd2012708863 >> { i_11_, i_12_, i_6_, i_10_, i_9_ };
assign n118 = 32'd221196079 >> { n55, n124, n119, i_2_, n57 };
assign n119 = 64'h80888088aaaa8088 >> { n120, n104, n122, n121, n96, n123 };
assign n120 = 64'he8eaeceef8fafcff >> { i_1_, i_2_, i_3_, i_6_, i_7_, i_8_ };
assign n121 = 16'h0080 >> { i_5_, i_6_, i_2_, i_8_ };
assign n122 = 64'hdddddfffdfffdfff >> { i_8_, i_1_, i_3_, i_6_, i_5_, i_7_ };
assign n123 = 4'h1 >> { i_0_, i_4_ };
endmodule

654
openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.act Normal file
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@ -0,0 +1,654 @@
i_0_ 0.517800 0.509800
i_1_ 0.507400 0.499600
i_2_ 0.508800 0.498400
i_3_ 0.478800 0.507400
i_4_ 0.491600 0.501200
i_5_ 0.499600 0.504400
i_6_ 0.494200 0.516000
i_7_ 0.502600 0.504000
i_8_ 0.510400 0.482400
i_9_ 0.516800 0.499800
i_10_ 0.493000 0.507200
i_11_ 0.495600 0.504600
i_12_ 0.502800 0.507600
i_13_ 0.494600 0.500600
i_14_ 0.504800 0.502800
i_16_ 0.504000 0.505200
i_17_ 0.497400 0.512600
i_18_ 0.502200 0.502200
i_19_ 0.495200 0.500000
i_20_ 0.491000 0.493200
i_21_ 0.495600 0.501600
i_22_ 0.495200 0.503200
i_23_ 0.505400 0.491000
i_24_ 0.518400 0.508200
i_25_ 0.502400 0.500800
i_26_ 0.494600 0.494600
i_27_ 0.497000 0.486400
i_28_ 0.500400 0.500600
i_29_ 0.503400 0.500800
i_30_ 0.489000 0.511800
i_31_ 0.495400 0.503000
i_32_ 0.481000 0.510800
i_33_ 0.500800 0.501600
i_34_ 0.498400 0.496200
i_35_ 0.512400 0.485400
i_36_ 0.493000 0.499400
i_37_ 0.497000 0.501000
i_38_ 0.505800 0.501600
n45 0.000600 0.025535
n46 0.007400 0.237365
n47 0.016000 0.000507
n48 0.006400 0.000028
n49 0.123000 0.026212
n50 0.500600 0.125514
n51 0.122000 0.026567
n52 0.239600 0.095360
n53 0.016000 0.004553
n54 0.246800 0.094778
n55 0.134400 0.030214
n56 0.244200 0.089975
n57 0.995200 0.000000
n58 0.000000 0.000000
n59 0.997800 0.025852
n60 0.128000 0.029538
n61 0.058400 0.007102
n62 0.123000 0.025653
n63 0.962800 0.090969
n64 0.252200 0.094921
n65 0.067000 0.006902
n66 0.000000 0.000000
n67 0.008200 0.237452
n68 0.015400 0.000489
n69 0.016000 0.000444
n70 0.241000 0.098188
n71 0.124000 0.026377
n72 0.261000 0.089271
n73 0.125400 0.025966
n74 0.260000 0.099153
n75 0.234000 0.097721
n76 0.242600 0.092149
n77 0.063800 0.008474
n78 0.969400 0.000965
n79 0.003600 0.121985
n80 0.000000 0.000464
n81 0.000200 0.000006
n82 0.125400 0.026450
n83 0.243400 0.094495
n84 0.125000 0.026618
n85 0.997400 0.000000
n86 0.000000 0.000015
n87 0.117600 0.026356
n88 0.128800 0.029209
n89 0.244800 0.102081
n90 0.015000 0.000426
n91 0.002800 0.236969
n92 0.123800 0.027757
n93 0.030400 0.001734
n94 0.057800 0.006902
n95 0.000200 0.000000
n96 0.113000 0.024458
n97 0.122200 0.025590
n98 0.015400 0.000472
n99 0.128200 0.027168
n100 0.016200 0.000474
n101 0.001600 0.000010
n102 0.250200 0.091886
n103 0.031200 0.001879
n104 0.184400 0.031650
n105 0.129200 0.028722
n106 0.000000 0.000000
n107 0.012200 0.000510
n108 0.117600 0.028205
n109 0.995000 0.000000
n110 0.000200 0.000050
n111 0.999400 0.000474
n112 0.122000 0.028443
n113 0.061600 0.006943
n114 0.014600 0.000454
n115 0.015800 0.000444
n116 0.008000 0.005167
n117 0.126800 0.026916
n118 0.997200 0.000068
n119 0.019200 0.000431
n120 0.186000 0.007014
n121 0.014600 0.000464
n122 0.232200 0.017175
n123 0.018200 0.000443
n124 0.995600 0.001698
n125 0.015200 0.000482
n126 0.063800 0.007433
n127 0.118200 0.025867
n128 0.033400 0.002072
n129 0.015800 0.000501
n130 0.000000 0.000000
n131 0.000000 0.000000
n132 0.007000 0.000111
n133 0.059000 0.007017
n134 0.991000 0.000001
n135 0.014200 0.000485
n136 0.129000 0.028071
n137 0.033400 0.002054
n138 0.991800 0.000063
n139 0.996400 0.000000
n140 0.003000 0.000025
n141 0.242000 0.089340
n142 0.014600 0.000529
n143 0.996800 0.000429
n144 0.115000 0.025850
n145 0.129200 0.026603
n146 0.123000 0.027116
n147 0.016600 0.000492
n148 0.031000 0.002016
n149 0.054800 0.006993
n150 0.002400 0.000009
n151 0.132600 0.029850
n152 0.032200 0.001795
n153 0.014400 0.000444
n154 0.982200 0.003292
n155 0.111400 0.025404
n156 0.011400 0.000444
n157 0.006600 0.000057
n158 0.010400 0.000358
n159 0.134000 0.010573
n160 0.122200 0.028002
n161 0.077000 0.007987
n162 0.277200 0.152811
n163 0.129600 0.028505
n164 0.257400 0.100855
n165 0.032800 0.001762
n166 0.996400 0.000000
n167 0.003600 0.000015
n168 0.005200 0.000078
n169 0.251400 0.091190
n170 0.118400 0.025466
n171 0.116600 0.024777
n172 0.000000 0.000000
n173 0.129400 0.029266
n174 0.999000 0.000092
n175 0.130000 0.029735
n176 0.082200 0.007550
n177 0.253800 0.091496
n178 0.093200 0.201037
n179 0.015800 0.000478
n180 0.995400 0.000000
n181 0.989600 0.092199
n182 0.032600 0.002000
n183 0.123800 0.028068
n184 0.000000 0.000000
n185 0.000200 0.000000
n186 0.998200 0.000008
n187 0.016800 0.000451
n188 0.502600 0.247370
n189 0.002800 0.000008
n190 0.017800 0.000561
n191 0.997600 0.000000
n192 0.001800 0.000008
n193 0.120200 0.026794
n194 0.016800 0.000497
n195 0.993200 0.000001
n196 0.004200 0.139905
n197 0.068400 0.007526
n198 0.752800 0.035448
n199 0.000800 0.001124
n200 0.813400 0.030949
n201 0.016800 0.000547
n202 0.033600 0.002135
n203 0.009000 0.159379
n204 0.064600 0.007597
n205 0.897200 0.009343
n206 0.030800 0.001946
n207 0.008200 0.000125
n208 0.130000 0.027985
n209 0.249400 0.094905
n210 0.977400 0.039770
n211 0.075200 0.007822
n212 0.000000 0.000000
n213 0.007200 0.253157
n214 0.122000 0.029273
n215 0.032600 0.001790
n216 0.120800 0.028646
n217 0.004800 0.000279
n218 0.127200 0.027063
n219 0.000200 0.055144
n220 0.061600 0.061637
n221 0.000200 0.094607
n222 0.849200 0.027645
n223 0.012600 0.000530
n224 0.994000 0.163012
n225 0.252600 0.093899
n226 0.071800 0.068115
n227 0.181800 0.032528
n228 0.002800 0.008991
n229 0.003000 0.000007
n230 0.015200 0.000452
n231 0.012800 0.000462
n232 0.002400 0.000008
n233 0.000000 0.000000
n234 0.008400 0.000983
n235 0.001800 0.000283
n236 0.998600 0.000000
n237 0.001400 0.006110
n238 0.000000 0.000001
n239 0.000000 0.000005
n240 0.015600 0.000512
n241 0.998800 0.000001
n242 0.058600 0.211920
n243 0.001400 0.005628
n244 1.000000 0.000338
n245 0.986400 0.000166
n246 0.813200 0.000021
n247 0.692000 0.089460
n248 0.186600 0.030164
n249 0.000800 0.000013
n250 0.121800 0.027239
n251 0.778400 0.019470
n252 0.031000 0.016653
n253 0.252800 0.092653
n254 0.990600 0.001037
n255 0.016000 0.000489
n256 0.031800 0.001942
n257 0.001000 0.000002
n258 0.240600 0.093058
n259 0.151400 0.026532
n260 0.134600 0.028269
n261 0.000000 0.000200
n262 0.035600 0.023152
n263 0.134000 0.186651
n264 0.003800 0.049266
n265 0.005600 0.000428
n266 0.001200 0.000306
n267 0.124600 0.177646
n268 0.236200 0.086675
n269 0.056600 0.006824
n270 0.045200 0.004362
n271 0.185600 0.030668
n272 0.000000 0.000000
n273 0.000200 0.000000
n274 0.000000 0.000000
n275 0.001600 0.000000
n276 0.001400 0.000004
n277 0.001200 0.000007
n278 0.000000 0.000000
n279 0.000000 0.000000
n280 0.000600 0.000006
n281 0.000000 0.000015
n282 0.018400 0.000542
n283 0.000000 0.000000
n284 0.002200 0.000060
n285 0.000400 0.000002
n286 0.129600 0.028310
n287 0.996000 0.000000
n288 0.000000 0.000000
n289 0.023000 0.032222
n290 0.968600 0.000930
n291 0.000000 0.000000
n292 0.993000 0.000008
n293 0.000200 0.000022
n294 0.000000 0.000000
n295 0.037200 0.000287
n296 0.002200 0.000077
n297 0.999800 0.000025
n298 0.001000 0.000016
n299 0.018200 0.000500
n300 0.000000 0.000000
n301 0.000000 0.000000
n302 0.000200 0.000000
n303 0.008600 0.000256
n304 0.973800 0.000614
n305 0.015800 0.000556
n306 0.017800 0.000567
n307 0.382000 0.171543
n308 0.950600 0.002354
n309 0.043000 0.000775
n310 0.031600 0.001735
n311 0.954200 0.000450
n312 0.032400 0.001727
n313 0.031200 0.001679
n314 0.245000 0.087407
n315 0.244800 0.101937
n316 0.015800 0.000489
n317 0.000400 0.000000
n318 0.000000 0.000003
n319 0.268200 0.091067
n320 0.027200 0.009852
n321 0.191400 0.006872
n322 0.253200 0.091650
n323 0.000000 0.210556
n324 0.121800 0.025901
n325 0.018000 0.000460
n326 0.014600 0.000430
n327 0.104800 0.000000
n328 0.001400 0.059784
n329 0.256400 0.101622
n330 0.032400 0.001783
n331 0.058400 0.007601
n332 0.131400 0.003850
n333 0.557600 0.094153
n334 0.122800 0.027364
n335 0.117600 0.013751
n336 0.666200 0.085373
n337 0.028600 0.222388
n338 0.118600 0.024986
n339 0.999000 0.000000
n340 0.000800 0.000001
n341 0.966200 0.000000
n342 0.009400 0.000154
n343 0.000000 0.000261
n344 0.952200 0.002525
n345 0.756200 0.196176
n346 0.013200 0.000436
n347 0.015800 0.004026
n348 0.207400 0.150134
n349 0.087800 0.001816
n350 0.929400 0.000000
n351 0.995800 0.000000
n352 0.002800 0.000014
n353 0.006200 0.166345
n354 0.000400 0.000001
n355 0.937600 0.005424
n356 0.122000 0.028563
n357 0.061200 0.007983
n358 0.060000 0.006745
n359 0.000200 0.000000
n360 0.809600 0.031234
n361 0.001600 0.000007
n362 0.129600 0.026490
n363 0.096200 0.296204
n364 0.028600 0.001747
n365 0.002200 0.202121
n366 0.134400 0.027352
n367 0.046800 0.002087
n368 0.120400 0.026534
n369 0.999200 0.000000
n370 0.001600 0.000011
n371 0.004200 0.000038
n372 0.000200 0.000000
n373 0.237000 0.089343
n374 0.057400 0.006791
n375 0.061000 0.007093
n376 0.032400 0.001873
n377 0.134000 0.026584
n378 0.252800 0.103831
n379 0.874800 0.026794
n380 0.001800 0.000148
n381 0.914800 0.006214
n382 0.245400 0.097566
n383 0.066200 0.007463
n384 0.000000 0.000000
n385 0.002600 0.000017
n386 0.068800 0.007656
n387 0.876200 0.000000
n388 0.977600 0.030366
n389 0.123800 0.000274
n390 0.000200 0.000000
n391 0.000400 0.000001
n392 0.000000 0.000000
n393 0.132600 0.025250
n394 0.998800 0.138931
n395 0.000200 0.000000
n396 0.253400 0.091895
n397 0.001000 0.000041
n398 0.000400 0.129461
n399 0.914800 0.001234
n400 0.000000 0.000000
n401 0.005400 0.234824
n402 0.119800 0.026391
n403 0.004400 0.002304
n404 0.248800 0.094927
n405 0.255200 0.084515
n406 0.130400 0.025056
n407 0.003400 0.000037
n408 0.059000 0.006642
n409 0.000000 0.000000
n410 0.000600 0.000001
n411 0.002800 0.000000
n412 0.012600 0.002722
n413 0.005600 0.194237
n414 0.258400 0.100761
n415 0.000400 0.000000
n416 0.996000 0.000002
n417 0.000000 0.000001
n418 0.903400 0.000003
n419 0.127400 0.176082
n420 0.094200 0.008761
n421 0.949600 0.004543
n422 0.950800 0.192492
n423 0.001800 0.000421
n424 0.910400 0.000117
n425 0.045800 0.000457
n426 0.254400 0.097184
n427 0.007800 0.251594
n428 0.018600 0.000492
n429 0.003800 0.184566
n430 0.018600 0.000547
n431 0.997800 0.000014
n432 0.999600 0.000001
n433 0.124400 0.026964
n434 0.957200 0.000002
n435 0.269400 0.097631
n436 0.983200 0.000136
n437 0.006000 0.000006
n438 0.129400 0.176338
n439 0.990600 0.000000
n440 0.000800 0.005372
n441 0.048400 0.002473
n442 0.001400 0.000000
n443 0.000000 0.000000
n444 0.989600 0.000002
n445 0.000000 0.000000
n446 0.028200 0.001757
n447 0.000800 0.000000
n448 0.197200 0.006680
n449 0.990800 0.015692
n450 0.893800 0.008579
n451 0.030400 0.002242
n452 0.035000 0.001778
n453 0.809400 0.034193
n454 0.895600 0.001910
n455 0.001200 0.000005
n456 0.046800 0.000460
n457 0.017200 0.003631
n458 0.000000 0.003696
n459 0.046600 0.294566
n460 0.997400 0.000001
n461 0.998200 0.000009
n462 0.870800 0.004080
n463 0.001800 0.000157
n464 0.032800 0.002201
n465 0.000800 0.000000
n466 0.000600 0.073353
n467 0.007000 0.000130
n468 0.914800 0.023735
n469 0.124400 0.024965
n470 0.120200 0.026016
n471 0.969800 0.035957
n472 0.126400 0.027456
n473 0.779400 0.032055
n474 0.015200 0.000472
n475 0.007200 0.001044
n476 0.003200 0.000020
n477 0.000600 0.000001
n478 0.001200 0.000260
n479 0.005400 0.011434
n480 0.003600 0.195573
n481 0.002000 0.000003
n482 0.997400 0.000000
n483 0.000200 0.000297
n484 0.000200 0.000000
n485 0.121400 0.029595
n486 0.998200 0.000002
n487 0.001200 0.000002
n488 0.195800 0.007798
n489 0.004400 0.000675
n490 0.906000 0.000373
n491 0.046000 0.000480
n492 0.090400 0.002258
n493 0.015600 0.118258
o_0_ 0.033600 0.079455
n495 0.130400 0.027814
n496 0.018000 0.000300
n497 0.020600 0.000511
n498 0.008200 0.001020
n499 0.239200 0.091074
n500 0.003200 0.003406
n501 0.003200 0.000075
n502 0.021000 0.000029
n503 0.254000 0.093762
n504 0.014200 0.011958
n505 0.064600 0.141413
n506 0.478400 0.016355
n507 0.785400 0.032210
n508 0.000600 0.000076
n509 0.564600 0.007997
n510 0.001000 0.000047
n511 0.006200 0.006710
n512 0.991400 0.000134
n513 0.991800 0.000000
n514 0.998800 0.000007
n515 0.064800 0.008156
n516 0.063600 0.008282
n517 0.995200 0.000013
n518 0.000800 0.000002
n519 0.184400 0.031666
n520 0.002600 0.000076
n521 0.000000 0.000000
n522 0.253800 0.046650
n523 0.000000 0.000000
n524 0.000000 0.000013
n525 0.000200 0.000000
n526 0.998400 0.000001
n527 0.977600 0.000001
n528 0.000000 0.000000
n529 0.988400 0.000037
n530 0.629400 0.202368
n531 0.000000 0.000000
n532 0.002200 0.248496
n533 0.002800 0.053861
n534 0.965600 0.000765
n535 0.994000 0.000001
n536 0.019600 0.000830
n537 0.002800 0.144940
n538 0.008400 0.000014
n539 0.181400 0.032234
n540 0.997000 0.008733
n541 0.997600 0.000000
n542 0.001600 0.230501
n543 0.004200 0.000041
n544 0.942600 0.001642
n545 0.001600 0.000006
n546 0.000000 0.000001
n547 0.001400 0.000249
n548 0.014000 0.018895
n549 0.994400 0.000000
n550 0.998400 0.181024
n551 0.000000 0.000000
n552 0.990600 0.000091
n553 0.948000 0.200131
n554 0.000200 0.000000
n555 0.000000 0.000003
n556 0.999800 0.000011
n557 0.999400 0.000004
n558 0.000000 0.000000
n559 0.014800 0.000011
n560 1.000000 0.000000
n561 1.000000 0.000765
n562 0.000000 0.000000
n563 0.000600 0.185376
n564 0.972000 0.000135
n565 0.006000 0.000001
n566 0.244600 0.093221
n567 0.007600 0.009102
n568 0.001200 0.000001
n569 0.003400 0.000014
n570 0.181600 0.030721
n571 0.001600 0.000016
n572 0.980000 0.034116
n573 0.006000 0.000255
n574 0.001200 0.000004
n575 0.992000 0.000000
n576 0.986800 0.000153
n577 0.993000 0.010326
n578 0.990200 0.044848
n579 0.997400 0.027042
n580 0.001200 0.000004
n581 0.004400 0.000019
n582 0.999600 0.000400
n583 0.000200 0.000000
n584 0.003000 0.000010
n585 0.000600 0.000000
n586 0.999600 0.024774
o_1_ 0.032000 0.069592
n588 0.005400 0.000056
n589 0.001800 0.126466
n590 0.043800 0.002277
n591 0.991000 0.000111
n592 0.001600 0.226375
n593 0.486600 0.000359
n594 0.989600 0.281765
n595 0.977200 0.000000
n596 0.026000 0.019823
n597 0.030800 0.237967
n598 0.996000 0.000000
n599 1.000000 0.000000
n600 0.003200 0.247939
n601 0.002000 0.000002
n602 0.008600 0.103910
n603 0.996800 0.000005
n604 0.000200 0.000000
n605 0.999800 0.000000
n606 1.000000 0.000002
n607 1.000000 0.000000
n608 0.000000 0.000099
n609 0.000200 0.076281
n610 0.999800 0.167820
o_2_ 0.237000 0.303482
n612 1.000000 0.255095
n613 0.869400 0.000001
n614 0.797000 0.000002
n615 0.646000 0.087836
n616 0.716200 0.049102
n617 0.070000 0.114336
n618 0.011400 0.000416
n619 0.019200 0.255465
n620 1.000000 0.000000
n621 0.989200 0.000145
n622 0.944200 0.005996
n623 0.023800 0.000065
n624 0.995400 0.001738
n625 0.902000 0.008206
n626 0.000200 0.000011
n627 0.910200 0.007352
n628 0.966000 0.035921
n629 0.998000 0.000161
n630 0.994000 0.000000
n631 0.023000 0.019872
n632 0.951000 0.046487
n633 0.948800 0.003589
n634 0.044400 0.002077
n635 0.039800 0.000019
n636 0.898800 0.162778
n637 0.000200 0.000015
n638 0.997600 0.000000
n639 0.989400 0.228063
n640 0.000000 0.000001
n641 0.276000 0.094945
n642 0.013800 0.185645
n643 0.000400 0.138614
n644 0.502200 0.150843
n645 0.999600 0.000000
n646 0.001800 0.119488
n647 0.005600 0.000019
n648 0.991600 0.000018
n649 0.984800 0.000000
n650 0.048600 0.007295
n651 0.007600 0.004766
n652 0.003400 0.280438
n653 0.999600 0.130579
n654 0.998600 0.000000
n655 0.999000 0.000002
n656 0.381600 0.038059
n657 0.000200 0.000000
n658 0.011400 0.000427
n659 0.001000 0.000013
n660 0.998800 0.000000

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@ -0,0 +1,575 @@
i_0_ 0.504400 0.505000
i_1_ 0.493000 0.499400
i_2_ 0.501000 0.511000
i_3_ 0.499400 0.501600
i_4_ 0.508400 0.509800
i_5_ 0.491000 0.500200
i_6_ 0.491600 0.503600
i_7_ 0.499600 0.498600
i_8_ 0.501800 0.495600
n28 0.000000 0.000000
o_1_ 0.109400 0.001396
n32 0.125200 0.027623
n33 0.245400 0.092023
n34 0.122000 0.027955
n35 0.128800 0.028038
n36 0.120000 0.027424
n37 0.128600 0.028415
n38 0.017000 0.000515
n39 0.014000 0.000517
n40 0.991000 0.000019
n41 0.003200 0.000302
n42 0.253400 0.094839
n43 0.130600 0.027424
n44 0.015400 0.000480
n45 0.013400 0.000525
n46 0.123000 0.026344
n47 0.014200 0.000495
n48 0.996600 0.026183
n49 0.123400 0.028415
n50 0.015200 0.000521
n51 0.003600 0.000028
n52 0.029000 0.001929
n53 0.123600 0.028541
n54 0.243000 0.091159
n55 0.128200 0.028541
n56 0.123400 0.027296
n57 0.974000 0.000081
n58 0.991400 0.012299
n59 0.993800 0.000272
n60 0.125400 0.027546
n61 0.251800 0.091404
n62 0.015600 0.000513
n63 0.125200 0.028038
n64 0.992600 0.026105
n65 0.244600 0.094556
n66 0.018200 0.000461
n67 0.001000 0.000009
n68 0.016600 0.000460
n69 0.006200 0.000277
n70 0.246400 0.094136
n71 0.250800 0.094659
n72 0.016800 0.000519
n73 0.988600 0.000097
n74 0.002200 0.000010
n75 0.124600 0.027546
n76 0.017800 0.000513
n77 0.002200 0.000028
n78 0.029800 0.001836
n79 0.993000 0.000637
n80 0.131400 0.027546
n81 0.015800 0.000503
n82 0.123000 0.029315
n83 0.017400 0.000522
n84 0.013600 0.000515
n85 0.989200 0.015808
n86 0.991800 0.179204
n87 0.015000 0.000491
n88 0.013800 0.000460
n89 0.014600 0.000476
n90 0.015000 0.000517
n91 0.002000 0.000008
n92 0.015800 0.000490
n93 0.014200 0.000493
n94 0.016400 0.000489
n95 0.992600 0.000680
n96 0.121000 0.026620
n97 0.017600 0.000540
n98 0.013000 0.000486
n99 0.015600 0.000463
n100 0.994400 0.027615
n101 0.017800 0.000527
n102 0.995600 0.026332
n103 0.011800 0.000513
o_2_ 0.392800 0.004866
n105 0.976800 0.044322
n106 0.989400 0.027905
n107 0.128000 0.028038
n108 0.016600 0.000460
n109 0.034800 0.001977
n110 0.993400 0.000500
n111 0.063200 0.007459
n112 0.064000 0.007578
n113 0.994000 0.026473
n114 0.017200 0.000466
n115 0.018000 0.000538
n116 0.956400 0.080573
n117 0.993400 0.000021
n118 0.030400 0.001943
n119 0.997000 0.026203
n120 0.997000 0.026244
n121 0.991200 0.000366
n122 0.013200 0.000524
n123 0.983200 0.000254
n124 0.932400 0.003943
n125 0.993200 0.028607
n126 0.256600 0.096659
n127 0.013000 0.000521
n128 0.943600 0.000001
n129 0.011200 0.000155
n130 0.254400 0.092023
n131 0.128200 0.027623
n132 0.010200 0.006964
n133 0.987600 0.091560
n134 0.127400 0.027293
n135 0.243400 0.090882
n136 0.992600 0.026686
n137 0.124800 0.027623
n138 0.028000 0.001761
n139 0.015000 0.000490
n140 0.905400 0.005237
n141 0.983600 0.092411
n142 0.987600 0.089702
n143 0.251000 0.093192
n144 0.252200 0.092951
n145 0.030000 0.001877
n146 0.015000 0.000479
n147 0.012000 0.000455
n148 0.251000 0.090555
n149 0.121600 0.025759
n150 0.970400 0.055415
n151 0.994600 0.026281
n152 0.019000 0.000540
n153 0.017800 0.000475
n154 0.015400 0.000493
n155 0.990600 0.090028
n156 0.247600 0.096893
n157 0.015200 0.000461
n158 0.122200 0.027713
n159 0.991800 0.026282
n160 0.015400 0.000458
n161 0.013800 0.000488
n162 0.014000 0.000495
n163 0.993400 0.024862
n164 0.015800 0.000513
n165 0.993200 0.000005
n166 0.001600 0.000006
n167 0.019000 0.000501
n168 0.993800 0.000003
n169 0.001200 0.000006
n170 0.011400 0.000458
n171 0.994000 0.027665
n172 0.995400 0.000943
n173 0.116800 0.028366
n174 0.132600 0.027973
n175 0.033400 0.001972
n176 0.017600 0.000458
n177 0.004200 0.000040
n178 0.248600 0.096659
n179 0.993000 0.063142
n180 0.015600 0.000538
n181 0.992400 0.028765
n182 0.018600 0.000501
n183 0.014600 0.000489
n184 0.990800 0.000002
n185 0.001000 0.000007
n186 0.001800 0.000010
n187 0.001800 0.000009
n188 0.017000 0.000490
n189 0.256000 0.096893
n190 0.016600 0.000508
n191 0.005000 0.000031
n192 0.002000 0.000007
n193 0.002000 0.000007
n194 0.885200 0.014300
n195 0.932000 0.000246
n196 0.961200 0.000035
n197 0.995600 0.027933
n198 0.988000 0.000405
n199 0.033200 0.001977
n200 0.983000 0.021348
n201 0.018800 0.000517
n202 0.014600 0.000082
n203 0.986600 0.171512
n204 0.931600 0.116050
n205 0.983600 0.000126
n206 0.997200 0.000450
n207 0.001600 0.000006
n208 0.990800 0.091488
n209 0.020200 0.000490
n210 0.012600 0.000521
n211 0.996200 0.026170
n212 0.994000 0.000842
n213 0.991400 0.001902
n214 0.992600 0.043426
n215 0.017200 0.000487
n216 0.989200 0.004753
n217 0.002400 0.089457
n218 0.996000 0.026375
n219 0.994400 0.253713
o_3_ 0.253000 0.001028
n221 0.991800 0.000018
n222 0.982000 0.000069
n223 0.001600 0.000007
n224 0.993200 0.000273
n225 0.991600 0.020355
n226 0.034000 0.001949
n227 0.980000 0.000084
n228 0.993200 0.000851
n229 0.997000 0.000362
n230 0.992600 0.000372
n231 0.994000 0.006957
n232 0.003600 0.000033
n233 0.000600 0.000006
n234 0.002000 0.000006
n235 0.997800 0.026426
n236 0.988200 0.124473
n237 0.029400 0.001961
n238 0.120200 0.028324
n239 0.989200 0.001780
n240 0.955000 0.002346
n241 0.002400 0.000005
n242 0.995000 0.026212
n243 0.992000 0.071193
n244 0.015000 0.000484
n245 0.992800 0.001249
n246 0.117200 0.026218
n247 0.029400 0.001905
n248 0.990600 0.000296
n249 0.247200 0.095758
n250 0.242000 0.094839
n251 0.014000 0.000462
n252 0.001600 0.000011
n253 0.994800 0.024911
n254 0.001600 0.000008
n255 0.951200 0.086443
n256 0.996400 0.000331
n257 0.030400 0.001869
n258 0.995600 0.029005
n259 0.989600 0.015055
n260 0.992400 0.090792
n261 0.994200 0.028683
n262 0.246200 0.091653
n263 0.994400 0.027764
n264 0.974200 0.000041
n265 0.995600 0.026095
n266 0.994800 0.024903
n267 0.991200 0.003353
n268 0.951400 0.009791
n269 0.993400 0.025602
n270 0.972200 0.052602
n271 0.996000 0.024658
n272 0.993000 0.000392
n273 0.002400 0.000027
n274 0.989200 0.000068
n275 0.031600 0.001989
n276 0.994800 0.007045
o_4_ 0.297000 0.001719
n278 0.895600 0.162379
n279 0.990800 0.000033
n280 0.995400 0.000570
n281 0.969800 0.056467
n282 0.994400 0.000229
n283 0.992400 0.000331
n284 0.996600 0.026226
n285 0.996200 0.026302
n286 0.993400 0.000373
n287 0.249600 0.093823
n288 0.250000 0.092951
n289 0.996800 0.000243
n290 0.981800 0.034860
n291 0.997400 0.028228
n292 0.995600 0.000058
n293 0.029200 0.002075
n294 0.996200 0.024840
n295 0.992600 0.000793
n296 0.014000 0.000486
n297 0.968400 0.058886
n298 0.996000 0.026631
n299 0.997000 0.028612
n300 0.993400 0.026054
n301 0.992600 0.000046
n302 0.994400 0.027752
n303 0.990400 0.000070
n304 0.002000 0.000008
n305 0.003400 0.000008
n306 0.028400 0.002051
n307 0.993400 0.000005
n308 0.995000 0.000821
n309 0.987600 0.007892
n310 0.917200 0.137535
n311 0.977200 0.000024
n312 0.014200 0.163494
n313 0.996200 0.000388
n314 0.993800 0.090997
n315 0.994000 0.000041
n316 0.961200 0.000024
n317 0.990000 0.026195
n318 0.017400 0.000500
n319 0.988800 0.001915
n320 0.953400 0.002400
n321 0.994400 0.028718
n322 0.992200 0.067620
n323 0.996400 0.000606
n324 0.962600 0.054766
n325 0.993200 0.089159
n326 0.994600 0.087093
n327 0.951000 0.002410
n328 0.994200 0.000229
n329 0.262000 0.094556
n330 0.994800 0.000201
n331 0.990200 0.025110
n332 0.002200 0.000011
n333 0.247000 0.088997
n334 0.993800 0.000025
n335 0.002600 0.000008
n336 0.967000 0.000184
n337 0.004000 0.000018
n338 0.002000 0.000010
n339 0.995600 0.027787
n340 0.990000 0.026131
n341 0.033600 0.001970
n342 0.995600 0.000592
n343 0.994600 0.061071
n344 0.994600 0.025674
n345 0.992800 0.088582
n346 0.031200 0.002019
n347 0.995400 0.026195
n348 0.993800 0.027783
n349 0.990400 0.001937
n350 0.966400 0.061577
n351 0.995400 0.026353
n352 0.995600 0.025715
n353 0.995000 0.000404
n354 0.993200 0.000299
n355 0.992800 0.000064
n356 0.123000 0.029263
n357 0.003400 0.000013
n358 0.985200 0.000014
n359 0.001400 0.000006
n360 0.996600 0.026199
n361 0.960600 0.072606
n362 0.994600 0.000216
n363 0.995600 0.090478
n364 0.015200 0.000455
n365 0.960000 0.072079
n366 0.994200 0.046113
n367 0.992800 0.086595
n368 0.959200 0.074103
n369 0.993200 0.000660
n370 0.990200 0.134607
n371 0.031400 0.001808
n372 0.981400 0.000039
n373 0.004000 0.000031
n374 0.995000 0.000263
n375 0.983200 0.005627
n376 0.026000 0.024331
n377 0.001800 0.000018
n378 0.996000 0.000311
n379 0.963800 0.066206
n380 0.996800 0.000463
n381 0.996400 0.000277
n382 0.996800 0.026305
n383 0.991800 0.065971
n384 0.001600 0.000010
n385 0.987800 0.000024
n386 0.003600 0.000037
n387 0.993400 0.043420
n388 0.969000 0.000110
n389 0.002800 0.000011
n390 0.992400 0.026279
n391 0.927600 0.121195
n392 0.992600 0.006354
n393 0.996800 0.027708
n394 0.981400 0.000215
n395 0.001600 0.000008
n396 0.003600 0.000029
n397 0.992200 0.000030
n398 0.002400 0.000009
n399 0.001400 0.000006
n400 0.996000 0.000501
n401 0.989800 0.000018
n402 0.002400 0.000011
n403 0.001400 0.000008
n404 0.989400 0.011878
n405 0.916000 0.138225
n406 0.992800 0.000014
n407 0.988400 0.000008
n408 0.005800 0.000118
n409 0.011400 0.003587
n410 0.002800 0.000009
n411 0.991800 0.000040
n412 0.991400 0.095598
n413 0.990200 0.000379
o_8_ 0.349800 0.002551
n415 0.924000 0.130524
n416 0.983400 0.032258
n417 0.983800 0.011813
n418 0.994000 0.000364
n419 0.980000 0.000014
n420 0.997000 0.026195
n421 0.994200 0.000324
n422 0.992800 0.121254
n423 0.992600 0.000010
n424 0.988600 0.006715
n425 0.003400 0.006246
n426 0.953400 0.000124
n427 0.994200 0.241129
n428 0.987000 0.007104
n429 0.996400 0.026356
n430 0.994800 0.000290
n431 0.004400 0.092593
o_9_ 0.403200 0.000043
n433 0.995600 0.095814
n434 0.993400 0.038196
n435 0.993600 0.024852
n436 0.130000 0.028115
n437 0.993800 0.044574
n438 0.013200 0.000453
n439 0.019000 0.000508
n440 0.989400 0.000015
n441 0.994000 0.003184
n442 0.891400 0.168369
n443 0.978600 0.040581
o_10_ 0.403800 0.000301
n445 0.978000 0.000044
n446 0.994400 0.025586
n447 0.001200 0.000009
n448 0.021400 0.004759
n449 0.004400 0.000029
n450 0.993800 0.000370
n451 0.953400 0.000054
n452 0.978800 0.209842
n453 0.994400 0.089826
n454 0.004200 0.000029
o_11_ 0.350600 0.002084
n456 0.962400 0.069158
n457 0.994200 0.001589
n458 0.840800 0.000140
n459 0.991400 0.046785
n460 0.870400 0.193841
n461 0.125400 0.027828
n462 0.990200 0.025435
n463 0.029400 0.001816
n464 0.031400 0.001794
n465 0.994600 0.007160
n466 0.996400 0.026214
n467 0.993600 0.007148
n468 0.955800 0.000567
n469 0.995000 0.000888
n470 0.994000 0.000270
o_12_ 0.317400 0.243163
n472 0.798600 0.250699
n473 0.990000 0.019603
n474 0.996200 0.027907
n475 0.869000 0.074324
n476 0.983200 0.000202
n477 0.988600 0.000689
n478 0.989000 0.000029
n479 0.995200 0.027583
n480 0.969000 0.000978
n481 0.994600 0.002785
n482 0.977400 0.000121
n483 0.008400 0.089927
n484 0.992000 0.028673
n485 0.990200 0.000009
o_13_ 0.307800 0.303413
n487 0.993800 0.000516
n488 0.995400 0.028651
n489 0.996600 0.026395
n490 0.979600 0.160741
n491 0.996000 0.028813
n492 0.995400 0.090836
o_14_ 0.341000 0.316198
n494 0.989200 0.000000
o_15_ 0.219200 0.000318
n496 0.930400 0.043796
n497 0.955000 0.122138
n498 0.965600 0.057609
n499 0.858600 0.028316
n500 0.993800 0.086371
n501 0.995200 0.002791
n502 0.997000 0.028222
n503 0.984800 0.000180
o_16_ 0.194000 0.027751
n505 0.993800 0.006763
n506 0.867000 0.000032
n507 0.994800 0.026079
o_17_ 0.172400 0.000018
n509 0.996400 0.027848
o_18_ 0.179600 0.000561
n511 0.979600 0.000500
n512 0.267400 0.086947
n513 0.985000 0.080272
n514 0.967200 0.000329
n515 0.991400 0.176143
n516 0.971600 0.000029
n517 0.053000 0.000308
n518 0.972400 0.000000
n519 0.815600 0.244911
n520 0.991000 0.024752
n521 0.961600 0.000106
n522 0.944800 0.002617
n523 0.986400 0.000006
n524 0.994800 0.000566
n525 0.956600 0.061465
n526 0.994200 0.038867
n527 0.968400 0.058976
n528 0.012200 0.000161
n529 0.967800 0.000110
n530 0.917600 0.000060
n531 0.990600 0.184160
n532 0.990800 0.000154
n533 0.978000 0.000126
n534 0.624400 0.058429
n535 0.982200 0.000008
n536 0.985600 0.009482
n537 0.993200 0.028683
n538 0.950000 0.000284
n539 0.013200 0.119947
n540 0.864800 0.001560
o_5_ 0.336200 0.008020
n542 0.994200 0.027847
n543 0.981600 0.000066
n544 0.104400 0.010183
n545 0.985600 0.040693
n546 0.952600 0.084627
n547 0.989800 0.000016
o_6_ 0.405200 0.002535
n549 0.983600 0.000160
n550 0.963000 0.068096
n551 0.850800 0.211876
n552 0.978600 0.020720
n553 0.988800 0.000082
n554 0.987200 0.123397
n555 0.969000 0.000184
o_7_ 0.362200 0.027373
n557 0.988000 0.045601
n558 0.967800 0.000073
n559 0.939400 0.000077
n560 0.515200 0.115410
n561 0.079600 0.086566
n562 0.962800 0.011938
n563 0.883600 0.000532
n564 0.989000 0.054625
n565 0.765600 0.272521
n566 0.963200 0.001389
n567 0.950000 0.000028
n568 0.991600 0.178580
n569 0.608600 0.058685
n570 0.845800 0.098692
n571 0.993400 0.000005
n572 0.958800 0.000768
n573 0.990400 0.000011
n574 0.963600 0.000164
n575 0.922600 0.000670
n576 0.992600 0.144436
n577 0.962000 0.069620
n578 0.880000 0.000415
n579 0.030800 0.000687
n580 0.962200 0.017248
n581 0.876800 0.001237
n582 0.993600 0.000739
n583 0.947000 0.000178
n584 0.971600 0.000000
n585 0.956800 0.051408
n586 0.924200 0.130560
n587 0.991000 0.025470
n588 0.981400 0.000101
n589 0.904000 0.153507
n590 0.995800 0.016707
n591 0.980400 0.000107
n592 0.994200 0.000569
n593 0.984200 0.000024
n594 0.918200 0.002910
o_0_ 0.000000 0.000000

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