Commit Graph

3704 Commits

Author SHA1 Message Date
tangxifan 0852ef33c3 remove caching for deps 2019-11-02 16:30:01 -06:00
Ganesh Gore f042c35edf Travis Experiments Squashed 2019-11-02 16:14:26 -06:00
tangxifan e1a7a2895a simulation ini file name can be customizable 2019-11-02 09:59:34 -06:00
tangxifan d5d7450ce7 make simulation ini writing as an option 2019-11-02 09:46:12 -06:00
tangxifan c3db880599 adding explicit file path to simulation info writer 2019-11-02 09:21:02 -06:00
tangxifan 358e9892ac reduce some error message to warnings 2019-11-02 00:09:13 -06:00
tangxifan 5bae8fecde add debugging mode to see why travis failed 2019-11-01 23:26:08 -06:00
Ganesh Gore 94b60b9714 Travis Test: Run 2 2019-11-01 23:12:56 -06:00
Ganesh Gore 5c8ca81645 Travis failure debug 2019-11-01 23:06:33 -06:00
tangxifan 495000c649 recover caching for libs 2019-11-01 21:37:17 -06:00
tangxifan 17f816effd try to uncache libini 2019-11-01 21:26:22 -06:00
tangxifan e9ed64c926 try to let cmake identify libini 2019-11-01 21:17:35 -06:00
tangxifan f811ddc62a Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-11-01 20:52:45 -06:00
tangxifan f70f387f9f minor tuning on ini compilation 2019-11-01 20:51:49 -06:00
Ganesh Gore a880802803 Bug Fix: Corrected read VPR stat filename 2019-11-01 20:51:05 -06:00
tangxifan a9c02cd2a5 fix errors in travis 2019-11-01 20:32:40 -06:00
tangxifan 550df19ee2 use a stable cmake now 2019-11-01 20:26:29 -06:00
tangxifan 3669a47d3b reworked the ini writer 2019-11-01 20:25:01 -06:00
tangxifan dab66b8be7 start adding auto check cpp files 2019-11-01 19:49:50 -06:00
tangxifan e2b042c61c Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-11-01 18:27:27 -06:00
Ganesh Gore 370a5ed408 Bug Fix: shifter ff.v include path to tcl script 2019-11-01 18:22:40 -06:00
Ganesh Gore 595d2d3070 Simple argument shuffle 2019-11-01 18:21:26 -06:00
Ganesh Gore 27005d6640 Added Modelsim Python Script 2019-11-01 18:20:40 -06:00
Ganesh Gore a0512e40b1 Created intermidiate file for modelsim simulation 2019-11-01 18:20:00 -06:00
tangxifan 4d4ef1113d give up iverilog on travis 2019-11-01 17:53:50 -06:00
tangxifan 1d78725d4d add installation 2019-11-01 17:48:17 -06:00
tangxifan 9a37b66d53 move installation to a script 2019-11-01 17:39:30 -06:00
tangxifan 161664f253 try to comfort iverilog package extraction 2019-11-01 17:24:06 -06:00
tangxifan 2dc3a4eb1f fixing bugs in iVerilog installation 2019-11-01 17:03:21 -06:00
tangxifan 5332588e82 retrying travis installation of iVerilog 10.3 2019-11-01 16:36:29 -06:00
tangxifan 3ae841b80f start refactoring auto-check top testbench generation 2019-11-01 16:33:12 -06:00
tangxifan b61b81b8d8 tuning iverilog version display 2019-11-01 15:29:08 -06:00
tangxifan d4fedb76d7 revert to default iverilog of Ubuntu 18.04 2019-11-01 15:24:58 -06:00
tangxifan b54bec1609 streamline regression tes 2019-11-01 15:23:38 -06:00
tangxifan 000f93ffd7 try to fix travis bugs 2019-11-01 15:19:34 -06:00
tangxifan 480478e545 reorganizing travis 2019-11-01 15:12:08 -06:00
tangxifan 8c0d60abd6 debugging travis 2019-11-01 15:00:33 -06:00
tangxifan c2cef205a4 update travis: try to compile iverilog through source 2019-11-01 14:52:42 -06:00
tangxifan b53a9b13bf update travis with installation 2019-11-01 14:03:55 -06:00
tangxifan 32953b0292 rework on Travis Scripts 2019-11-01 13:41:30 -06:00
tangxifan de0be72634 try to make travis install latest iVerilog 2019-11-01 13:25:29 -06:00
tangxifan a49010d2d3 reorganize the Travis regression test, temporarily shadow s298 2019-11-01 11:09:35 -06:00
tangxifan 49bfb3223c add compact routing to regression test 2019-11-01 10:53:47 -06:00
tangxifan 139ea8b3e3 add s298 single mode arch to Travis 2019-11-01 10:49:37 -06:00
tangxifan 531cc064fc bug fixing for formal top-level testbench 2019-11-01 10:47:40 -06:00
Ganesh Gore da0778e813 Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev 2019-11-01 00:46:34 -06:00
tangxifan d709868463 adding more regression tests which is quick run but very helpful for debugging 2019-10-31 20:17:40 -06:00
tangxifan 2dff779005 critical bug fixed for bitstream generation for offset truth tables 2019-10-31 20:16:08 -06:00
tangxifan a6a3e7c36b adding mcnc_big20 to regression test 2019-10-31 19:31:27 -06:00
Ganesh Gore 81180939ca Bug fix: Missing exit_if_fail flag in fpga_flow script 2019-10-31 09:56:57 -06:00