add XML parsing for device model library settings

This commit is contained in:
tangxifan 2020-01-17 17:15:58 -07:00
parent 88a96673e3
commit d58186507c
3 changed files with 6 additions and 6 deletions

View File

@ -11,13 +11,13 @@
<technology_library>
<device_library>
<device_model name="logic" type="transistor">
<lib type="academia" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="0.9" pn_ratio="2"/>
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</device_model>
<device_model name="io" type="transistor"/>
<lib type="academia" corner="TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<device_model name="io" type="transistor">
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="2.5" pn_ratio="3"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>

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@ -321,7 +321,7 @@ void TechnologyLibrary::set_model_ref(const TechnologyModelId& model_id,
/* Set the library file path of a model in the library */
void TechnologyLibrary::set_model_lib_path(const TechnologyModelId& model_id,
const std::string& lib_path) {
const std::string& lib_path) {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
model_lib_paths_[model_id] = lib_path;

View File

@ -26,8 +26,8 @@
* State University (ASU). Available at ptm.asu.edu
*******************************************************************/
enum e_tech_lib_type {
TECH_LIB_MODEL_INDUSTRY,
TECH_LIB_MODEL_ACADEMIA,
TECH_LIB_INDUSTRY,
TECH_LIB_ACADEMIA,
NUM_TECH_LIB_TYPES
};
/* Strings correspond to each technology library type */