reorganize and clean-up sample architecture
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@ -255,9 +255,18 @@
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</circuit_library>
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</openfpga_architecture>
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<openfpga_simulation_setting>
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<general sim_temp="25" post="false" captab="false" fast="true"/>
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<monte_carlo mc_sim="false" num_mc_points="2"/>
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<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
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<clock_setting>
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<operating frequency="200e6" num_cycles="auto" slack="0.2"/>
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<programming frequency="10e6"/>
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</clock_setting>
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<simulator_option>
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<operating_condition temperature="25"/>
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<output_log post="false" captab="false"/>
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<accuracy type="abs" value="1e-13"/>
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<runtime fast_simulation="true"/>
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</simulator_option>
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<monte_carlo num_simulation_points="2"/>
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<measurement_setting>
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<slew>
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<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
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<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
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@ -266,15 +275,15 @@
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<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
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<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
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</delay>
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</measure>
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<stimuli>
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<clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6">
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</measurement_setting>
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<stimulus>
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<stimuli type="clock">
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<rise slew_time="20e-12" slew_type="abs"/>
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<fall slew_time="20e-12" slew_type="abs"/>
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</clock>
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<input>
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</stimuli>
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<stimuli type="input">
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<rise slew_time="25e-12" slew_type="abs"/>
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<fall slew_time="25e-12" slew_type="abs"/>
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</input>
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</stimuli>
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</stimuli>
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</stimulus>
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</openfpga_simulation_setting>
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