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add XML parsing for wire parasitics in circuit model

This commit is contained in:
tangxifan 2020-01-15 19:54:57 -07:00
parent 999c364b25
commit 602d0bde4c
3 changed files with 58 additions and 3 deletions
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4
libopenfpga/libarchopenfpga/arch/sample_arch.xml
View File

@ -111,7 +111,7 @@
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/>
@ -119,7 +119,7 @@
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>

2
libopenfpga/libarchopenfpga/src/circuit_types.h
View File

@ -79,7 +79,7 @@ enum e_circuit_model_gate_type {
};
enum e_wire_model_type {
WIRE_MODEL_PIE,
WIRE_MODEL_PI,
WIRE_MODEL_T,
NUM_WIRE_MODEL_TYPES
};

55
libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
View File

@ -210,6 +210,22 @@ e_circuit_model_port_type string_to_circuit_model_port_type(const std::string& t
return NUM_CIRCUIT_MODEL_PORT_TYPES;
}
/********************************************************************
* Convert string to the enumerate of wire model type
*******************************************************************/
static
e_wire_model_type string_to_wire_model_type(const std::string& type_string) {
if (std::string("pi") == type_string) {
return WIRE_MODEL_PI;
}
if (std::string("t") == type_string) {
return WIRE_MODEL_T;
}
return NUM_WIRE_MODEL_TYPES;
}
/********************************************************************
* Parse XML codes of design technology of a circuit model to circuit library
*******************************************************************/
@ -513,6 +529,36 @@ void read_xml_circuit_port(pugi::xml_node& xml_port,
}
}
/********************************************************************
* This is a generic function to parse XML codes that describe
* RC parasitics for wire circuit model to circuit library
*******************************************************************/
static
void read_xml_wire_param(pugi::xml_node& xml_wire_param,
const pugiutil::loc_data& loc_data,
CircuitLibrary& circuit_lib, const CircuitModelId& model) {
/* Find the type of the wire model */
const char* type_attr = get_attribute(xml_wire_param, "model_type", loc_data).value();
/* Translate the type of circuit model to enumerate */
e_wire_model_type wire_model_type = string_to_wire_model_type(std::string(type_attr));
if (NUM_WIRE_MODEL_TYPES == wire_model_type) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_wire_param),
"Invalid 'type' attribute '%s'\n",
type_attr);
}
circuit_lib.set_wire_type(model, wire_model_type);
/* Parse the R and C values */
circuit_lib.set_wire_r(model, get_attribute(xml_wire_param, "R", loc_data).as_float(0.));
circuit_lib.set_wire_c(model, get_attribute(xml_wire_param, "C", loc_data).as_float(0.));
/* Parse the number of levels for the wire model */
circuit_lib.set_wire_num_levels(model, get_attribute(xml_wire_param, "num_level", loc_data).as_int(0));
}
/********************************************************************
* Parse XML codes of a circuit model to circuit library
*******************************************************************/
@ -625,6 +671,15 @@ void read_xml_circuit_model(pugi::xml_node& xml_model,
auto xml_port = get_first_child(xml_model, "port", loc_data);
read_xml_circuit_port(xml_port, loc_data, circuit_lib, model);
}
/* Parse the parasitics of wires */
if ( (CIRCUIT_MODEL_WIRE == circuit_lib.model_type(model))
|| (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) ) {
auto xml_wire_param = get_single_child(xml_model, "wire_param", loc_data);
read_xml_wire_param(xml_wire_param, loc_data, circuit_lib, model);
}
/* Parse the delay matrix if defined */
}
/********************************************************************