coolbreeze413
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b86bd1ca68
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re-enable counter_5clock,sdc_controller, lut_adder tests
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2021-11-19 18:06:06 +05:30 |
tangxifan
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e9468eedbf
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Merge pull request #420 from lnis-uofu/enable-all-quicklogic-tests
Enable all quicklogic tests
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2021-11-18 21:07:08 -08:00 |
tangxifan
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773d45258a
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Merge pull request #38 from RapidSilicon/update_from_upstream
Pulling refs/heads/update_from_upstream into master
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2021-11-18 09:19:42 -08:00 |
coolbreeze413
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68008f742c
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Merge branch 'master' into enable-all-quicklogic-tests
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2021-11-18 18:40:43 +05:30 |
coolbreeze413
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31379062e3
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remove minor comments
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2021-11-18 18:40:15 +05:30 |
nadeemyaseen-rs
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1ea56b2d18
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-11-18 00:00:55 +05:00 |
tangxifan
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1aa411a6f3
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Merge pull request #408 from lnis-uofu/yosys-symbiflow-plugins-integration
add plugins, set yosys install for plugin
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2021-11-17 11:00:44 -08:00 |
coolbreeze413
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91094305bd
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enable all tests except 15 and 19
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2021-11-17 20:56:12 +05:30 |
coolbreeze413
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5293ba8357
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update yosys-symbiflow-plugins to latest to fix quicklogic tests
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2021-11-17 15:43:45 +05:30 |
coolbreeze413
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264023c2c9
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remove clean step in compilation of yosys/plugins to check CI
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2021-11-15 21:41:17 +05:30 |
Lalit Sharma
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756b64671b
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Fixing yosys checkout error
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2021-11-12 02:33:25 -08:00 |
Lalit Sharma
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fe74c42252
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Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure
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2021-11-12 01:46:06 -08:00 |
Lalit Sharma
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7b611601fc
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Bumping up changes to submodule yosys-plugins
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2021-11-12 01:14:01 -08:00 |
coolbreeze413
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840fa399c6
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enable single counter test (fails, needs debug)
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2021-11-09 21:36:33 +05:30 |
coolbreeze413
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a823c3e143
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remove clean step in build to avoid long compilation times
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2021-11-04 10:19:25 +05:30 |
coolbreeze413
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192eb1e655
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correct yosys paths for CI
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2021-11-04 09:11:57 +05:30 |
coolbreeze413
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d2ce4579cf
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add yosys-symbiflow-plugins submodule
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2021-11-04 07:54:44 +05:30 |
coolbreeze413
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3fa373f8bc
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add plugins, set yosys install for plugin
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2021-11-04 07:22:09 +05:30 |
ganeshgore
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a42342fa9e
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Merge pull request #402 from lnis-uofu/yosys+verific_support
Adding Yosys+Verific support.
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2021-11-02 15:22:48 -06:00 |
tangxifan
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f86b6960e2
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Merge pull request #36 from RapidSilicon/upstream
Upstream
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2021-11-01 10:39:13 -07:00 |
Aram Kostanyan
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a707226ba6
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Added 'basic_tests/verific_test' test case into regression tests suite.
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2021-11-01 18:33:33 +05:00 |
Aram Kostanyan
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b332a5a1b4
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Added 'basic_tests/verific_test' test-case.
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2021-11-01 18:20:57 +05:00 |
tangxifan
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ff264c00a2
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
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2021-10-31 11:51:34 -07:00 |
tangxifan
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0d882f57b1
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Merge branch 'master' into yosys+verific_support
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2021-10-30 22:49:21 -07:00 |
tangxifan
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4e50644ea8
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Merge pull request #403 from lnis-uofu/yosyshq
Use Yosys HQ v0.10 as a submodule
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2021-10-30 20:57:49 -07:00 |
tangxifan
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0d14aa4cb8
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[Flow] Add comments to clarify the limitations
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2021-10-30 19:17:11 -07:00 |
tangxifan
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7f999d03c6
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[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade
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2021-10-30 18:05:39 -07:00 |
tangxifan
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370e3fef83
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[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks
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2021-10-30 18:03:59 -07:00 |
tangxifan
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7455990ead
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[Flow] bug fix
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2021-10-30 16:52:32 -07:00 |
tangxifan
|
c8e9dfbeda
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[Test] bug fix
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2021-10-30 16:50:57 -07:00 |
tangxifan
|
27b82d1473
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[Flow] bug fix
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2021-10-30 16:09:31 -07:00 |
tangxifan
|
a4cfc84930
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[Test] Bug fix
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2021-10-30 16:00:47 -07:00 |
tangxifan
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335347a74f
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[Test] Bug fix
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2021-10-30 15:48:25 -07:00 |
tangxifan
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6277234125
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[Flow] bug fix in BRAM-oriented yosys scripts
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2021-10-30 15:34:30 -07:00 |
tangxifan
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be47e78289
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[Arch] Change arch for Sapone test
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2021-10-30 15:23:19 -07:00 |
tangxifan
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e6cc3c4942
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[Flow] Enable flatten for dff-related yosys scripts
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2021-10-30 15:12:34 -07:00 |
tangxifan
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ad5cce0ae8
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[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
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2021-10-30 15:11:07 -07:00 |
tangxifan
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8dea7e80e6
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[Flow] Update yosys script to not use sdff and dffe
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2021-10-30 14:56:54 -07:00 |
tangxifan
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40d11a45d9
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[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
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2021-10-30 14:49:56 -07:00 |
tangxifan
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b7ad61227d
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[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
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2021-10-30 14:47:37 -07:00 |
tangxifan
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ec184ef532
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[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
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2021-10-30 14:46:12 -07:00 |
tangxifan
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0b770f3330
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[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
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2021-10-30 14:36:43 -07:00 |
tangxifan
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59a622a910
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[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
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2021-10-30 14:34:37 -07:00 |
tangxifan
|
978c60e75b
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[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
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2021-10-30 13:29:38 -07:00 |
tangxifan
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18bab18032
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[Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release
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2021-10-30 13:20:58 -07:00 |
tangxifan
|
16de60e943
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[Test] Turn off ACE2 run in bitstream generation only flows
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2021-10-30 12:31:14 -07:00 |
tangxifan
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94328351be
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[Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts
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2021-10-30 12:00:06 -07:00 |
tangxifan
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91627abe12
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[FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided
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2021-10-30 11:53:46 -07:00 |
tangxifan
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0a449cc24c
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[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected
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2021-10-30 11:45:01 -07:00 |
tangxifan
|
9c06041ce4
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[Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff`
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2021-10-30 11:27:40 -07:00 |