Merge pull request #408 from lnis-uofu/yosys-symbiflow-plugins-integration

add plugins, set yosys install for plugin

.dockerignore

@@ -12,12 +12,12 @@
 !/openfpga/openfpga
 !/vpr/libvpr.a
 !/vpr/vpr
-!/yosys/share/
-!/yosys/yosys
-!/yosys/yosys-abc
-!/yosys/yosys-config
-!/yosys/yosys-filterlib
-!/yosys/yosys-smtbmc
+!/yosys/install/share/
+!/yosys/install/bin/yosys
+!/yosys/install/bin/yosys-abc
+!/yosys/install/bin/yosys-config
+!/yosys/install/bin/yosys-filterlib
+!/yosys/install/bin/yosys-smtbmc
 !/openfpga_flow
 !/openfpga.sh
 !/openfpga_flow/

.github/workflows/build.yml

@@ -170,12 +170,12 @@ jobs:
             openfpga/openfpga
             vpr/libvpr.a
             vpr/vpr
-            yosys/share/
-            yosys/yosys
-            yosys/yosys-abc
-            yosys/yosys-config
-            yosys/yosys-filterlib
-            yosys/yosys-smtbmc
+            yosys/install/share/
+            yosys/install/bin/yosys
+            yosys/install/bin/yosys-abc
+            yosys/install/bin/yosys-config
+            yosys/install/bin/yosys-filterlib
+            yosys/install/bin/yosys-smtbmc
             openfpga_flow
             openfpga.sh
   docker_distribution:
@@ -240,11 +240,11 @@ jobs:
           chmod +x ace2/ace
           chmod +x openfpga/openfpga
           chmod +x vpr/vpr
-          chmod +x yosys/yosys
-          chmod +x yosys/yosys-abc
-          chmod +x yosys/yosys-config
-          chmod +x yosys/yosys-filterlib
-          chmod +x yosys/yosys-smtbmc
+          chmod +x yosys/install/bin/yosys
+          chmod +x yosys/install/bin/yosys-abc
+          chmod +x yosys/install/bin/yosys-config
+          chmod +x yosys/install/bin/yosys-filterlib
+          chmod +x yosys/install/bin/yosys-smtbmc
       - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 18.04)
         shell: bash
         run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh

.gitmodules

@@ -1,4 +1,8 @@
 [submodule "yosys"]
 	path = yosys
 	url = https://github.com/YosysHQ/yosys
-    branch = release-branch-0.10
+	branch = release-branch-0.10
+	ignore = dirty
+[submodule "yosys-plugins"]
+	path = yosys-plugins
+	url = https://github.com/SymbiFlow/yosys-symbiflow-plugins

CMakeLists.txt

@@ -231,13 +231,24 @@ include(CheckCXXCompilerFlag)
 add_custom_target(
     yosys ALL 
     COMMAND $(MAKE) config-gcc
-    COMMAND $(MAKE) 
+    COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install
     WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys
     COMMENT "Compile Yosys with given Makefile"
 )
 
 # yosys compilation ends
 
+# yosys-plugins compilation starts
+add_custom_target(
+    yosys-plugins ALL
+    COMMAND $(MAKE) install_ql-qlf YOSYS_PATH=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install EXTRA_FLAGS="-DPASS_NAME=synth_ql"
+    WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys-plugins
+    DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/yosys/install/bin/yosys
+    COMMENT "Compile Yosys-plugins with given Makefile"
+)
+
+add_dependencies(yosys-plugins yosys)
+
 # run make to extract compiler options, linker options and list of source files
 #add_custom_target(
 #  yosys

Makefile

@@ -21,7 +21,7 @@ compile:
 	cd build && $(MAKE)
 
 clean:
-	rm -rf build
+	rm -rf build yosys/install
 
 build/Makefile:
 	make checkout

docker/Dockerfile.master

@@ -3,7 +3,7 @@ RUN mkdir -p /opt/openfpga
 WORKDIR /opt/openfpga
 COPY . /opt/openfpga
 RUN chmod +x abc/abc ace2/ace openfpga/openfpga vpr/vpr
-RUN chmod +x yosys/yosys yosys/yosys-abc yosys/yosys-config yosys/yosys-filterlib yosys/yosys-smtbmc
-ENV PATH="/opt/openfpga/openfpga:/opt/openfpga/yosys:${PATH}"
+RUN chmod +x yosys/install/bin/yosys yosys/install/bin/yosys-abc yosys/install/bin/yosys-config yosys/install/bin/yosys-filterlib yosys/install/bin/yosys-smtbmc
+ENV PATH="/opt/openfpga/openfpga:/opt/openfpga/yosys/install/bin:${PATH}"
 ENV PATH="/opt/openfpga/ace2:/opt/openfpga/abc:/opt/openfpga/vpr:${PATH}"
 ENV OPENFPGA_PATH="/opt/openfpga"

openfpga_flow/misc/fpgaflow_default_tool_path.conf

@@ -1,10 +1,10 @@
 # Standard Configuration Example
 [CAD_TOOLS_PATH]
 openfpga_shell_path = ${PATH:OPENFPGA_PATH}/openfpga/openfpga
-yosys_path = ${PATH:OPENFPGA_PATH}/yosys/yosys
+yosys_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys
 misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
 odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
-abc_path = ${PATH:OPENFPGA_PATH}/yosys/yosys-abc
+abc_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys-abc
 abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
 abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
 vpr_path = ${PATH:OPENFPGA_PATH}/vpr/vpr

openfpga_flow/misc/qlf_yosys.ys

@@ -1,7 +1,10 @@
 # Yosys synthesis script for ${TOP_MODULE}
+
+plugin -i ql-qlf
+
 # Read verilog files
 ${READ_VERILOG_FILE}
 
-synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}
+synth_ql -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}
 
 write_verilog -noattr -nohex ${OUTPUT_VERILOG}

openfpga_flow/regression_test_scripts/quicklogic_reg_test.sh

@@ -10,9 +10,9 @@ echo -e "QuickLogic regression tests";
 
 # TODO: Disabled all the tests here because Quicklogic's synthesis script is not in Yosys v0.10 release. Will bring back once Quicklogic manages to merge their contribution to Yosys upstream
 
-##echo -e "Testing yosys flow using custom ys script for running quicklogic device";
-##run-task quicklogic_tests/flow_test --debug --show_thread_logs
-##
+echo -e "Testing yosys flow using custom ys script for running quicklogic device";
+run-task quicklogic_tests/flow_test --debug --show_thread_logs
+
 ##echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device";
 ##run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs
 ##run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs

openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf

@@ -26,58 +26,58 @@ yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/io_tc1/rtl/*.v
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/unsigned_mult_80/rtl/*.v
-bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/bin2bcd/bin2bcd.v
+#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/io_tc1/rtl/*.v
+#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/unsigned_mult_80/rtl/*.v
+#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/bin2bcd/bin2bcd.v
 bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter/counter.v
-bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v
-bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v
-bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v
+#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v
+#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v
+#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v
 #cavlc_top requires async reset/preset
 #bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v
-bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v
+#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v
 # counter120bitx5 requires 5 clocks
 #bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter120bitx5/rtl/*.v
-bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter_16bit/rtl/*.v
-bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/dct_mac/rtl/*.v
-bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/des_perf/rtl/*.v
-bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f_systemC/rtl/*.v
+#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter_16bit/rtl/*.v
+#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/dct_mac/rtl/*.v
+#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/des_perf/rtl/*.v
+#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f_systemC/rtl/*.v
 #i2c_master_top requires async reset/preset
 #bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v
 #iir requires async reset/preset
 #bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v
 #jpeg_qnr requires async reset/preset
 #bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v
-bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v
+#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v
 # sdc_controller requires 4 clocks
 #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v
 
 [SYNTHESIS_PARAM]
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
 
-bench0_top = io_tc1
-bench1_top = unsigned_mult_80
-bench2_top = bin2bcd
+#bench0_top = io_tc1
+#bench1_top = unsigned_mult_80
+#bench2_top = bin2bcd
 bench3_top = counter
-bench5_top = rs_decoder_top
-bench6_top = top_module
-bench7_top = sha256 
-bench8_top = cavlc_top
+#bench5_top = rs_decoder_top
+#bench6_top = top_module
+#bench7_top = sha256 
+#bench8_top = cavlc_top
 #bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
-bench9_top = cf_fft_256_8
+#bench9_top = cf_fft_256_8
 #bench10_top = counter120bitx5
 #bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
-bench11_top = top
-bench12_top = dct_mac 
-bench13_top = des_perf
-bench14_top = diffeq_f_systemC 
-bench15_top = i2c_master_top 
+#bench11_top = top
+#bench12_top = dct_mac 
+#bench13_top = des_perf
+#bench14_top = diffeq_f_systemC 
+#bench15_top = i2c_master_top 
 #bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
-bench16_top = iir
+#bench16_top = iir
 #bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
-bench17_top = jpeg_qnr
+#bench17_top = jpeg_qnr
 #bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
-bench18_top = multi_enc_decx2x4 
+#bench18_top = multi_enc_decx2x4 
 # sdc_controller requires 4 clocks
 #bench19_top = sdc_controller
 #bench19_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys

yosys-plugins

@@ -0,0 +1 @@
+Subproject commit c44f188756783b2a9bc7197a0c72fd3f3698da1f