tangxifan
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b374056e78
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fix bug in duplicate pin addition
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2019-12-26 16:24:05 -07:00 |
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tangxifan
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7eb7be2084
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added duplicated pin support to build top module
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2019-12-26 15:02:27 -07:00 |
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tangxifan
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a28fc3013c
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reorganize the top module builder
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2019-12-26 14:37:36 -07:00 |
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tangxifan
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2306b17d9f
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added pin duplication support to grid module builder
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2019-12-25 22:24:44 -07:00 |
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tangxifan
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72d2fc6d69
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add entry to new functions for pin duplication
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2019-12-25 20:24:41 -07:00 |
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tangxifan
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d0aed4eb66
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add new option: duplicate_grid_pin
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2019-12-25 19:46:58 -07:00 |
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tangxifan
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868c573e59
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remove unused codes and parameters
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2019-12-24 20:43:29 -07:00 |
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tangxifan
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5445047863
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renamed grid and routing track naming, which are now independent from coordinates
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2019-12-24 20:17:11 -07:00 |
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tangxifan
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0eebdaf942
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add grid port naming function for modules
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2019-12-24 15:07:03 -07:00 |
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tangxifan
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43e78585ba
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add routing track naming function for unique modules
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2019-12-24 14:55:17 -07:00 |
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tangxifan
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a36cb676c2
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minor fix in ctags to include library source files
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2019-12-18 22:24:58 +08:00 |
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tangxifan
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a04631305c
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remove legacy verilog utils functions
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2019-12-04 18:02:26 -07:00 |
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tangxifan
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73386dd1a9
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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tangxifan
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a176c253ee
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remove legacy codes in FPGA-Verilog: routing block generation
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2019-12-04 16:15:50 -07:00 |
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tangxifan
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95ea513339
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move refactored Verilog routing block generation functions to cpp files
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2019-12-04 16:09:27 -07:00 |
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tangxifan
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322228de43
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remove legacy codes in FPGA-Verilog
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2019-12-04 16:02:43 -07:00 |
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tangxifan
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0dd72999d5
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deleting legacy codes: fpga_verilog top-level function
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2019-12-04 15:55:16 -07:00 |
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tangxifan
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0daf170e45
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refactored all the new functions to new source files, ready to delete legacy codes
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2019-12-04 15:38:42 -07:00 |
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tangxifan
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099863a956
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make FPGA-X2P to be run conditionally
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2019-12-03 13:50:39 -07:00 |
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tangxifan
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0c2ad5ab5e
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critical bug fixed for some corner cases
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2019-11-13 20:45:41 -07:00 |
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tangxifan
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1291b99d66
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now make ini file generation more flexible: user can specify a name or use the default name
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2019-11-13 12:55:57 -07:00 |
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tangxifan
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d84cd66287
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refactored analysis SDC generator for grids
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2019-11-12 22:18:13 -07:00 |
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tangxifan
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6c58a4dd92
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refactored unused grid block SDC analysis generation
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2019-11-12 10:01:17 -07:00 |
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tangxifan
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8a57a29d2d
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refactoring analysis SDC generation for grids
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2019-11-11 22:38:11 -07:00 |
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tangxifan
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5f219b428c
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refactored analysis SDC generation for switch blocks
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2019-11-11 19:24:39 -07:00 |
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tangxifan
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876733f052
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now we use module manager to generate analysis SDC, being independent from VPR structures
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2019-11-10 21:15:34 -07:00 |
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tangxifan
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a849522be9
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refactored CB SDC analysis generation
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2019-11-10 20:15:16 -07:00 |
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tangxifan
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8e8e59b0ca
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give specific name to mux so that we can bind it to SDC generator
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2019-11-10 19:42:30 -07:00 |
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tangxifan
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3d711823e5
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refactoring SDC generator for unused CBs
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2019-11-10 18:15:13 -07:00 |
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tangxifan
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67b3b25bea
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refactoring analysis sdc generation
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2019-11-10 16:08:49 -07:00 |
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tangxifan
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1f368abfbe
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refactoring analysis SDC generation
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2019-11-10 15:40:54 -07:00 |
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tangxifan
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bcd8237263
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refactored grid PnR SDC generator
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2019-11-09 20:57:54 -07:00 |
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tangxifan
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d226d18d40
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move SDC generator for routing modules to an independent source file
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2019-11-09 11:54:05 -07:00 |
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tangxifan
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a7f2a61d0d
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refactored CB SDC generation
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2019-11-09 11:42:38 -07:00 |
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tangxifan
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4b5ecc516b
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refactored SDC SB constrain generation
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2019-11-09 10:52:15 -07:00 |
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tangxifan
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be574b0d45
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refactored disable routing mux outputs
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2019-11-08 19:05:05 -07:00 |
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tangxifan
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e273c00c9d
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add refactored disable timing for memory cells
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2019-11-08 17:38:07 -07:00 |
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tangxifan
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ea7c981c85
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critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer
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2019-11-08 15:01:30 -07:00 |
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tangxifan
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33b3705ced
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refactoring disable outputs sdc generation
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2019-11-08 11:15:35 -07:00 |
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tangxifan
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35e718b32d
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rename backend sdc generator to be backend assistant
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2019-11-08 10:20:12 -07:00 |
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tangxifan
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14e7744fee
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start refactoring sdc generator, make it geneirc by placing it in parallel to Verilog generator
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2019-11-07 22:20:48 -07:00 |
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tangxifan
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56b4ee008e
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add test for heterogeneous FPGA and fix bugs
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2019-11-06 17:45:11 -07:00 |
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tangxifan
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4ea5756be6
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bug fixed for std cell MUX2 architecture and add the case to regression tests
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2019-11-06 16:06:47 -07:00 |
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tangxifan
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09eb373a6e
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bug fixing for autocheck top testbench where clock port is not default names
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2019-11-06 12:21:20 -07:00 |
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tangxifan
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0e620f35a4
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bug fixed for MUX2 std cells, avoid duplicated module writing
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2019-11-06 11:45:28 -07:00 |
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tangxifan
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aac4ccb279
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fixing bug for heterogeneous FPGAs
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2019-11-06 11:19:17 -07:00 |
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tangxifan
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6c04b8d959
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bug fixing for heterogeneous FPGAs
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2019-11-05 20:24:03 -07:00 |
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tangxifan
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066962fbb9
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bug fixed for clb2clb direct connection
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2019-11-05 17:41:21 -07:00 |
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tangxifan
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227fb9a1a5
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clean up the support for std cells
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2019-11-05 17:32:05 -07:00 |
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tangxifan
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aa56d95073
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bug fixed for using standard cells
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2019-11-05 17:19:57 -07:00 |