add new option: duplicate_grid_pin

vpr7_x2p/vpr/SRC/base/OptionTokens.c

@@ -65,6 +65,7 @@ struct s_TokenPair OptionBaseTokenList[] = {
         { "fpga_x2p_sim_window_size", OT_FPGA_X2P_SIM_WINDOW_SIZE }, /* Window size in determining number of clock cycles in simulation */
         { "fpga_x2p_compact_routing_hierarchy", OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY }, /* use a compact routing hierarchy in SPICE/Verilog generation */
         { "fpga_x2p_output_sb_xml", OT_FPGA_X2P_OUTPUT_SB_XML }, /* use a compact routing hierarchy in SPICE/Verilog generation */
+        { "fpga_x2p_duplicate_grid_pin", OT_FPGA_X2P_DUPLICATE_GRID_PIN }, /* Duplicate the pins at each side of a grid when generating SPICE and Verilog netlists */
         /* Xifan TANG: FPGA SPICE Support */
         { "fpga_spice", OT_FPGA_SPICE },/* Xifan TANG: SPICE Model Support, turn on the functionality*/
         { "fpga_spice_dir", OT_FPGA_SPICE_DIR },/* Xifan TANG: SPICE Model Support, directory of spice netlists*/

vpr7_x2p/vpr/SRC/base/OptionTokens.h

@@ -82,6 +82,7 @@ enum e_OptionBaseToken {
     OT_FPGA_X2P_SIM_WINDOW_SIZE, /* Window size in determining number of clock cycles in simulation */
     OT_FPGA_X2P_COMPACT_ROUTING_HIERARCHY, /* use a compact routing hierarchy in SPICE/Verilog generation */
     OT_FPGA_X2P_OUTPUT_SB_XML, /* output switch blocks to XML files */
+    OT_FPGA_X2P_DUPLICATE_GRID_PIN, /* Duplicate the pins at each side of a grid when generating SPICE and Verilog netlists */
     /* Xifan TANG: FPGA SPICE Support */
     OT_FPGA_SPICE, /* Xifan TANG: FPGA SPICE Model Support */
     OT_FPGA_SPICE_DIR, /* Xifan TANG: FPGA SPICE Model Support */

vpr7_x2p/vpr/SRC/base/ReadOptions.c

@@ -491,6 +491,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) {
     case OT_FPGA_X2P_OUTPUT_SB_XML: 
       /* Read the file prefix to output SB XML files */
       return ReadString(Args, &Options->sb_xml_dir);
+    case OT_FPGA_X2P_DUPLICATE_GRID_PIN:
+      return Args;
     /* Xifan TANG: FPGA SPICE Model Options*/
     case OT_FPGA_SPICE:
       return Args;

vpr7_x2p/vpr/SRC/base/SetupVPR.c

@@ -1275,6 +1275,12 @@ static void SetupFpgaSpiceOpts(t_options Options,
     fpga_spice_opts->sb_xml_dir = Options.sb_xml_dir;
   }
 
+  /* Check if user wants to duplicate the pin at each side of grids */
+  fpga_spice_opts->duplicate_grid_pin = FALSE;
+  if (Options.Count[OT_FPGA_X2P_DUPLICATE_GRID_PIN]) { 
+    fpga_spice_opts->duplicate_grid_pin = TRUE;
+  }
+
   /* Decide if we need to do FPGA-SPICE */
   fpga_spice_opts->do_fpga_spice = FALSE;
   if (( TRUE == fpga_spice_opts->SpiceOpts.do_spice)

vpr7_x2p/vpr/SRC/base/vpr_api.c

@@ -175,6 +175,7 @@ void vpr_print_usage(void) {
   vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_sim_window_size <float>\n");
   vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_compact_routing_hierarchy\n");
   vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_output_sb_xml <directory_path_output_switch_block_XML>\n");
+  vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_x2p_duplicate_grid_pin\n");
   vpr_printf(TIO_MESSAGE_INFO, "SPICE Support Options:\n");
   vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice\n");
   vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_spice_dir <directory_path_output_spice_netlists>\n");

vpr7_x2p/vpr/SRC/base/vpr_types.h

@@ -1302,6 +1302,7 @@ struct s_fpga_spice_opts {
   t_bitstream_gen_opts BitstreamGenOpts; /* Xifan Bitsteam Generator */
 
   boolean compact_routing_hierarchy; /* use compact routing hierarchy */
+  boolean duplicate_grid_pin; /* Duplicate pins at each side of the grid */
 
   /* Signal Density */
   float signal_density_weight;