tangxifan
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7245917b9c
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fix a bug for iopad SPICE generation
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2019-06-11 11:43:56 -06:00 |
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tangxifan
|
1776ae3ec8
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add explicit port mapping for inverters of memory decoders
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2019-06-10 17:36:14 -06:00 |
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tangxifan
|
8e3ad675e0
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use sstream for rr_block verilog writer
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2019-06-10 16:23:35 -06:00 |
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tangxifan
|
009e5244d3
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minor fix on the port direction of configuration peripherals for memory decoders
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2019-06-10 15:39:35 -06:00 |
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tangxifan
|
f43955037c
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remove input port requirements for SRAM circuit module
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2019-06-10 15:29:44 -06:00 |
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tangxifan
|
e4f70771a2
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updated SDC generator to embrace the RRGSB data structure
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2019-06-10 14:47:27 -06:00 |
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tangxifan
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8a8f4153ce
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use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
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2019-06-10 12:50:10 -06:00 |
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tangxifan
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e31407f693
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start cleaning up SDC generator with new RRGSB data structure
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2019-06-10 10:57:26 -06:00 |
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tangxifan
|
17bc7fc296
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update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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2019-06-08 20:11:22 -06:00 |
|
Xifan Tang
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61e359efc5
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Enable an option to disable/enable graphics in VPR compilation
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2019-06-08 15:08:17 -06:00 |
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tangxifan
|
8c5ec4572d
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revert string to sprintf
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2019-06-07 20:20:41 -06:00 |
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tangxifan
|
0f1ed19ad0
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Revert to the use of sprintf instead std::string. Have no idea why string is not working
|
2019-06-07 18:54:57 -06:00 |
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tangxifan
|
44ce0e8834
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update gsb unique module detection and fix formal verification port direction
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2019-06-07 17:18:38 -06:00 |
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tangxifan
|
24d53390d8
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clean up DeviceRRGSB internal data and member functions
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2019-06-07 14:45:56 -06:00 |
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tangxifan
|
c9f810ceb6
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update rr_gsb to build connection blocks
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2019-06-07 11:01:55 -06:00 |
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tangxifan
|
472aff5acb
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add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
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2019-06-06 23:45:21 -06:00 |
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tangxifan
|
ce9fc5696c
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rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
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tangxifan
|
8c1e7b799f
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fixed critical bugs in Connection Block Unique Module detection
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2019-06-06 16:31:50 -06:00 |
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tangxifan
|
873e4d989f
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fine-tuning Verilog format and node addition to rr_blocks
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2019-06-06 12:48:41 -06:00 |
|
tangxifan
|
c2de0eefb1
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fix redundant comma in SB Verilog module
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2019-06-06 09:15:05 -06:00 |
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tangxifan
|
b9e1b1afc4
|
fix a critical bug in num_reserved_sram_ports
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2019-06-05 17:31:01 -06:00 |
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tangxifan
|
aaf8d23971
|
fix critical bugs in routing submodules
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2019-06-05 16:43:18 -06:00 |
|
tangxifan
|
01e075377d
|
fix typo in Verilog generation
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2019-06-05 15:30:34 -06:00 |
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tangxifan
|
21d0cb52bc
|
Merge remote-tracking branch 'origin' into tileable_sb
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2019-06-05 13:31:49 -06:00 |
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tangxifan
|
24ca3104b0
|
fix minor bugs in Switch Block submodules
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2019-06-05 13:30:55 -06:00 |
|
tangxifan
|
0f87ae9886
|
support switch block submodule Verilog generation by segments
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2019-06-05 12:56:05 -06:00 |
AurelienUoU
|
84fabbd43b
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Fix sdc analysis bug related to virtual nodes + add the option in regression test
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2019-06-05 12:10:28 -06:00 |
Baudouin Chauviere
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d24488092d
|
Fix bug
|
2019-06-05 11:40:04 -06:00 |
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tangxifan
|
c2d8fa00ba
|
add rr_block unique_side_module verilog generation
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2019-06-04 17:47:40 -06:00 |
|
tangxifan
|
98b82c17be
|
bug fixing for clear RRSwitchBlock
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2019-06-04 14:02:49 -06:00 |
|
tangxifan
|
2c6780ab92
|
add side mirror detection for RRSwitchBlock
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2019-06-04 13:01:22 -06:00 |
|
Baudouin Chauviere
|
1932d00309
|
Correction of the SDC to remove global clocks
|
2019-05-30 15:04:21 -06:00 |
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tangxifan
|
5b15a746d3
|
add num_driver_nodes to Switch Block XML writter
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2019-05-28 20:52:33 -06:00 |
|
tangxifan
|
5ed076dfb4
|
fixed a critical bug in rotating
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2019-05-28 17:55:09 -06:00 |
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tangxifan
|
9cc5518d5a
|
keep adding segment information for SB XML outputter
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2019-05-28 15:59:55 -06:00 |
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tangxifan
|
e7e18eb4c1
|
Add more information in SB XML outputter
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2019-05-28 15:56:41 -06:00 |
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tangxifan
|
ca363da30c
|
add options to specify output directory of SB XML
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2019-05-28 15:19:10 -06:00 |
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tangxifan
|
6b51b42ee7
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-28 14:53:44 -06:00 |
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tangxifan
|
af91fca1e0
|
add rr_blocks XML writer to help debugging Switch Block Rotation
|
2019-05-28 14:52:44 -06:00 |
|
Baudouin Chauviere
|
3da216f297
|
correction Null issue for the flat model
|
2019-05-28 14:15:24 -06:00 |
|
tangxifan
|
6f30d3ad05
|
support rotation on segment groups inside RRChan and improve rotatable mirror searching
|
2019-05-28 11:25:16 -06:00 |
|
tangxifan
|
0f5666ea11
|
fixed the bug in mirror node direction
|
2019-05-27 21:58:21 -06:00 |
|
tangxifan
|
eece161d58
|
keep debugging on Switch Block rotation
|
2019-05-27 21:10:30 -06:00 |
|
tangxifan
|
5720217cfd
|
Add copy constructor for RRChan, RRSwitchBlock etc.
|
2019-05-27 15:44:34 -06:00 |
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tangxifan
|
1bea9870fc
|
developed new rotating methods for RRSwitchBlocks, debugging ongoing
|
2019-05-26 23:35:30 -06:00 |
|
tangxifan
|
4b852afeac
|
skip rotating mirror detection which is too time-consuming
|
2019-05-25 23:41:46 -06:00 |
|
tangxifan
|
22e71f5847
|
Add rotate one side of switch block functionality
|
2019-05-25 22:48:07 -06:00 |
|
tangxifan
|
858a323228
|
Add more support for rotating Switch Blocks
|
2019-05-25 21:26:35 -06:00 |
|
tangxifan
|
2eab0b1c1c
|
update unique_mirror search algorithm for Switch Blocks
|
2019-05-25 19:54:15 -06:00 |
|
tangxifan
|
d3eae80e64
|
implemented an native way in finding rotable Switch blocks
|
2019-05-25 19:37:18 -06:00 |