Lin
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b2a5bd8437
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fix merge error
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2024-09-11 14:35:24 +08:00 |
Jingrong Lin
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77b188060b
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Merge branch 'master' into preloading_clean
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2024-09-11 11:08:49 +08:00 |
victorzh001
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04a60ca4b5
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Merge branch 'master' into victor_OpenFPGA_dbg
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2024-09-10 11:01:47 +08:00 |
tangxifan
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7250a7d703
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[core] code format
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2024-09-09 12:46:46 -07:00 |
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tangxifan
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5f50e4623c
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[core] add a new option map_global_net_to_msb for pb_pin_fixup
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2024-09-09 12:21:09 -07:00 |
Victor
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9a2fc86dcd
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add dependency on build_fabric
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2024-09-06 17:58:47 +08:00 |
|
Victor
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7bacc781d0
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update code according to code review comments
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2024-09-06 15:39:08 +08:00 |
|
Victor
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4aca4fda6f
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fix issue in reg test
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2024-09-05 10:43:53 +08:00 |
|
Victor
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ba5c8a3364
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update code format
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2024-09-03 11:20:51 +08:00 |
|
Victor
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0093d4b269
|
Add command report_reference
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2024-09-02 15:21:50 +08:00 |
|
Lin
|
a2b290c83b
|
mod typo
|
2024-08-30 15:47:29 +08:00 |
|
Lin
|
cb003f8833
|
mod prelod flag
|
2024-08-30 12:51:56 +08:00 |
|
Lin
|
8372eead6a
|
add preload flag to device_rr_gsb and revert change to build fabric
|
2024-08-28 18:14:33 +08:00 |
|
Lin
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a23860a6a7
|
reformat code
|
2024-08-28 17:58:15 +08:00 |
|
Lin
|
352c9b49c9
|
add cmd dependency
|
2024-08-28 17:52:34 +08:00 |
|
Lin
|
cde4c8d34a
|
mod according to code review
|
2024-08-28 15:45:19 +08:00 |
|
Lin
|
1b0fcaee0f
|
reformat code
|
2024-08-27 17:05:13 +08:00 |
|
Lin
|
9c061e0ab5
|
Merge branch 'preloading' of github.com:lnis-uofu/OpenFPGA
|
2024-08-25 22:48:56 -07:00 |
|
Lin
|
968824c2dd
|
build unique blocks final version
|
2024-08-25 19:56:23 -07:00 |
|
Lin
|
699131ad58
|
full flow with bugs
|
2024-08-19 01:18:06 -07:00 |
|
Lin
|
7f426d5939
|
add commands
|
2024-08-02 03:10:10 -07:00 |
|
Lin
|
48a386c9b6
|
add read and write uniqueblocks commands
|
2024-08-02 01:43:01 -07:00 |
|
tangxifan
|
5cfd23747b
|
[core] code format
|
2024-06-28 13:47:03 -07:00 |
|
tangxifan
|
7892c2340c
|
[core] add a new option 'disable_unused_trees' to route clock rr graph
|
2024-06-27 12:01:54 -07:00 |
|
tangxifan
|
bf24382f19
|
[core] code format
|
2024-05-02 18:33:07 -07:00 |
|
tangxifan
|
4d3447f773
|
[core] rework fabric hierarchy writer
|
2024-05-02 18:05:38 -07:00 |
|
tangxifan
|
6f94399767
|
[core] code format
|
2024-04-10 22:53:52 -07:00 |
|
tangxifan
|
971f0e8838
|
[core] add a new option '--show_invalid_side'
|
2024-04-10 22:52:36 -07:00 |
|
tangxifan
|
47baaff94c
|
[core] rename command name to 'write_fabric_pin_physical_location`` and start developing exec func
|
2024-04-10 13:30:02 -07:00 |
|
tangxifan
|
f1334645db
|
[core] added a new command write_pin_physical_location
|
2024-04-10 13:07:49 -07:00 |
|
tangxifan
|
72a3c05747
|
[core] code format
|
2023-09-17 13:29:30 -07:00 |
|
tangxifan
|
ccd4c1861b
|
[core] developing new command to write module naming rules
|
2023-09-16 19:37:06 -07:00 |
|
tangxifan
|
37573abc22
|
[core] code format
|
2023-09-15 23:32:40 -07:00 |
|
tangxifan
|
c85c64eb5a
|
[core] syntax
|
2023-09-15 23:30:34 -07:00 |
|
tangxifan
|
2a45b49890
|
[core] developing renaming commands. options and functions
|
2023-09-15 19:15:18 -07:00 |
|
tangxifan
|
87f2822ef8
|
[core] working on logical and physical children
|
2023-08-02 19:46:27 -07:00 |
|
tangxifan
|
2d2b8f67aa
|
[core] adding new option '--group_config_block' to command 'build_fabric'
|
2023-07-31 17:32:48 -07:00 |
|
tangxifan
|
091ac88c7e
|
[lib] code format
|
2023-07-14 12:16:40 -07:00 |
|
tangxifan
|
c58035dbd4
|
[core] start developing option --group_tile for build_fabric
|
2023-07-14 11:01:04 -07:00 |
|
tangxifan
|
3de4d3fc09
|
[core] add a new command 'write_fabric_key' and now writer supports module-level keys
|
2023-07-08 18:12:51 -07:00 |
|
tangxifan
|
61544af2b4
|
[core] start adding new options
|
2023-06-21 14:01:00 -07:00 |
|
tangxifan
|
299b42873d
|
[core] fix no warning build
|
2023-06-19 13:01:43 -07:00 |
|
tangxifan
|
c7ade72200
|
[core] code complete for the core wrapper creator. Start debugging
|
2023-06-18 19:17:42 -07:00 |
|
tangxifan
|
8bc70b590a
|
[core] developing fpga_core insertion
|
2023-06-17 23:42:45 -07:00 |
|
tangxifan
|
50e201feeb
|
[core] now clock routing for programmable clock network works for 1 clock design
|
2023-03-07 13:13:25 -08:00 |
|
tangxifan
|
6f2572324e
|
[core] developing route clock rr_graph command
|
2023-02-28 11:52:38 -08:00 |
|
tangxifan
|
7f07a9d031
|
[lib] add default seg/switch to clock arch. Fixed syntax
|
2023-02-24 19:15:39 -08:00 |
|
tangxifan
|
786b458a27
|
[core] adding new command 'append_clock_rr_graph'
|
2023-02-23 13:30:18 -08:00 |
|
tangxifan
|
e1dab3d227
|
[code] format
|
2023-02-22 22:01:24 -08:00 |
|
tangxifan
|
e175472a07
|
[core] adding new commands
|
2023-02-22 21:58:25 -08:00 |