tangxifan
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e867e203f4
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[Documentation] Use release mode in Docker settings
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2020-09-20 15:00:56 -06:00 |
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tangxifan
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544c44fe46
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[FPGA-SPICE] Add VDD and VSS port to module definition
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2020-09-20 14:58:15 -06:00 |
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tangxifan
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615a24999a
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[Documentation] Remove out-of-date description
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2020-09-20 14:45:33 -06:00 |
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tangxifan
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460fef5807
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[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
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2020-09-20 12:58:55 -06:00 |
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tangxifan
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222bc86cbf
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[FPGA-SPICE] Add auxiliary SPICE netlist writer
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2020-09-20 12:53:28 -06:00 |
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tangxifan
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06c0073a3e
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[FPGA-SPICE] Add SPICE writer for fpga top module
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2020-09-20 12:43:48 -06:00 |
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tangxifan
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1dfb3e06cc
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[FPGA-SPICE] add SPICE writer for logic blocks
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2020-09-20 12:38:24 -06:00 |
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tangxifan
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5e78e91fdf
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[FPGA-SPICE] Add SPICE writer for routing blocks
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2020-09-20 12:27:48 -06:00 |
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tangxifan
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0f25b52907
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[FPGA-Verilog] code format fix
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2020-09-20 12:18:22 -06:00 |
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tangxifan
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2fae311c8e
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[FPGA-SPICE] Add SPICE writer for memories
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2020-09-20 12:14:34 -06:00 |
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tangxifan
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f284f6f8d0
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[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
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2020-09-20 12:03:10 -06:00 |
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tangxifan
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6801d260e9
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[FPGA-SPICE] Add SPICE writer for LUT
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2020-09-20 11:58:11 -06:00 |
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tangxifan
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0f9fce92b2
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[FPGA-SPICE] Add SPICE writer for routing multiplexers
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2020-09-20 11:49:02 -06:00 |
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tangxifan
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c7e3d97d1b
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[FPGA-SPICE] Add supply voltage generator
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2020-09-20 11:19:06 -06:00 |
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tangxifan
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15df9b3893
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[FPGA-SPICE] Add SPICE subcircuit writer
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2020-09-19 23:01:44 -06:00 |
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tangxifan
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82e137cbe4
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[FPGA-SPICE] Add wire module SPICE writer
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2020-09-19 19:31:16 -06:00 |
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tangxifan
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1b2762386c
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[FPGA-SPICE] Bug fix for essential gate netlist writing
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2020-09-19 16:52:30 -06:00 |
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tangxifan
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26a0a769ea
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[FPGA-SPICE] Split essential gate SPICE netlists into separated files
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2020-09-19 16:45:26 -06:00 |
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tangxifan
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e102e30d19
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[FPGA-SPICE] Add support for AND/OR logic gate
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2020-09-19 16:20:21 -06:00 |
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tangxifan
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482d90018f
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[FPGA-SPICE] Create generic PMOS/NMOS instanciation function
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2020-09-19 15:33:28 -06:00 |
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tangxifan
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3262ceb276
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[FPGA-SPICE] Bug fix for pass gate transistor sizing
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2020-09-19 15:24:40 -06:00 |
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tangxifan
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aa078f079c
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[FPGA-SPICE] Restructured SPICE netlist writers for atom circuits to avoid large cpp files
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2020-09-19 15:20:19 -06:00 |
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tangxifan
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f5dadca884
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[FPGA-SPICE] Optimize the print-out of SPICE ports
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2020-09-19 15:07:48 -06:00 |
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tangxifan
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51d423e4db
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[FPGA-SPICE] Add pass-gate SPICE netlist writer
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2020-09-19 14:59:00 -06:00 |
Laboratory for Nano Integrated Systems (LNIS)
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882854585c
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Merge pull request #86 from LNIS-Projects/dev
Misc Updates
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2020-09-17 19:43:06 -06:00 |
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tangxifan
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9e4353ddf4
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[Documentation] Patch on the travis link
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2020-09-17 17:01:23 -06:00 |
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tangxifan
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ccd9ebe71b
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[Documentation] Use travis.com in CI badge as travis.org will be deprecated by the end of 2020
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2020-09-17 16:59:20 -06:00 |
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tangxifan
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681e80d4b6
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[Regression tests] update frac_lut test case using more representative benchmarks
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2020-09-17 10:39:22 -06:00 |
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tangxifan
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367cf59efd
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[Benchmark] Bug fix in the and2_or2 benchmark
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2020-09-17 10:35:13 -06:00 |
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tangxifan
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de48b8c7b2
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[Benchmark] Add a new micro benchmark to test fracturable LUTs
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2020-09-17 10:21:25 -06:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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92690f6b1e
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Merge pull request #85 from LNIS-Projects/dev
Support on flexible local routing architecture
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2020-09-16 19:59:54 -06:00 |
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tangxifan
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9cfb2f52ef
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[OpenFPGA code] bug fix for fully equivalent outputs of pb_type
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2020-09-16 19:26:46 -06:00 |
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tangxifan
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ca1bafc688
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[OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture
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2020-09-16 19:26:12 -06:00 |
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tangxifan
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2aff461f59
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[Regression Tests] Deploy no local routing test case to CI
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2020-09-16 18:09:24 -06:00 |
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tangxifan
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c22d8e2421
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[Architecture] Bug fix in no local routing architecture
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2020-09-16 18:07:52 -06:00 |
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tangxifan
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c40c9f5876
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[Regression test] add test case for no local routing architecture
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2020-09-16 18:05:33 -06:00 |
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tangxifan
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f5b7ac6269
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[OpenFPGA Architecture] Add a new architecture with no local routing
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2020-09-16 18:04:55 -06:00 |
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tangxifan
|
5fe039dd7c
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[Regression Tests] Deploy the fully connected crossbar test to CI
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2020-09-16 17:35:49 -06:00 |
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tangxifan
|
35d47ee0e7
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[Regression tests] bug fix in the test case for fully connected output crossbar
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2020-09-16 17:33:54 -06:00 |
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tangxifan
|
030d7f02f8
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[OpenFPGA architecture] bug fix in the fully connected output crossbar architecture
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2020-09-16 17:30:08 -06:00 |
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tangxifan
|
30fb99095f
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[Regression Tests] Add new test case for fully connected output crossbar
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2020-09-16 17:29:15 -06:00 |
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tangxifan
|
3c0faf0021
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[OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs
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2020-09-16 17:27:24 -06:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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bcbc583593
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Merge pull request #84 from LNIS-Projects/dev
Add compiler compatibility tests to Travis CI
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2020-09-14 23:18:55 -06:00 |
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tangxifan
|
8b6c8f73e9
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 21:26:53 -06:00 |
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tangxifan
|
b43cd2741d
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[Regression Tests] Add gcc-5 compatibility test to Travis CI
|
2020-09-14 20:14:16 -06:00 |
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tangxifan
|
c23742c751
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 20:13:27 -06:00 |
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tangxifan
|
fc6bfdc7a2
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[OpenFPGA Code] Patch syntax compatibility for older gcc
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2020-09-14 18:55:21 -06:00 |
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tangxifan
|
d4bac95cd4
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[Regression Tests] Enable matrix eval parameter in setting up compilers
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2020-09-14 17:07:14 -06:00 |
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tangxifan
|
c08d4f5cd9
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[Regression Test] Patch travis script
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2020-09-14 16:59:08 -06:00 |
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tangxifan
|
e3559f0df9
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[Regression Test] Add compiler coverage test to CI
|
2020-09-14 16:53:16 -06:00 |