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Merge pull request #86 from LNIS-Projects/dev 

Misc Updates
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Laboratory for Nano Integrated Systems (LNIS) 2020-09-17 19:43:06 -06:00 committed by GitHub
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5 changed files with 42 additions and 4 deletions
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2
README.md
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@ -1,5 +1,5 @@
# Getting Started with OpenFPGA <img src="./docs/source/figures/OpenFPGA_logo.png" width="200" align="right">
[![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA)
[![Build Status](https://travis-ci.com/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.com/LNIS-Projects/OpenFPGA)
[![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)
## Introduction

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openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act Normal file
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a 0.5 0.5
b 0.5 0.5
c 0.25 0.25
d 0.25 0.25

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openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif Normal file
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.model and2_or2
.inputs a b
.outputs c d
.names a b c
11 1
.names a b d
00 0
.end

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openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v Normal file
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/////////////////////////////////////////
// Functionality: 2-input AND + 2-input OR
// This benchmark is designed to test fracturable LUTs
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module and2_or2(
a,
b,
c,
d);
input wire a;
input wire b;
output wire c;
output wire d;
assign c = a & b;
assign d = a | b;
endmodule

7
openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf
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@ -27,6 +27,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
#
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
# Modelsim is ok with this but icarus fails due to poor support on timing and looping
#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
@ -39,9 +40,9 @@ bench1_top = routing_test
bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
bench2_top = and2_latch
bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act
bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
bench2_top = and2_or2
bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=