From de48b8c7b2f01ae9d81c6b2a81a9a3162796d0c1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 17 Sep 2020 10:21:25 -0600 Subject: [PATCH 1/5] [Benchmark] Add a new micro benchmark to test fracturable LUTs --- .../micro_benchmark/and2_or2/and2_or2.act | 4 ++++ .../micro_benchmark/and2_or2/and2_or2.blif | 11 ++++++++++ .../micro_benchmark/and2_or2/and2_or2.v | 22 +++++++++++++++++++ 3 files changed, 37 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act new file mode 100644 index 000000000..33c156f30 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act @@ -0,0 +1,4 @@ +a 0.5 0.5 +b 0.5 0.5 +c 0.25 0.25 +d 0.25 0.25 diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif new file mode 100644 index 000000000..88e7fcf9a --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif @@ -0,0 +1,11 @@ +.model and2_or2 +.inputs a b +.outputs c d + +.names a b c +11 1 + +.names a b d +00 1 + +.end diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v new file mode 100644 index 000000000..b57cdeffe --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v @@ -0,0 +1,22 @@ +///////////////////////////////////////// +// Functionality: 2-input AND + 2-input OR +// This benchmark is designed to test fracturable LUTs +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module and2_or2( + a, + b, + c, + d); + +input wire a; +input wire b; +output wire c; +output wire d; + +assign c = a & b; +assign d = a | b; + +endmodule From 367cf59efda561d110157ad7ddbf91a5c721f214 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 17 Sep 2020 10:35:13 -0600 Subject: [PATCH 2/5] [Benchmark] Bug fix in the and2_or2 benchmark --- openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif index 88e7fcf9a..14a8bc6eb 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif +++ b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif @@ -6,6 +6,6 @@ 11 1 .names a b d -00 1 +00 0 .end From 681e80d4b62c68c56494439c424fa4f4887ea007 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 17 Sep 2020 10:39:22 -0600 Subject: [PATCH 3/5] [Regression tests] update frac_lut test case using more representative benchmarks --- .../fpga_verilog/lut_design/frac_lut/config/task.conf | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf index fbe91030d..1809feae5 100644 --- a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf @@ -27,6 +27,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml # bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif # Modelsim is ok with this but icarus fails due to poor support on timing and looping #bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif @@ -39,9 +40,9 @@ bench1_top = routing_test bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v -bench2_top = and2_latch -bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act -bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v +bench2_top = and2_or2 +bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act +bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From ccd9ebe71b5087e49ba0c11472ac6d40fee6dbad Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 17 Sep 2020 16:59:20 -0600 Subject: [PATCH 4/5] [Documentation] Use travis.com in CI badge as travis.org will be deprecated by the end of 2020 --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 614d295c3..4c05b4f94 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # Getting Started with OpenFPGA -[![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) +[![Build Status](https://travis-ci.com/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) ## Introduction From 9e4353ddf4d0af0496162eb8b30df6384e9d649c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 17 Sep 2020 17:01:23 -0600 Subject: [PATCH 5/5] [Documentation] Patch on the travis link --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 4c05b4f94..1965b9b47 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # Getting Started with OpenFPGA -[![Build Status](https://travis-ci.com/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) +[![Build Status](https://travis-ci.com/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.com/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) ## Introduction