3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
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* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
af0646260c
[Test] Bug fix in pin constraints
2021-01-19 17:44:05 -07:00
186f2f1968
[Test] Use pin constraint in multi-clock test case
2021-01-19 17:42:40 -07:00
e17a5cbbf2
[Test] Rename to pin constraint to comply with libpcf requirement
2021-01-19 15:52:51 -07:00
ab25e1af5f
[Test] Add example XML for net mapping between benchmark to FPGA
2021-01-19 09:29:21 -07:00
ea9d6bfe91
[Flow] Update the design constraint file to follow bug fix in parser
2021-01-17 10:41:01 -07:00
dd74f05a31
[Test] Add repack constraints to tests
2021-01-17 10:35:36 -07:00
d0e05b3575
[Lib] Now use pb_type in design constraints instead of physical tiles
2021-01-16 21:35:43 -07:00
8578c1ecac
[Flow] Rename the design contraint file syntax
2021-01-16 15:35:13 -07:00
9154cfdeec
[Flow] Add comments for the design constraint file
2021-01-16 15:34:01 -07:00
6ab0f71896
[Test] Add an example of repack pin constraints file
2021-01-16 14:38:39 -07:00
3b5394b45f
[Test] Now use dedicated simulation settings for the 4-clock architecture
2021-01-14 15:40:16 -07:00
314e458632
[Test] Update task configuration to use post-yosys .v file in verification
2021-01-13 15:42:45 -07:00
91f12071d5
[Test] Use counter4bit in the multi-clock test
2021-01-13 13:34:59 -07:00
250adb01cf
[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
2021-01-13 13:18:31 -07:00
99e2a068fb
[Test] Add a test case for multi-clock
2021-01-12 18:06:25 -07:00
43418cd76b
[Test] Deploy pipeplined and2 to test cases
2021-01-10 10:28:22 -07:00
06af30ef10
[Test] Add test case for the SCFF usage in configuration chain
2021-01-04 17:30:19 -07:00
6b50bbf986
Merge pull request #134 from lnis-uofu/ganesh_dev
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Support Delay Customization in OpenFPGA Task Configuration File
2020-12-08 15:32:48 -07:00
0cb8457e21
[Test] Add test case for tileable I/O
2020-12-04 16:02:47 -07:00
179b0ce304
[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
2020-11-30 18:11:47 -07:00
27a480b5f8
[Test] arch name fix in the test case
2020-11-30 17:45:54 -07:00
a1d3b439d3
[Test] Add a new test case to define a global reset port from a global tile port
2020-11-30 17:19:12 -07:00
7db030018c
[Bug] Fixed variable file location
2020-11-25 22:44:40 -07:00
fefba0db59
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
2020-11-25 17:29:53 -07:00
1d993296d8
[Flow] Example of using test variable in task conf
2020-11-25 17:25:12 -07:00
655da9f3d0
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
2020-11-22 16:37:19 -07:00
845436fa71
[Test] Add sequential benchmark for global tile clock test case
2020-11-17 14:34:54 -07:00
485258a9ea
[Test] Add test case for global clock from tiles
2020-11-10 19:24:25 -07:00
61376a2979
[Test] Add test cases for various tile organization
2020-11-04 16:32:52 -07:00
4c14428400
[Test] Add test case for fast configuration support on multi-region frame-based configuration protocol
2020-10-30 10:50:00 -06:00
ca7d43275d
[Test] Add test case for multi_region configuration frame
2020-10-30 10:48:29 -06:00
241ebf054a
[Test] Add a test case for validating fast configuration techniques on multi-region memory banks
2020-10-29 16:29:46 -06:00
ff386001c4
[Test] Add openfpga task for multi-region memory banks
2020-10-29 13:56:32 -06:00
dc68c52d0a
[Test] Now use a light architecture to speed up the test case runtime
2020-10-12 12:53:34 -06:00
8941e38613
[Test] Enable verification in the new test case
2020-10-12 12:50:08 -06:00
9e1fd300dc
[Test] Add test case for customized location of fabric netlists
2020-10-12 12:47:58 -06:00
d4d02ab16a
[Regression Test] Move fabric key tests to basic tests
2020-09-29 14:22:23 -06:00
a0d1d68402
[Regression Test] Add regression tests for smart fast configuration chain using multiple regions
2020-09-29 13:53:41 -06:00
5be5835b71
[Regression Test] Add multiple region configuration chain test case
2020-09-29 13:48:39 -06:00
19dd3778d9
[Architecture] Add test case for memory bank to use both reset and set
2020-09-24 17:04:24 -06:00
335f5b78c1
[Regression Test] Add test case to use both set and reset for configuration frame
2020-09-24 17:02:28 -06:00
2d81ff9012
[Regression test] Add configuration chain test case where both set and reset are used
2020-09-24 16:59:52 -06:00
7fbccdd102
[Regression Tests] Add test cases for configuration chain using different DFF cells
2020-09-24 14:34:12 -06:00
e7906899dd
[Regression test] Bug fix for fast configuration frame. Now should use a latch with reset
2020-09-24 13:53:12 -06:00
ffd1a72d22
[Architecture] Add regression tests for the frame-based configuration using reset and set signals
2020-09-24 12:18:26 -06:00
fde15c4f88
[Regression Test] Add test for fast memory bank configuration using set signals
2020-09-24 12:13:35 -06:00
48083d2276
[Regression Test] Adapt fast memory bank test case
2020-09-24 10:32:03 -06:00
186f00edfc
[Regression Test] Add test cases for memory bank using different SRAM cells
2020-09-24 10:25:03 -06:00
5b0d451f0f
[Regression Test] Add test case for configurable latch with active-low set
2020-09-23 23:04:10 -06:00
AurelienAlacchi
tangxifan
ganeshgore