tangxifan
|
5efc9d0e00
|
[test] update golden outputs
|
2024-07-08 23:24:16 -07:00 |
|
tangxifan
|
092b8b038f
|
[core] remove verbose out
|
2024-07-08 22:23:37 -07:00 |
|
tangxifan
|
04504e4d5d
|
[core] code format
|
2024-07-08 22:22:59 -07:00 |
|
tangxifan
|
1cdb1c5995
|
[core] fixed a bug on calculating subtile pins
|
2024-07-08 22:22:08 -07:00 |
|
tangxifan
|
5cb104a5f6
|
[test] fixed a bug
|
2024-07-08 22:04:40 -07:00 |
|
tangxifan
|
bf484dbc70
|
[doc] add perimeter cb examples on prog clk network
|
2024-07-08 21:25:12 -07:00 |
|
tangxifan
|
229adebe07
|
[doc] new option to write_fabric_verilog
|
2024-07-08 21:06:12 -07:00 |
|
tangxifan
|
41839bfd7a
|
[test] typo
|
2024-07-08 20:21:40 -07:00 |
|
tangxifan
|
8a5c33b1d6
|
[doc] new option for perimeter cb
|
2024-07-08 19:01:16 -07:00 |
|
tangxifan
|
03c1c6f917
|
[test] code format
|
2024-07-08 18:35:23 -07:00 |
|
tangxifan
|
c7d6c3ab61
|
[arch] now all the outputs of I/O can only on 1 side
|
2024-07-08 18:34:13 -07:00 |
|
tangxifan
|
ad053cddca
|
[test] code format
|
2024-07-08 18:02:30 -07:00 |
|
tangxifan
|
fe06c2f2b1
|
[core] code format
|
2024-07-08 16:18:58 -07:00 |
|
tangxifan
|
db459b0e87
|
[core] add verbose outputs
|
2024-07-08 16:18:32 -07:00 |
|
tangxifan
|
e8f9deeeaf
|
[core] fixed a critical bug on computing pin index for subtile in clock taps
|
2024-07-08 16:12:20 -07:00 |
|
tangxifan
|
6dde383a7f
|
[core] debugging
|
2024-07-08 16:00:18 -07:00 |
|
tangxifan
|
c30eafac9f
|
[test] fixed a bug on clk ntwk arch where some io clocks are not tapped
|
2024-07-08 15:26:16 -07:00 |
|
tangxifan
|
8bca3d79be
|
[core] fixed a bug where tap points of clock network cannot reach perimeter cb
|
2024-07-08 15:17:24 -07:00 |
|
tangxifan
|
b50acacfba
|
[test] fixed some bug in pin loc; Outputs are not recommend on the fringe I/O tiles
|
2024-07-08 15:09:31 -07:00 |
|
tangxifan
|
549dc6e7e6
|
[lib] update vtr
|
2024-07-08 13:39:55 -07:00 |
|
tangxifan
|
ab454be831
|
[lib] update vtr
|
2024-07-08 13:32:54 -07:00 |
|
tangxifan
|
7bd60f5f7d
|
[core] support perimeter cb when identify pins of I/Os tiles
|
2024-07-08 12:39:54 -07:00 |
|
tangxifan
|
6492d43a01
|
[test] add a new test to validate perimeter cb using global tile clock
|
2024-07-08 11:29:20 -07:00 |
|
tangxifan
|
48ae3691c4
|
[test] typo
|
2024-07-08 10:57:54 -07:00 |
|
tangxifan
|
5c9c4d93c5
|
[core] typo
|
2024-07-08 10:46:47 -07:00 |
|
tangxifan
|
cdd477ad80
|
[core] remove restrictions on cb clock nodes
|
2024-07-08 10:14:39 -07:00 |
|
tangxifan
|
8449da0143
|
[core] typo
|
2024-07-07 23:36:13 -07:00 |
dependabot[bot]
|
7d9fcc1a7b
|
Bump yosys from `a739e21` to `dac5bd1`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `a739e21` to `dac5bd1`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](a739e21a5f...dac5bd1983)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-07-08 06:12:43 +00:00 |
|
tangxifan
|
ff56139a53
|
[test] debugging
|
2024-07-07 23:07:51 -07:00 |
|
tangxifan
|
b0851a6299
|
[test] debugging
|
2024-07-07 23:05:37 -07:00 |
|
tangxifan
|
686cd761b7
|
[test] debugging
|
2024-07-07 22:48:21 -07:00 |
|
tangxifan
|
57a378ae59
|
[test] typo
|
2024-07-07 22:35:14 -07:00 |
|
tangxifan
|
f784e58383
|
[test] typo
|
2024-07-07 22:33:45 -07:00 |
|
tangxifan
|
1a5e2392fc
|
[test] add a new testcase to validate clock network when perimeter cb is on
|
2024-07-07 22:32:13 -07:00 |
|
tangxifan
|
db12532eb8
|
[test] typo
|
2024-07-07 21:41:39 -07:00 |
|
tangxifan
|
7996de3fe6
|
[core] now support perimeter cb in programmable clock network arch
|
2024-07-07 14:57:05 -07:00 |
|
tangxifan
|
4da5150a26
|
[doc] update for bottom-left tile organization
|
2024-07-07 14:20:26 -07:00 |
|
tangxifan
|
439de61fd0
|
[test] fixed a bug on ecb support
|
2024-07-07 14:00:11 -07:00 |
|
tangxifan
|
91f8bb5841
|
[doc] update figures for ecb
|
2024-07-07 13:40:01 -07:00 |
|
tangxifan
|
201b2555e5
|
[test] code format
|
2024-07-06 12:15:08 -07:00 |
|
tangxifan
|
703cbddc9e
|
[core] code format
|
2024-07-06 12:14:57 -07:00 |
|
tangxifan
|
43ca3ec747
|
[test] make arch pin loc for spread for perimeter cb validation
|
2024-07-06 12:11:31 -07:00 |
|
tangxifan
|
6024e35f89
|
[core] fixed a bug
|
2024-07-05 18:50:14 -07:00 |
|
tangxifan
|
1f7fbfef64
|
[core] fixed a bug on inter-tile connections in top module
|
2024-07-05 18:19:22 -07:00 |
|
tangxifan
|
e95b264965
|
[core] debugging
|
2024-07-05 18:08:48 -07:00 |
|
tangxifan
|
a46820b7c1
|
[core] add a new test for bottom-left tile grouping
|
2024-07-05 18:00:37 -07:00 |
|
tangxifan
|
cca9fb4756
|
[core] fixed a bug on bottom left tile organization
|
2024-07-05 17:55:19 -07:00 |
|
tangxifan
|
46d916f0a0
|
[core] fixed the bugs in fabric tile build-up
|
2024-07-05 16:59:08 -07:00 |
|
tangxifan
|
5e89b950ed
|
[lib] update vtr
|
2024-07-05 13:41:38 -07:00 |
|
tangxifan
|
a41f437109
|
[core] now netlist look ok
|
2024-07-05 12:36:47 -07:00 |