tangxifan
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64bf2e01c3
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Merge pull request #535 from lnis-uofu/dependabot/submodules/yosys-plugins-503b979
Bump yosys-plugins from `ea7411a` to `503b979`
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2022-02-16 10:16:45 -08:00 |
dependabot[bot]
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30d045dce0
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Bump yosys-plugins from `ea7411a` to `503b979`
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `ea7411a` to `503b979`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](ea7411a915...503b9791c1 )
---
updated-dependencies:
- dependency-name: yosys-plugins
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
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2022-02-16 07:21:25 +00:00 |
tangxifan
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eec0da5327
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Merge pull request #533 from lnis-uofu/counter
Add initial conditions to counter benchmarks
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2022-02-15 18:33:45 -08:00 |
tangxifan
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e67f8ad8b2
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[FPGA-Verilog] Now full testbench does not check any output vectors during configuration phase
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2022-02-15 17:19:50 -08:00 |
tangxifan
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ed6d557e65
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Merge branch 'master' into counter
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2022-02-15 16:50:27 -08:00 |
tangxifan
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f02f3c10d4
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[Test] Fix bugs on the remaining implicit verilog test cases
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2022-02-15 16:49:15 -08:00 |
tangxifan
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074811a612
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[Script] Now counter benchmarks should pass on the implicit verilog test case
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2022-02-15 16:47:14 -08:00 |
tangxifan
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1370be0817
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[Script] Fixing bugs
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2022-02-15 16:44:51 -08:00 |
tangxifan
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a49cf35dbe
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Merge pull request #534 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-02-15 16:35:21 -08:00 |
tangxifan
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8be0868a3b
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[Test] Update test case which uses counter benchmarks: adding pin constraints
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2022-02-15 16:29:06 -08:00 |
github-actions[bot]
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a985d99359
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Updated Patch Count
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2022-02-16 00:21:07 +00:00 |
tangxifan
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430580f138
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[HDL] Fix a typo
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2022-02-15 16:09:14 -08:00 |
tangxifan
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a7786efde1
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[HDL] Now dual-clock counter has only 1 reset pin
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2022-02-15 16:07:50 -08:00 |
tangxifan
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f002c79a61
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[Test] Adapt pin constraints due to changes in pin names
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2022-02-15 16:06:46 -08:00 |
tangxifan
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b533fd17d5
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[Test] Rework pin constraints that cause problems
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2022-02-15 15:41:16 -08:00 |
tangxifan
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9ef7ad64d8
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[Test] Simplify paths
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2022-02-15 15:35:21 -08:00 |
tangxifan
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7121513396
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[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work
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2022-02-15 15:21:08 -08:00 |
tangxifan
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de4028bdcc
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Merge pull request #531 from lnis-uofu/dependabot/submodules/yosys-plugins-ea7411a
Bump yosys-plugins from `3b18b54` to `ea7411a`
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2022-02-15 14:20:17 -08:00 |
tangxifan
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478d31ef2e
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Merge branch 'master' into dependabot/submodules/yosys-plugins-ea7411a
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2022-02-15 09:29:16 -08:00 |
tangxifan
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f13a1a3dee
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Merge pull request #530 from lnis-uofu/counters
Fixed a bug in task run when removing previous runs
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2022-02-15 09:29:01 -08:00 |
dependabot[bot]
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7de269def3
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Bump yosys-plugins from `3b18b54` to `ea7411a`
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `3b18b54` to `ea7411a`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](3b18b5495c...ea7411a915 )
---
updated-dependencies:
- dependency-name: yosys-plugins
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
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2022-02-15 07:28:21 +00:00 |
tangxifan
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23e04824fa
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Merge branch 'master' into counters
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2022-02-14 23:19:56 -08:00 |
tangxifan
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74045fc7a1
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[Script] Fix a bug
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2022-02-14 23:11:42 -08:00 |
tangxifan
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2990eb7406
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[Script] Fixed a bug in task run when removing previous runs
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2022-02-14 22:54:16 -08:00 |
tangxifan
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1e8deae120
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Merge pull request #529 from lnis-uofu/counters
Enable comprehensive tests for counter benchmarks
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2022-02-14 18:27:20 -08:00 |
tangxifan
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be8f18310d
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[FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances
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2022-02-14 17:16:26 -08:00 |
tangxifan
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d3f68db228
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[FPGA-Verilog] fixing bugs in reset ports for counters in full testbenches
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2022-02-14 17:00:54 -08:00 |
tangxifan
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d0fe8d96fa
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[Test] Update template scripts and assoicated test cases by offering more options
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2022-02-14 16:03:48 -08:00 |
tangxifan
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d667102a43
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[Test] Add new test case to regression tests
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2022-02-14 15:58:53 -08:00 |
tangxifan
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70363effa4
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[Test] Add a new test to validate 8-bit counters using full testbenches
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2022-02-14 15:57:55 -08:00 |
tangxifan
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2fb1df11bb
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[Script] Add a new example script
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2022-02-14 15:54:07 -08:00 |
tangxifan
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7ef808cbe4
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[Test] Update pin constraints for different counter benchmarks
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2022-02-14 15:28:03 -08:00 |
tangxifan
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34e192c5ca
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[FPGA-Verilog] Fixed a bug on wiring FPGA global ports
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2022-02-14 15:21:29 -08:00 |
tangxifan
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570c1b10dc
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[Test] Add dedicated pin constraints for counter designs
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2022-02-14 13:54:48 -08:00 |
tangxifan
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85011824e2
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[Test] Enable Verilog-to-Verification flow for counter8 benchmarks
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2022-02-14 13:15:55 -08:00 |
tangxifan
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6630c17c23
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[Test] Use preconfigured testbench template to run counter8 tests
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2022-02-14 13:07:31 -08:00 |
tangxifan
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da3f9ccb80
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[Test] Truncating counter designs in each task
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2022-02-14 12:22:19 -08:00 |
tangxifan
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0268814fc6
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[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
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2022-02-14 12:20:56 -08:00 |
tangxifan
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a80b2d7882
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Merge pull request #528 from lnis-uofu/tb
Now the shared input ports in top-level testbench has a dedicated postfix (except clock ports)
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2022-02-14 12:17:38 -08:00 |
tangxifan
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8d48492ec0
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[FPGA-Verilog] Add clock ports to the white list when adding postfix
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2022-02-14 11:09:00 -08:00 |
tangxifan
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5794561f7b
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[FPGA-Verilog] Now shared input wire/register has a postfix in full testbench
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2022-02-14 10:39:27 -08:00 |
tangxifan
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ae5d77b7bc
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Merge pull request #527 from lnis-uofu/dependabot/submodules/yosys-plugins-3b18b54
Bump yosys-plugins from `13520da` to `3b18b54`
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2022-02-14 09:46:21 -08:00 |
dependabot[bot]
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bf9ebccb20
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Bump yosys-plugins from `13520da` to `3b18b54`
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `13520da` to `3b18b54`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](13520dac01...3b18b5495c )
---
updated-dependencies:
- dependency-name: yosys-plugins
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2022-02-14 07:25:30 +00:00 |
tangxifan
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c58cadafce
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Merge pull request #526 from lnis-uofu/tb
Now preconfigured top-level module has the same port name as reference benchmarks
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2022-02-13 23:01:27 -08:00 |
tangxifan
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2ca73d79e4
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[FPGA-Verilog] Fixed the bug on pin constraints
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2022-02-13 22:08:06 -08:00 |
tangxifan
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b1377f0d34
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[FPGA-Verilog] Fix syntax errors
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2022-02-13 20:29:05 -08:00 |
tangxifan
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6e132aace4
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[FPGA-Verilog] Remove the prefix added by VPR in preconfigured top module
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2022-02-13 20:26:21 -08:00 |
tangxifan
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fb4106de19
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[FPGA-Verilog] Fixed a bug in naming mismatch
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2022-02-13 20:06:35 -08:00 |
tangxifan
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a068237082
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[FPGA-Verilog] Rename internal wire names in testbenches, in order to be consistent with reference benchmarks
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2022-02-13 19:55:16 -08:00 |
tangxifan
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4703753807
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Merge pull request #524 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-02-12 17:26:11 -08:00 |