AurelienUoU
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2f14716f13
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Adding DPRAM behavioural Verilog netlist and its TB
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2019-12-03 13:58:20 -07:00 |
tangxifan
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099863a956
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make FPGA-X2P to be run conditionally
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2019-12-03 13:50:39 -07:00 |
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tangxifan
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eec64bb63f
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Merge pull request #31 from LNIS-Projects/dev
Update master with latest development version
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2019-12-02 17:52:03 -07:00 |
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tangxifan
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5b4ddfb3ce
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use adapt yosys Makefile for OpenFPGA framework
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2019-11-27 14:42:47 -07:00 |
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tangxifan
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1c7fdac3f2
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add CMakefile for yosys
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2019-11-27 14:42:18 -07:00 |
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tangxifan
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4d62dc1c3e
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Upgrade to yosys-0.9
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2019-11-27 14:40:39 -07:00 |
Ganesh Gore
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2b465cf153
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-11-22 16:03:04 -07:00 |
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tangxifan
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8cc72536d1
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minor bug fixing
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2019-11-22 15:54:14 -07:00 |
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tangxifan
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96733f9ea8
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add minor comments in task file for modelsim regression tests
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2019-11-16 22:34:03 -07:00 |
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Ganesh Gore
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e6d14c8bf5
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-11-16 19:20:51 -07:00 |
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Ganesh Gore
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3f235a16f9
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-11-16 19:14:34 -07:00 |
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Ganesh Gore
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6bb11918dc
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Updated modelsim and collected result
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2019-11-16 19:10:04 -07:00 |
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tangxifan
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a13f406918
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tweaking mcnc_big20 task run for modelsim
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2019-11-16 18:00:55 -07:00 |
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Ganesh Gore
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3c2055156a
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-11-16 16:12:30 -07:00 |
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Ganesh Gore
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bfb03af2c8
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Added run-task and run-flow functions
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2019-11-16 15:52:32 -07:00 |
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Ganesh Gore
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cb1c7a8030
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Added OpenFPGA bash function utility
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2019-11-16 13:19:00 -07:00 |
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Ganesh Gore
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00ec36c1af
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Added Modelsim error check in log
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2019-11-16 13:18:13 -07:00 |
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Ganesh Gore
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373dbe0718
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First draft for multithreaded Modelsim simulation
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2019-11-16 01:06:09 -07:00 |
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Ganesh Gore
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f05aede868
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Added task support for modelsim script
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2019-11-15 23:23:15 -07:00 |
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Ganesh Gore
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1c4acff79b
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-11-15 14:54:13 -07:00 |
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Ganesh Gore
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f52eaef622
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Updated flow script and skipped travis upload on failure test setup.
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2019-11-15 14:35:15 -07:00 |
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Ganesh Gore
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333d10c94c
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Added vpr_fpga_verilog_print_simulation_ini option
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2019-11-15 14:26:57 -07:00 |
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tangxifan
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4df6402241
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add python script for batch simulations
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2019-11-15 14:23:03 -07:00 |
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tangxifan
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0c2ad5ab5e
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critical bug fixed for some corner cases
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2019-11-13 20:45:41 -07:00 |
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tangxifan
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1291b99d66
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now make ini file generation more flexible: user can specify a name or use the default name
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2019-11-13 12:55:57 -07:00 |
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tangxifan
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d84cd66287
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refactored analysis SDC generator for grids
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2019-11-12 22:18:13 -07:00 |
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tangxifan
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6c58a4dd92
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refactored unused grid block SDC analysis generation
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2019-11-12 10:01:17 -07:00 |
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tangxifan
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8a57a29d2d
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refactoring analysis SDC generation for grids
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2019-11-11 22:38:11 -07:00 |
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tangxifan
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5f219b428c
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refactored analysis SDC generation for switch blocks
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2019-11-11 19:24:39 -07:00 |
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tangxifan
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876733f052
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now we use module manager to generate analysis SDC, being independent from VPR structures
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2019-11-10 21:15:34 -07:00 |
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tangxifan
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a849522be9
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refactored CB SDC analysis generation
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2019-11-10 20:15:16 -07:00 |
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tangxifan
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8e8e59b0ca
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give specific name to mux so that we can bind it to SDC generator
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2019-11-10 19:42:30 -07:00 |
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tangxifan
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3d711823e5
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refactoring SDC generator for unused CBs
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2019-11-10 18:15:13 -07:00 |
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tangxifan
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67b3b25bea
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refactoring analysis sdc generation
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2019-11-10 16:08:49 -07:00 |
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tangxifan
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1f368abfbe
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refactoring analysis SDC generation
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2019-11-10 15:40:54 -07:00 |
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tangxifan
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bcd8237263
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refactored grid PnR SDC generator
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2019-11-09 20:57:54 -07:00 |
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tangxifan
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d226d18d40
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move SDC generator for routing modules to an independent source file
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2019-11-09 11:54:05 -07:00 |
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tangxifan
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a7f2a61d0d
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refactored CB SDC generation
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2019-11-09 11:42:38 -07:00 |
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tangxifan
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4b5ecc516b
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refactored SDC SB constrain generation
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2019-11-09 10:52:15 -07:00 |
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tangxifan
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be574b0d45
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refactored disable routing mux outputs
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2019-11-08 19:05:05 -07:00 |
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tangxifan
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e273c00c9d
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add refactored disable timing for memory cells
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2019-11-08 17:38:07 -07:00 |
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tangxifan
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ea7c981c85
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critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer
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2019-11-08 15:01:30 -07:00 |
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tangxifan
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33b3705ced
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refactoring disable outputs sdc generation
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2019-11-08 11:15:35 -07:00 |
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tangxifan
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35e718b32d
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rename backend sdc generator to be backend assistant
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2019-11-08 10:20:12 -07:00 |
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tangxifan
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14e7744fee
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start refactoring sdc generator, make it geneirc by placing it in parallel to Verilog generator
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2019-11-07 22:20:48 -07:00 |
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tangxifan
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d391983e8c
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passing regression test on dpram benchmarks
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2019-11-07 14:57:46 -07:00 |
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tangxifan
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56b4ee008e
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add test for heterogeneous FPGA and fix bugs
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2019-11-06 17:45:11 -07:00 |
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tangxifan
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4ea5756be6
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bug fixed for std cell MUX2 architecture and add the case to regression tests
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2019-11-06 16:06:47 -07:00 |
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tangxifan
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09eb373a6e
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bug fixing for autocheck top testbench where clock port is not default names
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2019-11-06 12:21:20 -07:00 |
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tangxifan
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0e620f35a4
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bug fixed for MUX2 std cells, avoid duplicated module writing
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2019-11-06 11:45:28 -07:00 |