tangxifan
|
b78f8bec16
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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tangxifan
|
5bcd559851
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[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
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2020-10-30 17:29:04 -06:00 |
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tangxifan
|
0d77916041
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[Tool] Support multi-region frame-based configuration protocol
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2020-10-30 10:43:11 -06:00 |
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tangxifan
|
8ef6ae32fb
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[Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol
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2020-10-29 17:35:55 -06:00 |
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tangxifan
|
987eccf586
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[Tool] Bug fix in multi-region memory bank; Basic test passed
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2020-10-29 16:26:45 -06:00 |
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tangxifan
|
448e88645a
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[Tool] Support multiple memory banks in top-level module
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2020-10-29 12:42:03 -06:00 |
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tangxifan
|
bd49ea95d4
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[Tool] Add function to comput configuration bits by region
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2020-10-28 12:37:09 -06:00 |
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tangxifan
|
446f982410
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[Tool] Add warning when number of regions defined in fabric key is different than architecture
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2020-10-28 11:43:05 -06:00 |
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tangxifan
|
1ef0898f41
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[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
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2020-10-12 12:31:51 -06:00 |
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tangxifan
|
721bcce373
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[Tool] Change analysis SDC file name to track netlist name
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2020-10-10 17:43:35 -06:00 |
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tangxifan
|
e0d7bcfa11
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[Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols
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2020-09-29 12:49:32 -06:00 |
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tangxifan
|
e988e35f81
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[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
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2020-09-29 12:22:10 -06:00 |
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tangxifan
|
180d72f3e5
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[Tool] Add regions to fabric bitstream
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2020-09-28 21:04:08 -06:00 |
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tangxifan
|
e179a58b15
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[OpenFPGA Tool] Bug fix for long runtime
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2020-09-28 20:42:18 -06:00 |
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tangxifan
|
47f3c79927
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[OpenFPGA Tool] Bug fix in module manager due to configurable regions
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2020-09-28 19:08:19 -06:00 |
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tangxifan
|
f93d46a870
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[OpenFPGA Tool] Add multiple configuration chain support in top module builder
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2020-09-28 19:03:19 -06:00 |
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tangxifan
|
552dddffd0
|
[OpenFPGA Tool] Support configurable regions in module manager
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2020-09-28 18:13:07 -06:00 |
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tangxifan
|
052b8b71c7
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[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
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2020-09-27 20:54:58 -06:00 |
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tangxifan
|
154f23b108
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[OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches
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2020-09-26 11:54:06 -06:00 |
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tangxifan
|
1b4e449179
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[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol
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2020-09-25 21:05:20 -06:00 |
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tangxifan
|
6bea712db0
|
[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
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2020-09-25 14:54:51 -06:00 |
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tangxifan
|
8468f25b23
|
[OpenFPGA Tool] Bug fix in the smart fast configuration strategy
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2020-09-24 16:31:55 -06:00 |
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tangxifan
|
46b12611a9
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[OpenFPGA Tool] Bug fix for smart fast configuration
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2020-09-23 22:04:07 -06:00 |
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tangxifan
|
154c9045f6
|
[OpoenFPGA Tool] Bug fix for smart fast configuration
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2020-09-23 21:38:42 -06:00 |
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tangxifan
|
c2c37d7555
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[OpenFPGA Tool] Add more print-out for smart fast configuration
|
2020-09-23 21:34:23 -06:00 |
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tangxifan
|
a3abf81afe
|
[OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration
|
2020-09-23 21:25:06 -06:00 |
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tangxifan
|
064678fe32
|
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
|
2020-09-23 20:27:52 -06:00 |
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tangxifan
|
ad881ea4dc
|
[OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank
|
2020-09-23 18:59:25 -06:00 |
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tangxifan
|
9adeb550dc
|
[OpenFPGA Tool] Bug fix in fabric builder
|
2020-09-23 18:28:00 -06:00 |
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tangxifan
|
6480b06a2d
|
[OpenFPGA tool] Remove out-of-data test blif, architecture and scripts
|
2020-09-23 11:01:53 -06:00 |
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tangxifan
|
26f1a5d9ec
|
[OpenFPGA Tool] Bug fix for repacking no local routing architecture
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2020-09-21 22:22:03 -06:00 |
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tangxifan
|
c6ac02d210
|
[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation
|
2020-09-20 15:21:33 -06:00 |
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tangxifan
|
544c44fe46
|
[FPGA-SPICE] Add VDD and VSS port to module definition
|
2020-09-20 14:58:15 -06:00 |
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tangxifan
|
460fef5807
|
[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
|
2020-09-20 12:58:55 -06:00 |
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tangxifan
|
222bc86cbf
|
[FPGA-SPICE] Add auxiliary SPICE netlist writer
|
2020-09-20 12:53:28 -06:00 |
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tangxifan
|
06c0073a3e
|
[FPGA-SPICE] Add SPICE writer for fpga top module
|
2020-09-20 12:43:48 -06:00 |
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tangxifan
|
1dfb3e06cc
|
[FPGA-SPICE] add SPICE writer for logic blocks
|
2020-09-20 12:38:24 -06:00 |
|
tangxifan
|
5e78e91fdf
|
[FPGA-SPICE] Add SPICE writer for routing blocks
|
2020-09-20 12:27:48 -06:00 |
|
tangxifan
|
0f25b52907
|
[FPGA-Verilog] code format fix
|
2020-09-20 12:18:22 -06:00 |
|
tangxifan
|
2fae311c8e
|
[FPGA-SPICE] Add SPICE writer for memories
|
2020-09-20 12:14:34 -06:00 |
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tangxifan
|
f284f6f8d0
|
[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
|
2020-09-20 12:03:10 -06:00 |
|
tangxifan
|
6801d260e9
|
[FPGA-SPICE] Add SPICE writer for LUT
|
2020-09-20 11:58:11 -06:00 |
|
tangxifan
|
0f9fce92b2
|
[FPGA-SPICE] Add SPICE writer for routing multiplexers
|
2020-09-20 11:49:02 -06:00 |
|
tangxifan
|
c7e3d97d1b
|
[FPGA-SPICE] Add supply voltage generator
|
2020-09-20 11:19:06 -06:00 |
|
tangxifan
|
15df9b3893
|
[FPGA-SPICE] Add SPICE subcircuit writer
|
2020-09-19 23:01:44 -06:00 |
|
tangxifan
|
82e137cbe4
|
[FPGA-SPICE] Add wire module SPICE writer
|
2020-09-19 19:31:16 -06:00 |
|
tangxifan
|
1b2762386c
|
[FPGA-SPICE] Bug fix for essential gate netlist writing
|
2020-09-19 16:52:30 -06:00 |
|
tangxifan
|
26a0a769ea
|
[FPGA-SPICE] Split essential gate SPICE netlists into separated files
|
2020-09-19 16:45:26 -06:00 |
|
tangxifan
|
e102e30d19
|
[FPGA-SPICE] Add support for AND/OR logic gate
|
2020-09-19 16:20:21 -06:00 |
|
tangxifan
|
482d90018f
|
[FPGA-SPICE] Create generic PMOS/NMOS instanciation function
|
2020-09-19 15:33:28 -06:00 |