tangxifan
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940eb937f2
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[Test] add multi-region configuration frame test cases to CI
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2020-10-30 21:21:11 -06:00 |
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tangxifan
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b78f8bec16
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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tangxifan
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5bcd559851
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[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
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2020-10-30 17:29:04 -06:00 |
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tangxifan
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4c14428400
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[Test] Add test case for fast configuration support on multi-region frame-based configuration protocol
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2020-10-30 10:50:00 -06:00 |
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tangxifan
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ca7d43275d
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[Test] Add test case for multi_region configuration frame
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2020-10-30 10:48:29 -06:00 |
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tangxifan
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29da368742
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[Arch] Add architecture example for multi-region frame-based architecture using both set/reset for configurable memories
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2020-10-30 10:46:47 -06:00 |
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tangxifan
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b701bd2640
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[Arch] Add multi-region architecture example for frame-based protocol
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2020-10-30 10:45:14 -06:00 |
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tangxifan
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0d77916041
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[Tool] Support multi-region frame-based configuration protocol
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2020-10-30 10:43:11 -06:00 |
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tangxifan
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1d930d1b5d
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[Architecture] Add missing arch files and bug fix
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2020-10-29 18:08:26 -06:00 |
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tangxifan
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8ef6ae32fb
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[Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol
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2020-10-29 17:35:55 -06:00 |
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tangxifan
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c2c384e24b
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[Doc] update documentation about memory bank definition
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2020-10-29 17:04:25 -06:00 |
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tangxifan
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1ad591c08c
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[Test] Add smart fast configuration test cases for multi-region memory banks to CI
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2020-10-29 16:33:54 -06:00 |
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tangxifan
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153b265a6d
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[Architecture] Add openfpga architecture using multiple memory banks whose memory cell has both reset and set
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2020-10-29 16:32:05 -06:00 |
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tangxifan
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241ebf054a
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[Test] Add a test case for validating fast configuration techniques on multi-region memory banks
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2020-10-29 16:29:46 -06:00 |
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tangxifan
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51f2e7f625
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[Test] Add multi-region memory bank test case to CI
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2020-10-29 16:28:03 -06:00 |
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tangxifan
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987eccf586
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[Tool] Bug fix in multi-region memory bank; Basic test passed
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2020-10-29 16:26:45 -06:00 |
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tangxifan
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ff386001c4
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[Test] Add openfpga task for multi-region memory banks
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2020-10-29 13:56:32 -06:00 |
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tangxifan
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7534474423
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[Arch] Add architecture for multiple-region memory banks
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2020-10-29 13:54:51 -06:00 |
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tangxifan
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448e88645a
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[Tool] Support multiple memory banks in top-level module
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2020-10-29 12:42:03 -06:00 |
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tangxifan
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bd49ea95d4
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[Tool] Add function to comput configuration bits by region
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2020-10-28 12:37:09 -06:00 |
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tangxifan
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446f982410
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[Tool] Add warning when number of regions defined in fabric key is different than architecture
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2020-10-28 11:43:05 -06:00 |
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tangxifan
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efb0162e3f
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[Doc] Bug fix in tutorial due to renamed regression tests
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2020-10-28 08:58:19 -06:00 |
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tangxifan
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29431394a8
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[Doc] Add links to the technical summary in documentation for README
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2020-10-27 10:08:25 -06:00 |
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tangxifan
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90e6021e43
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[Doc] Update README with more links to documentation
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2020-10-27 09:53:57 -06:00 |
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tangxifan
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63f130d948
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[Test] Deploy none constant input test case to CI
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2020-10-13 12:04:07 -06:00 |
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tangxifan
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179ae355d0
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[Test] Do not run icarus verification for non const input test case. Icarus cannot handle the comb. loops
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2020-10-13 12:02:26 -06:00 |
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tangxifan
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97c3bf7ea0
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[Test] Add a test case for non-constant input multiplexers
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2020-10-13 11:58:17 -06:00 |
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tangxifan
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c5bcd93408
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[Architecture] Add the example architecture where std cell-based multiplexers do not have a constant input
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2020-10-13 11:57:21 -06:00 |
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tangxifan
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e5facf8866
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[Test] Deploy const gnd test case to CI
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2020-10-13 11:40:49 -06:00 |
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tangxifan
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99b1e68d92
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[Architecture] Add architecture using GND as constant inputs for multiplexers
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2020-10-13 11:39:27 -06:00 |
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tangxifan
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570b494df7
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[Test] Add test case for using GND signal as constant input for routing multiplexers
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2020-10-13 11:38:54 -06:00 |
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tangxifan
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6b6c018945
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[Test] Add the new test case to CI
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2020-10-12 12:54:51 -06:00 |
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tangxifan
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dc68c52d0a
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[Test] Now use a light architecture to speed up the test case runtime
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2020-10-12 12:53:34 -06:00 |
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tangxifan
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e59377a3ec
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[Flow] bug fix in the sample script for fabric netlist customization
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2020-10-12 12:52:01 -06:00 |
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tangxifan
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8941e38613
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[Test] Enable verification in the new test case
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2020-10-12 12:50:08 -06:00 |
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tangxifan
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9e1fd300dc
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[Test] Add test case for customized location of fabric netlists
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2020-10-12 12:47:58 -06:00 |
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tangxifan
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e510e79c12
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[Flow] Add openfpga shell example script to use fabric netlist option
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2020-10-12 12:42:43 -06:00 |
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tangxifan
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3aeea724de
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[Documentation] Update for new options in fpga-verilog
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2020-10-12 12:36:24 -06:00 |
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tangxifan
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1ef0898f41
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[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
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2020-10-12 12:31:51 -06:00 |
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tangxifan
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ccaa697e5a
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[Documentation] Add links to technical features to examples
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2020-10-10 22:40:37 -06:00 |
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tangxifan
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ea3a1b785c
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[Documentation] Fix the path to OpenFPGA logo in the README
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2020-10-10 21:44:18 -06:00 |
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tangxifan
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b8c20959b6
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[Regression test] Add new test case to CI
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2020-10-10 20:29:00 -06:00 |
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tangxifan
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82e7b159ce
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[Regression test] Add test case for fracturable LUT using AND gate to switch modes
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2020-10-10 20:26:41 -06:00 |
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tangxifan
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d0014878d5
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[Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes
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2020-10-10 20:24:57 -06:00 |
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tangxifan
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721bcce373
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[Tool] Change analysis SDC file name to track netlist name
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2020-10-10 17:43:35 -06:00 |
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tangxifan
|
800931c840
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[Documentation] Add configuration protocol to technical highlights
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2020-10-06 12:16:15 -06:00 |
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tangxifan
|
56ab63d939
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[Documentation] Fix format in table
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2020-10-06 12:02:15 -06:00 |
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tangxifan
|
c8339fc473
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[Documentation] Typo fix
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2020-10-06 12:00:30 -06:00 |
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tangxifan
|
113708c68f
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[Documentation] Reorganization the overview part by adding technical highlights
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2020-10-06 11:56:10 -06:00 |
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tangxifan
|
02e21d115b
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[Documentation] Update 3-rd party tool version requirements
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2020-10-06 10:00:12 -06:00 |