riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Test] Add the new test case to CI

This commit is contained in:
tangxifan 2020-10-12 12:54:51 -06:00
parent dc68c52d0a
commit 6b6c018945
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
.travis/basic_reg_test.sh
View File

@ -63,6 +63,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --deb
echo -e "Testing Verilog testbench generation only";
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs
echo -e "Testing separated Verilog fabric netlists and testbench locations";
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs
echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs