From 6b6c018945f765b246d60791b16370972d3949ea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 12 Oct 2020 12:54:51 -0600 Subject: [PATCH] [Test] Add the new test case to CI --- .travis/basic_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 8f5961618..474667b84 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -63,6 +63,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --deb echo -e "Testing Verilog testbench generation only"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs +echo -e "Testing separated Verilog fabric netlists and testbench locations"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs + echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs