Yitian4Debug
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1d0d8c5417
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Update read_xml_repack_design_constraints.cpp
code clean up
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2023-12-05 10:13:53 -08:00 |
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Yitian4Debug
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e6c9d22ce9
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Update repack_design_constraints.h
code clean up
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2023-12-05 10:10:19 -08:00 |
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Yitian4Debug
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aa51b6d388
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Update repack_design_constraints.h
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2023-12-05 09:40:25 -08:00 |
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Yitian4Debug
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57f3b7af0f
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Update repack_design_constraints.h
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2023-12-05 09:38:27 -08:00 |
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Yitian4Debug
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b765410300
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Update repack_design_constraints.cpp
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2023-12-05 09:37:56 -08:00 |
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Yitian4Debug
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7aa882f82c
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Update read_xml_repack_design_constraints.cpp
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2023-12-05 09:26:05 -08:00 |
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Yitian4Debug
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0e243d1c05
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Update repack_design_constraints.cpp
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2023-12-05 09:17:29 -08:00 |
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Yitian4Debug
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d0958fc017
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Update repack_design_constraints.h
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2023-12-05 09:09:45 -08:00 |
ubuntu
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a50b007d72
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add vtr assert
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2023-12-01 03:02:52 -08:00 |
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ubuntu
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539d41f3df
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reformat the code
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2023-11-29 17:42:13 -08:00 |
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ubuntu
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2511b79bd6
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format the code
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2023-11-29 02:27:53 -08:00 |
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ubuntu
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030f9d8837
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changes according to code review
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2023-11-29 02:12:07 -08:00 |
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ubuntu
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d28f024b61
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minor change
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2023-11-29 01:53:18 -08:00 |
tangxifan
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1aac6681bc
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Merge branch 'master' into repack_debug
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2023-11-22 10:48:59 -08:00 |
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ubuntu
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ee392f1b46
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add ignore_net to repackdesign constraint
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2023-11-21 21:47:03 -08:00 |
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tangxifan
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93cbbf2045
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[core] code format
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2023-10-06 18:20:55 -07:00 |
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tangxifan
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b07111497c
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[core] enable options in xml writers
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2023-10-06 18:20:17 -07:00 |
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tangxifan
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76f446caec
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[core] fixed a bug
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2023-09-25 21:13:11 -07:00 |
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tangxifan
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3adf81046a
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[core] code format
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2023-09-25 17:22:26 -07:00 |
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tangxifan
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5e269e8bc4
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[core] support port merging at grid modules
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2023-09-25 17:21:58 -07:00 |
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tangxifan
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fd99dafad7
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[core] code format
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2023-09-25 16:51:01 -07:00 |
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tangxifan
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96f36a96dd
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[core] syntax
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2023-09-25 16:50:30 -07:00 |
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tangxifan
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ca715f4c82
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[core] developing parser to support subtile port merge
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2023-09-25 16:46:34 -07:00 |
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tangxifan
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0a94763422
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[lib] add module rename assistant
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2023-09-22 18:16:01 -07:00 |
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tangxifan
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278b8e2409
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[lib] fixed a typo which causes outputted module name XMLs carry syntax errors
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2023-09-22 17:37:27 -07:00 |
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tangxifan
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c6175aa514
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[core] code format
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2023-09-17 22:37:48 -07:00 |
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tangxifan
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ef97127c63
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[core] fixed some bugs in testbenches when renaming top modules
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2023-09-17 22:34:00 -07:00 |
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tangxifan
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72a3c05747
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[core] code format
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2023-09-17 13:29:30 -07:00 |
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tangxifan
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ccd4c1861b
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[core] developing new command to write module naming rules
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2023-09-16 19:37:06 -07:00 |
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tangxifan
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37573abc22
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[core] code format
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2023-09-15 23:32:40 -07:00 |
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tangxifan
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bc407e5d69
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[core] code complete for rename modules
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2023-09-15 23:22:31 -07:00 |
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tangxifan
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7913e6cc6a
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[lib] update tests and fixed some bugs
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2023-09-15 17:38:51 -07:00 |
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tangxifan
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b5cf08a3c5
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[lib] add testing
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2023-09-15 17:15:05 -07:00 |
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tangxifan
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74b9f673ec
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[lib] syntax and add missing api
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2023-09-15 17:00:02 -07:00 |
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tangxifan
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636647902e
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[lib] developing io for module name map
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2023-09-15 16:53:24 -07:00 |
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tangxifan
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e5bc936144
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[lib] developing io
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2023-09-15 16:19:10 -07:00 |
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tangxifan
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b65dda90c4
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[lib] developing naming manager
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2023-09-15 16:02:13 -07:00 |
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tangxifan
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af67b02cca
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[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
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2023-09-15 13:51:14 -07:00 |
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tangxifan
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3273728bc3
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[lib] code format
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2023-08-26 18:15:30 -07:00 |
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tangxifan
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ac5873bac2
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[lib] fixed some bugs in message show
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2023-08-26 18:12:25 -07:00 |
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tangxifan
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97619fc545
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[lib] add verbose output option to fabric key assistant
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2023-08-26 18:07:08 -07:00 |
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tangxifan
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cfaae55bda
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[lib] debugged fabric key assistant
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2023-08-26 13:19:18 -07:00 |
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tangxifan
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adae7392e5
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[lib] developing fabric key assistant
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2023-08-26 12:54:12 -07:00 |
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tangxifan
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d3895c3dc0
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[core] code format
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2023-08-03 17:34:25 -07:00 |
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tangxifan
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53050b94ab
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[core] developing memory group modules in grid modules
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2023-08-01 17:50:03 -07:00 |
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tangxifan
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23643f3fb1
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[core] developing the physical memory block builder
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2023-07-31 22:57:26 -07:00 |
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tangxifan
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95a32628ab
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[core] fixed the bug in arch bitgen due to the tile modules
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2023-07-25 14:15:15 -07:00 |
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tangxifan
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7783229d90
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Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_fabric_tile
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2023-07-23 20:44:50 -07:00 |
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tangxifan
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6607bb7e48
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[core] now fpga verilog supports tile modules
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2023-07-18 22:35:22 -07:00 |
Chung Shien Chai
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b2f5b493c2
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Fix the cpp-format
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2023-07-16 13:08:40 -07:00 |