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OpenFPGA
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109 Commits

Author SHA1 Message Date
AurelienUoU 60f7ab0465 Start heterogeneous dev 2019-07-02 10:16:10 -06:00
Ganesh Gore 54f6ca2687 Added lattice benchmark settings 2019-07-01 11:07:23 -06:00
tangxifan c54f3905d5 fixed broken fpga flow 2019-06-28 13:07:04 -06:00
tangxifan 1332ba62e8 update tileable rr_graph generator to improve routability and also enable assoicated testing 2019-06-27 17:52:25 -06:00
tangxifan 4d3b5f12b4 fixed bugs for UNIVERSAL and WILTON switch blocks 2019-06-25 14:15:29 -06:00
AurelienUoU c76dbaac33 Update regression test avoiding overwritting files 2019-06-14 11:44:44 -06:00
tangxifan 0902d1e75a c++ string is not working, use char which is stable 2019-06-13 18:38:46 -06:00
AurelienUoU bf13c1f731 Add a script to create a new file with correct path rather than overwrite the existing 2019-06-11 14:28:58 -06:00
tangxifan d737c4ff46 fix path in regression test! TODO: must keep a duplicated copy for template.xml 2019-06-07 23:31:42 -06:00
tangxifan 0f1ed19ad0 Revert to the use of sprintf instead std::string. Have no idea why string is not working 2019-06-07 18:54:57 -06:00
AurelienUoU fcc10d8acf Correct fpga_flow/arch/template files 2019-06-04 16:45:04 -06:00
AurelienUoU a2f6ded2a2 Add path modification in file changing a keyword into OpenFPGA full path 2019-06-04 15:21:15 -06:00
AurelienUoU ba05a08ef0 Path correction in tech debugging + correction of yosys rewrite file in fpga_flow 2019-05-30 09:52:19 -06:00
AurelienUoU f934f6f0a3 Debug step 2019-05-28 15:01:16 -06:00
AurelienUoU e0717369e1 Re-insert power option in regression test 2019-05-28 09:48:03 -06:00
AurelienUoU d3f0ab59c2 Remove -power token until option is fixed 2019-05-23 19:26:25 -06:00
AurelienUoU 3811c18953 Correct syntax error in tokens of regression_fpga_flow.sh 2019-05-23 18:33:47 -06:00
AurelienUoU 1018134726 Update yosys to latest version + add simulation in fpga_flow 2019-05-23 17:55:49 -06:00
AurelienUoU 2b04376209 Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
AurelienUoU b4c97f86a3 Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
tangxifan d10e05f5cc Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-21 12:16:33 -06:00
tangxifan ec3b4c86c4 update file organization and be ready for SB/CB class 2019-05-21 12:15:38 -06:00
AurelienUoU 199cd99b23 Add dummy clock name in ace2 commands 2019-05-21 10:35:12 -06:00
AurelienUoU 2392d11790 Add debug command to understandn travis issue with ace 2019-05-20 16:06:37 -06:00
AurelienUoU becb90cd16 Correct syntax error in ace2 log file generation 2019-05-20 13:56:50 -06:00
AurelienUoU fbebb45bf2 Path correction in config file 2019-05-20 11:13:30 -06:00
AurelienUoU 82c76a2c39 Test removing the shell specification in fpga_flow.pl 2019-05-20 10:35:33 -06:00
AurelienUoU 43a64c26e8 Change tcsh to csh in fpga_flow.pl -> tcsh not found by travis 2019-05-20 09:44:38 -06:00
AurelienUoU 17ad905b14 Update flow and allow netlist generation 2019-05-17 17:00:38 -06:00
AurelienUoU df8bb0db1a Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
AurelienUoU ff9b84d800 Bug fix in Icarus requirement 2019-05-10 14:07:32 -06:00
Baudouin Chauviere 79f3db9880 removed the now useless tutorial part 2018-12-10 13:57:01 -07:00
tangxifan 72fbd8d6a8 update blif reader to identify clock signals 2018-12-10 13:28:44 -07:00
Baudouin Chauviere 79930982cf Changed for the naming 2018-12-08 16:19:38 -07:00
tangxifan b3c1018e28 fixed a bug in wired LUT 2018-12-06 16:50:30 -07:00
Baudouin Chauviere 0b1ccf7722 and in the config path as well 2018-12-06 14:57:32 -07:00
Baudouin Chauviere fe47b3d21f Changing arch from memory dec to scff. Get the bitstream from go.sh 2018-12-06 14:03:17 -07:00
tangxifan 4f5f8de46f Add Yosys and update flow_flow Perl Script 2018-11-30 21:14:43 -07:00
Baudouin Chauviere d55ecd154b Add the PTM to the benchmark flow 2018-11-21 11:32:34 -07:00
Baudouin Chauviere 8ce0a84bc1 Correction of the global make, the fpga_flow and the doc 2018-11-20 14:47:15 -07:00
Baudouin Chauviere 03e902023a Perl script integrated to flow. rm shell one 2018-11-20 13:32:11 -07:00
Baudouin Chauviere 15d69e2bb1 Generation script finished TODO: integration in flow 2018-11-20 13:24:31 -07:00
Baudouin Chauviere e74f05a161 Switching from sh to pl 2018-11-20 10:15:31 -07:00
Baudouin Chauviere 9611576d6a Update on the examples to respect the new syntax 2018-11-19 15:50:29 -07:00
Baudouin Chauviere dddca8acbb Global Makefile and typo correction 2018-10-24 17:34:51 -06:00
Baudouin Chauviere 9538dbd644 Config script written and changed some rights for some files 2018-10-24 15:59:32 -06:00
Aurelien Alacchi e0c2fc2c8a Documentation_code&example_update 2018-10-12 15:50:09 -06:00
Baudouin Chauviere e5c6471fc2 Update of the Readme and added an example 
ReadMe is now cleaner
 2018-10-03 17:10:29 -06:00
Baudouin Chauviere 4a4f539365 Change rights script 2018-09-27 15:51:09 -06:00
Baudouin Chauviere 665678267d Change rights script 2018-09-27 15:17:48 -06:00
Xifan Tang 1cf066d3ad Fixing minor bugs 2018-09-06 14:25:23 -06:00
Xifan Tang c009a37580 fix minor bugs 2018-09-04 17:56:37 -06:00
Xifan Tang 42da9160f0 Clean codes and update 2018-09-04 17:49:20 -06:00
Xifan Tang 00ecd0bb1d Cleanup codes and organization 2018-09-04 17:31:30 -06:00
Xifan Tang cb15bb5082 Clean code and fix minor bugs 2018-08-10 13:46:00 -06:00
Xifan Tang b0ef554b35 Add power property XML 2018-08-09 11:27:36 -06:00
Xifan Tang 90669d19c5 Update FPGA-SPICE and flow configurations 2018-08-09 11:27:16 -06:00
Xifan Tang fe13168f8f Add ABC and ACE2, fix bugs for fpga_flow and VPR 2018-07-27 22:54:52 -06:00
Xifan Tang 158dec405e Reorganize the code directory 2018-07-26 11:28:21 -06:00