tangxifan
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89086ed080
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add verbose output to build grid module
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2020-02-13 15:38:26 -07:00 |
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tangxifan
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072965cd64
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make grid module builder online; basic support on physical tiles
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2020-02-13 15:27:16 -07:00 |
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tangxifan
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59d579425e
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add utils for duplicate pins in grid module builder
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2020-02-12 20:48:07 -07:00 |
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tangxifan
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895d5b5a0a
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add utils for grid module builder
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2020-02-12 20:25:05 -07:00 |
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tangxifan
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002c2795fe
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add memory module builder
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2020-02-12 20:06:38 -07:00 |
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tangxifan
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8e381f0581
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add wire module builder
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2020-02-12 19:57:15 -07:00 |
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tangxifan
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e842150cc5
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add lut module builder
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2020-02-12 19:52:41 -07:00 |
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tangxifan
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fddd3c9463
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add mux module builder
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2020-02-12 19:45:14 -07:00 |
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tangxifan
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ea7d879b4f
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add decoder module builder
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2020-02-12 18:28:50 -07:00 |
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tangxifan
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f11832b8cf
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |
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tangxifan
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13fadd0f91
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move compact routing hierarchy to build_fabric command
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2020-02-12 15:49:47 -07:00 |
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tangxifan
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c78d3e9af1
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add mux library builder
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2020-02-12 14:58:23 -07:00 |
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tangxifan
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ce63b1cc62
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add circuit model binding for direct connections and enhance model type checking
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2020-02-12 11:40:20 -07:00 |
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tangxifan
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4a05cec037
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add rr_segment binding to circuit model
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2020-02-12 11:21:40 -07:00 |
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tangxifan
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a736e09c29
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add rr_switch binding in link openfpga arch command
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2020-02-12 10:52:20 -07:00 |
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tangxifan
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feccbc5780
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add more methods to link routing to circuit models in device annotation
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2020-02-12 10:08:54 -07:00 |
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tangxifan
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a31d6c6d1e
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rename pb_type annotation to device annotation
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2020-02-12 09:52:18 -07:00 |
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tangxifan
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4367dba9b7
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move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
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2020-02-11 21:02:58 -07:00 |
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tangxifan
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175bef014a
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add compact_routing hierarchy command
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2020-02-11 17:40:37 -07:00 |
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tangxifan
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1372f748f1
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put GSB builder online
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2020-02-11 16:37:14 -07:00 |
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tangxifan
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85f3826939
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put device rr_gsb online. Ready to plug-in
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2020-02-09 14:58:23 -07:00 |
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tangxifan
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230c7b709a
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put rr_gsb data structure online
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2020-02-09 00:20:44 -07:00 |
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tangxifan
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0b6b3bc029
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start adapting rr_gsb related data structure
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2020-02-07 11:32:33 -07:00 |
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tangxifan
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3d7eff64b9
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bug fixed for lut truth table fixup. Results look good
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2020-02-06 17:47:25 -07:00 |
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tangxifan
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ed9e038845
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add functionality of LUT truth table fix-up
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2020-02-06 17:14:29 -07:00 |
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tangxifan
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99f5a86b49
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bug fixed for routing annotation and routing net fix-up
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2020-02-06 12:54:55 -07:00 |
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tangxifan
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cccbb9fd49
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add missing files
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2020-02-05 22:12:44 -07:00 |
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tangxifan
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dad204674b
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done an initial version of clustering net fix-up based on routing results. Debugging on the way
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2020-02-05 21:50:52 -07:00 |
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tangxifan
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5006a4395d
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bring RRGraph object and writer online
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2020-01-31 16:39:40 -07:00 |
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tangxifan
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75c3507acf
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add verbose output option for openfpga linking architecture
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2020-01-31 11:36:58 -07:00 |
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tangxifan
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392ab0f027
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move duplicated codes on message printing to functions
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2020-01-31 10:53:41 -07:00 |
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tangxifan
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afde9808da
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add check codes for physical pb_graph_node and pb_graph_pin annotation
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2020-01-31 10:47:05 -07:00 |
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tangxifan
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fdc304a0fb
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fixed a bug in mapping pb_graph pins using rotation offset
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2020-01-30 22:00:53 -07:00 |
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tangxifan
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02d6256e95
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pass simple test on pb_type annotation for frac_lut5 architecture
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2020-01-30 21:39:44 -07:00 |
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tangxifan
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007e1997e6
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add pb_graph pin annotation
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2020-01-30 19:40:40 -07:00 |
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tangxifan
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d62c9fe86f
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adding pb_graph_node annotation
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2020-01-30 16:40:13 -07:00 |
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tangxifan
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e48ab8cb44
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move annotation source files to a separated folder
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2020-01-30 13:37:41 -07:00 |
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tangxifan
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568ed120c2
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change report naming fix-up to be XML format
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2020-01-29 21:53:56 -07:00 |
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tangxifan
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f28ca3ffd0
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add more echo to log
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2020-01-29 18:58:57 -07:00 |
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tangxifan
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87f1ca1151
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add naming fix-up report generation
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2020-01-29 18:56:47 -07:00 |
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tangxifan
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2dc4c26257
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add naming fix-up
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2020-01-29 17:49:33 -07:00 |
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tangxifan
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8c86c0af04
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add check netlist naming conflict command and functions
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2020-01-29 16:23:41 -07:00 |
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tangxifan
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d2c47693f6
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add check codes for mode bits annotation to pb_types and clean up utils source files
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2020-01-29 14:29:00 -07:00 |
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tangxifan
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a4381563bc
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move check codes to separated source files
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2020-01-29 13:47:59 -07:00 |
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tangxifan
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b67358d2c5
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add check codes for physical pb_type circuit model annotation
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2020-01-29 12:56:49 -07:00 |
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tangxifan
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a722438fa3
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add mode bits binding to pb_type annotation
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2020-01-29 12:27:55 -07:00 |
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tangxifan
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61b487eb75
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show more information in the log file
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2020-01-29 11:29:41 -07:00 |
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tangxifan
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399ba8d648
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add pb type port mapping to circuit model ports
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2020-01-29 11:24:14 -07:00 |
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tangxifan
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cf3c5b5c42
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add circuit model type checking for physical pb_type annotation
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2020-01-29 10:41:02 -07:00 |
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tangxifan
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8a7a4dc48e
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add physical type annotation for interconnects and inference
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2020-01-28 21:59:10 -07:00 |