tangxifan
|
881672d46a
|
update thru channel arch for avoid buggy pin locations
|
2020-08-19 19:52:35 -06:00 |
|
tangxifan
|
bf08e1841c
|
add new test case using thru channels
|
2020-08-19 17:58:34 -06:00 |
|
tangxifan
|
f0bc6f83f1
|
disable buffer absorbing in the template script for bitstream generation. This is applicable to a wide range of benchmarks
|
2020-08-19 15:34:59 -06:00 |
|
tangxifan
|
18735894f9
|
bug fix in openfpga arch: data1 and out1 should have the same offset as the data2 and out2
|
2020-08-19 15:27:30 -06:00 |
|
tangxifan
|
3273f441fe
|
bug fix in the flagship vpr arch
|
2020-08-19 15:23:20 -06:00 |
|
tangxifan
|
aa4a9b28cc
|
start testing the initial offset in the flagship architecture
|
2020-08-19 15:03:46 -06:00 |
|
tangxifan
|
f64079641d
|
bug fix in flagship vpr arch with frac mem and dsp
|
2020-08-19 12:43:58 -06:00 |
|
tangxifan
|
d7efdf35b6
|
add custom pin location to the flagship vpr arch with frac mem and dsp
|
2020-08-19 11:15:25 -06:00 |
|
tangxifan
|
dbd93e429d
|
now pro_blif.pl can accept customized clock name
|
2020-08-19 09:43:44 -06:00 |
|
tangxifan
|
743167521a
|
add Verilog design for fracturable 32k memory
|
2020-08-18 21:13:46 -06:00 |
|
tangxifan
|
42b5ea2cb1
|
bug fix in openfpga arch for frac mem and dsp
|
2020-08-18 20:42:36 -06:00 |
|
tangxifan
|
3ee4e10aa8
|
bug fix in the frac mem & DSP vpr arch
|
2020-08-18 17:25:45 -06:00 |
|
tangxifan
|
098859fe06
|
bug fix in the frac memory & DSP architecture
|
2020-08-18 15:05:51 -06:00 |
|
tangxifan
|
21c7eaa9cf
|
add 36-bit fracturable multiplier Verilog
|
2020-08-18 14:06:08 -06:00 |
|
tangxifan
|
f833e0ec66
|
add a flagship architecture using fracturable memory and dsp
|
2020-08-17 17:49:51 -06:00 |
|
tangxifan
|
1ca2829868
|
update readme for vpr architecture naming
|
2020-08-17 13:54:26 -06:00 |
|
tangxifan
|
cadf29022e
|
add README to explain the organization of regression tests
|
2020-07-28 13:44:06 -06:00 |
|
tangxifan
|
f33422d4d7
|
add regression test to track runtime on big fpga devices using practical benchmarks
|
2020-07-28 12:38:42 -06:00 |
|
tangxifan
|
534c609e17
|
add fixed layouts to a flagship architecture to test bitstream generation runtime
|
2020-07-28 11:51:50 -06:00 |
|
tangxifan
|
a156807559
|
enrich basic regression tests to cover more critical microbenchmarks
|
2020-07-27 19:47:43 -06:00 |
|
tangxifan
|
5d83abb2cf
|
bug fix in read architecture bitstream and regression tests
|
2020-07-27 19:37:05 -06:00 |
|
tangxifan
|
31e7a753a6
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-07-27 19:22:16 -06:00 |
ganeshgore
|
747c062f86
|
BugFix : Flow script accepts extra OpenFPGA arguments
|
2020-07-27 18:10:43 -06:00 |
|
tangxifan
|
50cc4dfba3
|
classify regression test to dedicated categories
|
2020-07-27 17:18:59 -06:00 |
|
tangxifan
|
5595ee9052
|
refine the test case for load external arch bitstream
|
2020-07-27 16:53:29 -06:00 |
|
tangxifan
|
cec6bf0b6f
|
add or2 microbenchmark for testing external arch bitstream
|
2020-07-27 15:59:03 -06:00 |
|
tangxifan
|
4174fbf77d
|
add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
|
2020-07-27 15:54:46 -06:00 |
|
tangxifan
|
a3eba8acbe
|
update task files using the new syntax on SHELL variables
|
2020-07-27 15:25:49 -06:00 |
|
tangxifan
|
615b557dc4
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-07-27 14:48:23 -06:00 |
|
tangxifan
|
dc7012d590
|
update regression tests for split fabric_bitstream commands
|
2020-07-27 14:24:48 -06:00 |
|
ganeshgore
|
45af056304
|
TASK_NAME and TASK_DIR variables are avaialble in config file now
|
2020-07-27 14:14:57 -06:00 |
|
ganeshgore
|
0e46e0d857
|
Updated task.conf format to have transparent shell variables
|
2020-07-27 14:08:58 -06:00 |
|
tangxifan
|
177de90822
|
bug fix in example scripts
|
2020-07-26 22:10:04 -06:00 |
|
tangxifan
|
f687774452
|
bug fix in template scripts
|
2020-07-26 21:46:03 -06:00 |
|
tangxifan
|
41a76126b9
|
add fabric bitstream writer to CI
|
2020-07-26 21:44:42 -06:00 |
|
tangxifan
|
c87f6b75b9
|
add test case for FPGA-SPICE
|
2020-07-24 19:12:35 -06:00 |
|
tangxifan
|
020154b0cd
|
add depopulate crossbar test case
|
2020-07-24 18:06:02 -06:00 |
|
tangxifan
|
021fedbc12
|
update fabric key to synchronize with new module/instance naming
|
2020-07-24 12:55:40 -06:00 |
|
tangxifan
|
fefcd88f14
|
update openfpga architecture README for power-gating
|
2020-07-22 21:55:59 -06:00 |
|
tangxifan
|
22159531c5
|
bug fix in power gating support of FPGA-Verilog
|
2020-07-22 20:21:38 -06:00 |
|
tangxifan
|
ca867ea6fa
|
add power gate inverter test case (full testbench)
|
2020-07-22 20:09:52 -06:00 |
|
tangxifan
|
87ef7f9f99
|
add power gate example architecture
|
2020-07-22 20:06:10 -06:00 |
|
tangxifan
|
8ade40713a
|
add missing architecture for CI
|
2020-07-22 14:07:39 -06:00 |
|
tangxifan
|
1a1c3885e7
|
use k6 n10 in mux designs to speed up CI
|
2020-07-22 13:54:09 -06:00 |
|
tangxifan
|
95c1fe61e1
|
use k6 n8 in mux design to speed up CI
|
2020-07-22 13:49:03 -06:00 |
|
tangxifan
|
f754c8af06
|
use k6_n10 architecture to reduce CI runtime
|
2020-07-22 13:45:55 -06:00 |
|
tangxifan
|
92c3449999
|
bug fix in the regression test due to benchmark changes
|
2020-07-22 13:17:05 -06:00 |
|
tangxifan
|
05dccadf21
|
bug fix in the testcases using yosys_vpr flow
|
2020-07-22 12:44:19 -06:00 |
|
tangxifan
|
7d39e136a4
|
enrich micro benchmarks
|
2020-07-22 12:33:52 -06:00 |
|
tangxifan
|
1d36de817f
|
adapt generate bitstream testcase to use yosys vpr flow
|
2020-07-22 12:24:34 -06:00 |