tangxifan
|
e959821813
|
[Tool] Enhance internal check functions for tile annotation
|
2020-11-11 13:59:24 -07:00 |
|
tangxifan
|
4dc0fb81c5
|
[Tool] Bug fix for clang compilation error
|
2020-11-10 20:32:58 -07:00 |
|
tangxifan
|
c61ec5a8b8
|
[Tool] Bug fix for defining global ports from tiles
|
2020-11-10 20:31:14 -07:00 |
|
tangxifan
|
67af145455
|
[Tool] Add XML writer for tile annotation
|
2020-11-10 14:51:46 -07:00 |
|
tangxifan
|
6fbdbe68ae
|
[Tool] Add tile annotation parser
|
2020-11-10 14:32:24 -07:00 |
|
tangxifan
|
0a273ffab6
|
[Tool] Bug fix in the tight requirements on CCFF circuit model
|
2020-11-06 11:16:46 -07:00 |
|
tangxifan
|
ba0120bd76
|
[Tool] Remove the limitation on requiring Qb ports for CCFF
|
2020-11-06 11:10:04 -07:00 |
|
tangxifan
|
37c10f0cb5
|
[Tool] Add mappable I/O support and enhance I/O support
|
2020-11-04 20:21:49 -07:00 |
|
tangxifan
|
f1ce816d6c
|
[Tool] Force inout port to be mandatory for I/O cells
|
2020-11-02 15:14:02 -07:00 |
|
tangxifan
|
e850dd5314
|
[Tool] Relax checking codes for embedded I/O circuit models
|
2020-11-02 13:54:31 -07:00 |
|
tangxifan
|
b78f8bec16
|
[Tool] Bug fixed for multi-region configuration frame
|
2020-10-30 21:19:20 -06:00 |
|
tangxifan
|
1e70825383
|
[OpenFPGA Tool] Add XML syntax for configurable regions
|
2020-09-28 13:51:43 -06:00 |
|
tangxifan
|
052b8b71c7
|
[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
|
2020-09-27 20:54:58 -06:00 |
|
tangxifan
|
491433fae2
|
[OpenFPGA Tool] Update XML parser for fabric regions
|
2020-09-27 20:41:01 -06:00 |
|
tangxifan
|
48b2bff0d9
|
[OpenFPGA Tool] Update fabric key data structure to support regions
|
2020-09-27 20:08:11 -06:00 |
|
tangxifan
|
94047037c5
|
[OpenFPGA Tool] Streamline codes in openfpga arch parser
|
2020-09-27 14:33:14 -06:00 |
|
tangxifan
|
51d96244c6
|
[OpenFPGA Tool] Remove deprecated XML syntax
|
2020-09-26 14:30:57 -06:00 |
|
tangxifan
|
8b8ce22fd1
|
[OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library
|
2020-09-23 20:37:28 -06:00 |
|
tangxifan
|
064678fe32
|
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
|
2020-09-23 20:27:52 -06:00 |
|
tangxifan
|
f284f6f8d0
|
[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
|
2020-09-20 12:03:10 -06:00 |
|
tangxifan
|
8b6c8f73e9
|
[OpenFPGA code] fix bug for clang compatibility
|
2020-09-14 21:26:53 -06:00 |
|
tangxifan
|
c23742c751
|
[OpenFPGA code] fix bug for clang compatibility
|
2020-09-14 20:13:27 -06:00 |
|
tangxifan
|
fc6bfdc7a2
|
[OpenFPGA Code] Patch syntax compatibility for older gcc
|
2020-09-14 18:55:21 -06:00 |
|
tangxifan
|
c31d36deb6
|
[Regression Tests] Deploy output buffer only routing multiplexer testcase to CI
|
2020-09-14 16:16:03 -06:00 |
|
tangxifan
|
9c66a35bf6
|
[arch language] Now circuit library will automatically identify the default circuit model if needed
|
2020-08-23 14:06:03 -06:00 |
|
tangxifan
|
b83319bf14
|
[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
|
2020-08-23 13:48:22 -06:00 |
|
tangxifan
|
161d660837
|
update documentation for the initial offset when mapping physical pins
|
2020-08-19 15:00:46 -06:00 |
|
tangxifan
|
3eea12ceae
|
added a new XML syntax: initial offset for physical mode pin mapping
|
2020-08-19 14:43:44 -06:00 |
|
tangxifan
|
2712c354a9
|
now physical pb_port binding support multiple ports
|
2020-08-18 12:38:56 -06:00 |
|
tangxifan
|
35af0dd676
|
streamline fabric bitstream file format
|
2020-07-27 16:34:43 -06:00 |
|
tangxifan
|
92d2d2d849
|
add fabric bitstream XML writer
|
2020-07-26 21:00:57 -06:00 |
|
tangxifan
|
a3d22c56e3
|
bug fix in FPGA-SPICE
|
2020-07-24 19:51:32 -06:00 |
|
tangxifan
|
6d046efc52
|
add max_width to technology library XML syntax to support multi-bin transistor in FPGA-SPICE
|
2020-07-24 16:25:27 -06:00 |
|
tangxifan
|
f573fa3ee0
|
move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
|
2020-07-22 18:47:12 -06:00 |
|
tangxifan
|
de4586217f
|
now device binding is not mandatory for circuit models
|
2020-07-14 12:04:22 -06:00 |
|
tangxifan
|
e2b492f184
|
add circuit model tech binding
|
2020-07-13 20:35:10 -06:00 |
|
tangxifan
|
62fd0947f5
|
using a unified string to replace multi net names to save memory of bitstream database
|
2020-07-08 16:28:20 -06:00 |
|
tangxifan
|
824b56f14c
|
fabric key can now accept instance name only; decoders are no longer part of the key
|
2020-07-06 16:42:33 -06:00 |
|
tangxifan
|
1ad6e8292a
|
move constants from verilog domain to common so that FPGA-SPICE can share
|
2020-07-05 11:39:46 -06:00 |
|
tangxifan
|
2a9377b3f4
|
use encoded address in storage of fabric bitstream to save memory
|
2020-07-03 15:12:29 -06:00 |
|
tangxifan
|
70d9678578
|
reserve child block in bistream manager
|
2020-07-03 14:04:10 -06:00 |
|
tangxifan
|
7d9c36aae1
|
use length instead of msb in bitstream manager for block bits to save memory
|
2020-07-03 12:06:15 -06:00 |
|
tangxifan
|
2783fda344
|
use index range instead of vector for block bitstream
|
2020-07-03 11:42:38 -06:00 |
|
tangxifan
|
6ea857ae6c
|
use fast method to inquire number of bits and blocks in bitstream databases
|
2020-07-03 10:55:25 -06:00 |
|
tangxifan
|
6397cbe9d2
|
remove unused data in bitstream manager to compact memory usage
|
2020-07-03 10:35:35 -06:00 |
|
tangxifan
|
246b4d5ac6
|
reserve block bits to save memory
|
2020-07-02 21:52:32 -06:00 |
|
tangxifan
|
043fb54206
|
remove unused data in bitstream database
|
2020-07-02 20:53:18 -06:00 |
|
tangxifan
|
9799fea48f
|
optimizing bitstream storage
|
2020-07-02 19:33:53 -06:00 |
|
tangxifan
|
dee4be96af
|
reserve all the input/output net storage in bitstream manager
|
2020-07-02 19:17:34 -06:00 |
|
tangxifan
|
f97e3bfba6
|
add timer to openfpga shell
|
2020-07-02 18:02:33 -06:00 |
|
tangxifan
|
e82d0d9f34
|
drop id list in bitstream manager to save memory usage
|
2020-07-02 16:18:32 -06:00 |
|
tangxifan
|
9f19c36a89
|
use char in fabric bitstream to save memory footprint
|
2020-07-02 15:56:50 -06:00 |
|
tangxifan
|
405824081b
|
reserve configuration blocks and bits in bitstream manager builder to be memory efficient
|
2020-07-02 15:28:52 -06:00 |
|
tangxifan
|
9d32a5b81f
|
add alias name support for fabric key
|
2020-06-27 14:59:53 -06:00 |
|
tangxifan
|
b36da17a08
|
bug fix for directory creation when the input is an empty string
|
2020-06-25 10:34:34 -06:00 |
|
tangxifan
|
e2d3ac78ec
|
skip empty lines in OpenFPGA shell
|
2020-06-25 10:18:05 -06:00 |
|
tangxifan
|
aded675633
|
rename files in fpga bitstream library to be consistent with conventions
|
2020-06-21 13:06:39 -06:00 |
|
tangxifan
|
2f33c35a4f
|
add example XML file for bitstream
|
2020-06-20 19:05:44 -06:00 |
|
tangxifan
|
3bcdd0e1d4
|
clean up writer format for bitstream
|
2020-06-20 19:01:33 -06:00 |
|
tangxifan
|
1e763515b3
|
bug fix in bitstream parser and writer
|
2020-06-20 18:39:21 -06:00 |
|
tangxifan
|
675a59ecb8
|
Move fpga_bitstream to the libopenfpga library and add XML reader
|
2020-06-20 18:25:17 -06:00 |
|
tangxifan
|
a5055e9d26
|
add support about loading external fabric key
|
2020-06-12 13:03:11 -06:00 |
|
tangxifan
|
3499b4d3e7
|
add fabric key writer for top-level module
|
2020-06-12 10:41:34 -06:00 |
|
tangxifan
|
f081cef495
|
add fabric key library
|
2020-06-12 00:07:04 -06:00 |
|
tangxifan
|
58807bfcb3
|
remove simulation settings from openfpga arch data structure
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
f26550141f
|
add missing files
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
15f087598c
|
split simulation settings to a separated XML file
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
8267dad8ef
|
add decoder support for Z signals
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
b8c449d520
|
add comments for decoding functions to help debugging the frame-based decoders
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a0d3b4e95
|
fix the broken CI/regression tests due to incorrect file path
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a26bb5eef
|
add advanced check in configurable memories
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
62c506182c
|
start developing frame-based configuration protocol
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
f52b5d5b4c
|
use error code in read_arch command
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
05d276097e
|
critical bug fixed in openfpga shell so that our command parse results should be reset each time before parsing a line
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
6aff33dd35
|
add fabric hierarchy writer
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
8726c618eb
|
add time unit support on SDC generator. Now users can define time_unit thru cmd-line options
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
8695c5ee78
|
add options to use general-purpose wildcards in SDC generator
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
8ac6e10727
|
bug fix in lut and mux module generation on supporting spypads
|
2020-04-22 14:41:16 -06:00 |
|
tangxifan
|
07a384e440
|
now use openfpga tokenizer to trim command line string in openfpga shell
|
2020-04-13 11:08:31 -06:00 |
|
tangxifan
|
e6c896d583
|
now inout must be global port and I/O port so that it will appear in the top-level module
|
2020-04-08 16:54:08 -06:00 |
|
tangxifan
|
b9dab2baaf
|
add exit codes to command execution in shell context
|
2020-04-08 16:18:05 -06:00 |
|
tangxifan
|
1fb37f4c71
|
improve directory creator to support same functionality as 'mkdir -p'
|
2020-04-08 12:55:09 -06:00 |
|
tangxifan
|
e31dc1f2f2
|
openfpga shell now support continued line charactor '\'
|
2020-04-07 21:27:51 -06:00 |
|
tangxifan
|
33315f0521
|
now openfpga shell allow empty space at beginning and end of each line in script mode
|
2020-04-07 20:46:45 -06:00 |
|
tangxifan
|
6eb125ec2a
|
Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
|
2020-04-06 14:09:52 -06:00 |
|
tangxifan
|
5f4e7dc5d4
|
support gpinput and gpoutput ports in module manager and circuit library
|
2020-04-05 16:52:21 -06:00 |
|
tangxifan
|
8b583b7917
|
debugging spy port builder in module manager
|
2020-04-05 16:01:25 -06:00 |
|
tangxifan
|
ff9cc50527
|
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
|
2020-03-27 20:09:50 -06:00 |
|
tangxifan
|
3647548526
|
clean up on the shell echo commands
|
2020-03-20 11:07:45 -06:00 |
|
tangxifan
|
3aca7b498c
|
Show help desk when a command is called inside shell without satisfying the dependency
|
2020-03-09 09:34:21 -06:00 |
|
tangxifan
|
b035b4c87f
|
debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
|
2020-02-21 12:16:50 -07:00 |
|
tangxifan
|
c6c3ef71f3
|
adapt all the Verilog submodule writers and bring it onlien
|
2020-02-16 13:35:18 -07:00 |
|
tangxifan
|
a88c4bc954
|
add decode utils to libopenfpga and adapt local decoder writer in Verilog
|
2020-02-16 12:21:59 -07:00 |
|
tangxifan
|
622c7826d1
|
start transplanting fpga_verilog
|
2020-02-15 15:03:00 -07:00 |
|
tangxifan
|
59c13550e0
|
add direct annotation with inter-column/row syntax
|
2020-02-14 17:40:59 -07:00 |
|
tangxifan
|
df3ae60954
|
add default configurable memory model set-up when reading openfpga architecture XML
|
2020-02-12 15:19:40 -07:00 |
|
tangxifan
|
99f5a86b49
|
bug fixed for routing annotation and routing net fix-up
|
2020-02-06 12:54:55 -07:00 |
|
tangxifan
|
87f1ca1151
|
add naming fix-up report generation
|
2020-01-29 18:56:47 -07:00 |
|
tangxifan
|
24b180b298
|
change the mode bit storage in annotation data structure from string to vector of integers
|
2020-01-29 11:59:20 -07:00 |