tangxifan
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c2066cc63c
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[core] fixed a bug where pb/cb/sb instance name is not assigned correctly in bitstream manager under tile modules
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2023-07-27 13:33:23 -07:00 |
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tangxifan
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156cb800aa
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[core] fixed a critical bug which causes wrong connections in tile modules
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2023-07-27 12:22:16 -07:00 |
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tangxifan
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dd486f5ccb
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[core] fixed a bug on checking if cb is in a tile
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2023-07-27 11:14:05 -07:00 |
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tangxifan
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cfec6c88f1
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[core] fixed a bug in cb instance naming
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2023-07-27 10:59:46 -07:00 |
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tangxifan
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be0715a81c
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[core] fixed a bug on cb instance name. Spot some bug in port naming for tile modules
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2023-07-27 10:42:56 -07:00 |
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tangxifan
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97219fd825
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[core] add more verbose to help debug failed test cases
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2023-07-26 23:26:11 -07:00 |
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tangxifan
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f5e8f175fb
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[core] fixed a bug which causes flow failures when group_tile is not enabled
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2023-07-25 21:27:58 -07:00 |
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tangxifan
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83428a209e
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[core] fixed a bug on io indexing which causes tile-based test cases failed in dv
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2023-07-25 16:03:50 -07:00 |
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tangxifan
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de6956530f
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[core] disable pnr sdc for tile-based fabric
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2023-07-25 15:38:41 -07:00 |
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tangxifan
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6ecbbb3a94
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[core] fixed a bug in fabric bitgen due to tile modules
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2023-07-25 14:49:12 -07:00 |
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tangxifan
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95a32628ab
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[core] fixed the bug in arch bitgen due to the tile modules
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2023-07-25 14:15:15 -07:00 |
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tangxifan
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64698443c9
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[core] fixed a bug on io location map for tile modules
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2023-07-24 22:11:57 -07:00 |
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tangxifan
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2105abdbca
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[core] fixed a bug
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2023-07-24 21:26:29 -07:00 |
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tangxifan
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e7d714b94d
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[core] fixed a bug on the tile module port addition: some grid output was not pulled out
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2023-07-24 21:21:25 -07:00 |
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tangxifan
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b8d080b08e
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[core] fixed a bug where undriven cb ports are not connected to tile
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2023-07-24 20:40:25 -07:00 |
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tangxifan
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3745897ff6
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[core] fixed a few bugs
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2023-07-24 16:10:29 -07:00 |
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tangxifan
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48b0ba8b78
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[core] format
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2023-07-24 15:00:26 -07:00 |
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tangxifan
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4294914987
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[core] fixed compiler warnings
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2023-07-24 14:59:43 -07:00 |
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tangxifan
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812473ef04
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[core] fixed the bug on io location map for tiled top module
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2023-07-24 14:50:39 -07:00 |
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tangxifan
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da36b735c6
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[core] syntax
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2023-07-24 12:13:45 -07:00 |
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tangxifan
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f031148959
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[core] syntax
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2023-07-23 22:39:36 -07:00 |
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tangxifan
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f551188d0f
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[core] developed tile directs to support tile modules
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2023-07-23 21:45:45 -07:00 |
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tangxifan
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14666f3ae5
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[core] sync
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2023-07-23 20:45:59 -07:00 |
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tangxifan
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0b3b7b5472
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[core] hotfix
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2023-07-23 13:39:06 -07:00 |
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tangxifan
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1ee7448070
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[core] supporting tile annotation (for global port) in tile modules
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2023-07-23 13:38:16 -07:00 |
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tangxifan
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399259ea1d
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[core] adding prog clock arch support for tile modules
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2023-07-23 13:11:13 -07:00 |
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tangxifan
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0f3f4b0d81
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[core] now tile module use unique port name (for heterogeneous blocks)
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2023-07-22 23:55:54 -07:00 |
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tangxifan
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003d9515ff
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[core] developing tile-based top module builder
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2023-07-22 17:13:30 -07:00 |
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tangxifan
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93c5a68592
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[core] developing top-level nets for tiles
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2023-07-21 23:21:53 -07:00 |
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tangxifan
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fcf308fcd6
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[core] developing inter-tile connections for top module
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2023-07-20 23:00:35 -07:00 |
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tangxifan
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b70f7fb1b6
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[core] now option conflicts in command 'build_fabric' can error out
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2023-07-20 21:22:07 -07:00 |
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tangxifan
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6b92299e39
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[core] start working on the net build-up for tile instances under the top-level module
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2023-07-20 17:38:13 -07:00 |
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tangxifan
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88c5d122ca
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[core] syntax
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2023-07-20 17:12:10 -07:00 |
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tangxifan
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db179ec4bb
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[core] split tile instance builder and the classic fine-grained builder
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2023-07-20 17:07:07 -07:00 |
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tangxifan
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ef214f4590
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[core] code format
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2023-07-20 17:00:29 -07:00 |
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tangxifan
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6458580e3e
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[core] move child instance builder to a separated source file as these codes are expanding in size
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2023-07-20 16:59:39 -07:00 |
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tangxifan
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bd265334b5
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[core] added tile instances to top module builder
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2023-07-19 23:26:55 -07:00 |
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tangxifan
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a06b9a0f48
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[core] now start to develop the tile instances under the top module
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2023-07-19 22:22:07 -07:00 |
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tangxifan
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2e69eebea0
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[core] now tile module builder is working
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2023-07-19 17:23:44 -07:00 |
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tangxifan
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0d03d7b483
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[core] now fabric tile cache both grid and gsb coord for pb
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2023-07-19 17:20:53 -07:00 |
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tangxifan
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778d03610c
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[core] debugging
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2023-07-19 15:27:05 -07:00 |
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tangxifan
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001b3b3f8b
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[core] debugging
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2023-07-19 14:38:07 -07:00 |
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tangxifan
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d03fa92ddf
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[core] debugging
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2023-07-19 12:49:35 -07:00 |
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tangxifan
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48e207d3e4
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[core] debugging
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2023-07-19 12:22:57 -07:00 |
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tangxifan
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6607bb7e48
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[core] now fpga verilog supports tile modules
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2023-07-18 22:35:22 -07:00 |
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tangxifan
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5ae146bd86
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[core] finish up tile module builder
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2023-07-18 21:17:40 -07:00 |
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tangxifan
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0dcec9d8e5
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[core] finishing up tile module builder
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2023-07-18 17:56:27 -07:00 |
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tangxifan
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403ed4ea60
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[core] still developing tile module port and net builder
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2023-07-18 16:03:47 -07:00 |
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tangxifan
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aabcc25567
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[core] developing tile module port and net builder
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2023-07-17 23:06:55 -07:00 |
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tangxifan
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ba4b7e3522
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[core] developing tile module builder
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2023-07-16 15:18:09 -07:00 |