tangxifan
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253d5fa26c
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[core] a new test to validate the L shape in homo geneous fpga
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2023-08-11 13:05:46 -07:00 |
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tangxifan
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0e9cf6e909
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[test] added a new testcase to validate heterogeneous fpga using group config block
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2023-08-06 22:11:38 -07:00 |
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tangxifan
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3e33f262bc
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[test] added a new test to validate group_config_block support when fpga_core wrapper is enabled
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2023-08-06 18:59:24 -07:00 |
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tangxifan
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b7048d3dc8
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[test] adding new tests to validate group config block
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2023-08-03 22:30:41 -07:00 |
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tangxifan
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65995d7c13
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[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
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2023-07-27 17:03:02 -07:00 |
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tangxifan
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46e58a56cb
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[test] added a new test case to validate clock network when using the tile modules
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2023-07-27 16:39:48 -07:00 |
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tangxifan
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81d699a723
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[test] added a new testcase to validate carry chain connections in tile modules
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2023-07-27 16:18:30 -07:00 |
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tangxifan
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e9f2adf3f9
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[test] add a new testcase to validate carry chain connections when using tile modules
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2023-07-27 16:06:43 -07:00 |
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tangxifan
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1ea8a33d4b
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[test] add a new testcase to validate global tile connections on tile modules
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2023-07-27 15:57:38 -07:00 |
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tangxifan
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5685fbd5e8
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[test] adding a new test case to validate the tile modules on 4x4 fabric
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2023-07-26 22:17:39 -07:00 |
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tangxifan
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0db4ef62e8
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[test] add a new test for tile-based fabric: using preconfig testbenches
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2023-07-25 15:48:14 -07:00 |
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tangxifan
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523cf83cc9
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[test] disable pnr writer in test cases
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2023-07-25 15:39:25 -07:00 |
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tangxifan
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82fe63297a
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[test] add a new test for top-left tile grouping
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2023-07-19 11:22:36 -07:00 |
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tangxifan
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270d6f933b
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[test] add a new testcase to validate mock wrapper
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2023-06-26 15:26:50 -07:00 |
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tangxifan
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919d6d8608
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[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches
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2023-06-25 22:49:51 -07:00 |
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tangxifan
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962ba67e36
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[test] adding new tests to validate fpga core wrapper naming rules
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2023-06-23 14:47:21 -07:00 |
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tangxifan
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fd8f371d85
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[test] add missing file
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2023-06-19 16:44:11 -07:00 |
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tangxifan
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efc9bf9907
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[test] added new test case to validate bitstream generation
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2023-06-19 12:40:37 -07:00 |
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tangxifan
|
97b089ae3c
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[test] added new testcases to validate fpga core wrapper
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2023-06-18 21:01:37 -07:00 |
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tangxifan
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ac31a20376
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[test] now bypass clock routing in default example
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2023-06-08 13:44:22 -07:00 |
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tangxifan
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27b8007d1b
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[test] rework pcf support testcase for mock wrapper
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2023-05-27 12:45:29 -07:00 |
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tangxifan
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b6c90eb99a
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[core] fixed several bugs which causes bgf and pcf support in mock wrapper failed
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2023-05-27 12:13:16 -07:00 |
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tangxifan
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e1feebc96d
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[core] fixing bugs on pcf and bgf support for mock efpga wrapper
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2023-05-26 21:54:08 -07:00 |
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tangxifan
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77be053966
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[test] mock wrapper does not need bitstream forcing
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2023-05-26 18:50:54 -07:00 |
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tangxifan
|
7fbe567d4c
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[test] add more testcases
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2023-05-25 20:24:02 -07:00 |
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tangxifan
|
7da7d03db5
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[script] add example script for mock wrapper
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2023-05-25 19:59:14 -07:00 |
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tangxifan
|
40598d25a3
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[core] fixed a bug which causes multi-clock programmable network failed in routing
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2023-04-20 15:05:45 +08:00 |
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tangxifan
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fba0a83679
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[test] debugging 2-clock network
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2023-04-20 14:44:01 +08:00 |
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tangxifan
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03cb664049
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[test] now clock network example script supports multiple clocks
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2023-04-20 10:56:36 +08:00 |
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tangxifan
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7d333b3669
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[test] add a new test for clock network: validate full testbench is working
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2023-04-20 10:36:08 +08:00 |
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tangxifan
|
780dec6b1b
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[test] add a new test to validate the programmable clock arch
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2023-02-28 21:46:57 -08:00 |
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tangxifan
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e974e5ddf7
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[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
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2023-01-18 18:31:36 -08:00 |
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tangxifan
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758cc7a089
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[test] debugging
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2023-01-15 11:44:48 -08:00 |
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tangxifan
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f6f153ace4
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[test] debugging
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2023-01-11 17:06:31 -08:00 |
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tangxifan
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d5ebbeea9a
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[test] adding a new test to show how to automate generation of bus group files
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2023-01-11 16:59:54 -08:00 |
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tangxifan
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54c3b965f2
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[script] fixed a bug
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2023-01-01 17:19:11 -08:00 |
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tangxifan
|
3c8e157d7b
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[script] rename and fix typo
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2023-01-01 17:13:23 -08:00 |
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tangxifan
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83d7ff56e1
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[script] add dedicated testcase for source commands
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2023-01-01 17:04:24 -08:00 |
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tangxifan
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cdec0cf28c
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[script] add a custom variable to specify the path to openfpga shell script
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2023-01-01 16:51:21 -08:00 |
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tangxifan
|
c50daf273c
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[script] add example script for using source command
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2023-01-01 16:50:10 -08:00 |
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tangxifan
|
d7a95a8ec2
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[script] fixed some bugs
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2022-12-30 18:30:52 -08:00 |
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tangxifan
|
6973e9fb98
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[script] add an example script for vpr standalone calls
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2022-12-30 18:23:14 -08:00 |
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tangxifan
|
609e096b1a
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[test] added a new test to validate explicit port direction in pin table support
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2022-10-17 15:25:19 -07:00 |
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tangxifan
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7f67794787
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[arch]add new arch to test
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2022-10-13 10:54:40 -07:00 |
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tangxifan
|
088ff1a474
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[script] fixed a bug
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2022-09-29 16:27:03 -07:00 |
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tangxifan
|
a3e7133d63
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Merge branch 'master' into wire_lut_test
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2022-09-29 16:02:18 -07:00 |
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tangxifan
|
ce0fbe1765
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[test] fixed a few bugs
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2022-09-29 15:32:31 -07:00 |
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tangxifan
|
3f8e2ade2e
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[script] update missing scripts required by pb_pin_fixup test cases
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2022-09-29 13:39:46 -07:00 |
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tangxifan
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49fa783914
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[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
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2022-09-29 10:45:27 -07:00 |
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tangxifan
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eaa0b5588a
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[test] fixed a bug in pin constrain examples
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2022-09-21 14:10:12 -07:00 |