tangxifan
|
60e8d2b29f
|
add missing files and try to refactor submodule essential
|
2019-08-20 16:13:08 -06:00 |
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tangxifan
|
29104b6fa5
|
rework on the circuit model ports and start prototyping mux Verilog generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
69039aa742
|
developed subgraph extraction and start refactoring mux generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
890ff05628
|
bug fixing and get ready for testing
|
2019-08-06 14:17:56 -06:00 |
|
tangxifan
|
003883b13b
|
implementing the local encoders
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2019-08-06 14:17:55 -06:00 |
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tangxifan
|
fb2ca66ce9
|
start adding submodules of local encoders to multiplexer
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2019-08-06 14:17:55 -06:00 |
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tangxifan
|
8b8e18a8de
|
bug fixing for mux subckt names
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2019-07-17 08:59:57 -06:00 |
|
tangxifan
|
dcc96bf7f5
|
bug fixing
|
2019-07-17 08:25:52 -06:00 |
|
tangxifan
|
6e1d49d74e
|
start to support direct mapping to MUX2 standard cells
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2019-07-17 07:54:23 -06:00 |
Baudouin Chauviere
|
69014704ef
|
Explicit verilog final push
|
2019-07-16 13:13:30 -06:00 |
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Baudouin Chauviere
|
40d3460bac
|
Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-11 22:13:30 -06:00 |
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Baudouin Chauviere
|
d0cd5a2bc1
|
Hot fix
|
2019-07-11 17:27:31 -06:00 |
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Baudouin Chauviere
|
f4be375637
|
Latest version explicit
|
2019-07-11 14:33:56 -06:00 |
|
Baudouin Chauviere
|
25f5bc7792
|
Latest version, not stable yet but close
|
2019-07-09 08:34:01 -06:00 |
|
Baudouin Chauviere
|
ae05c553d5
|
Top module done
|
2019-07-08 09:48:33 -06:00 |
|
Baudouin Chauviere
|
b08513d902
|
Big chunk added on the routing part of the explicit mapping
|
2019-07-02 14:12:42 -06:00 |
|
Baudouin Chauviere
|
8f5ad2eb67
|
Snapshot of progress
|
2019-07-02 10:10:48 -06:00 |
|
Baudouin Chauviere
|
863e8677c0
|
Further add new functions to tree
|
2019-07-01 12:12:36 -06:00 |
|
Baudouin Chauviere
|
0e04b88c8f
|
Include new files in the parameter spreading
|
2019-07-01 11:27:48 -06:00 |
|
Baudouin Chauviere
|
7c742f1cbb
|
Stable, is_explicit propagated through the code. Not implemented though except for muxes
|
2019-06-27 10:29:57 -06:00 |
|
Baudouin Chauviere
|
0ce9846e47
|
Stable, unfinished
|
2019-06-26 16:54:41 -06:00 |
|
Baudouin Chauviere
|
87ddca9f57
|
commiting current work. Stable but function not implemented yet
|
2019-06-26 14:22:02 -06:00 |
|
tangxifan
|
43128ad3f0
|
fix a bug in formal verification port for memory bank configuration circuits
|
2019-06-13 15:33:13 -06:00 |
|
tangxifan
|
1776ae3ec8
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
tangxifan
|
f43955037c
|
remove input port requirements for SRAM circuit module
|
2019-06-10 15:29:44 -06:00 |
|
tangxifan
|
17bc7fc296
|
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
|
2019-06-08 20:11:22 -06:00 |
|
tangxifan
|
c2d8fa00ba
|
add rr_block unique_side_module verilog generation
|
2019-06-04 17:47:40 -06:00 |
|
tangxifan
|
ea8c36ce6e
|
upgrade Verilog SB generator using the RRSwitchBlock
|
2019-05-23 17:37:39 -06:00 |
|
tangxifan
|
b185a17359
|
add routing_channel unique module generation
|
2019-05-20 22:33:17 -06:00 |
|
Baudouin Chauviere
|
2019840d7c
|
cleaned unused variables
|
2019-05-13 14:45:02 -06:00 |
AurelienUoU
|
42f20eda60
|
Add the user matching for internal register in formal verification script generation
|
2019-05-03 10:24:02 -06:00 |
|
tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |