52ae484a7c
[core] fixed a bug on messed up wire connections for OPINs
2024-05-20 13:50:31 -07:00
ca6e2f9831
[core] code format
2024-05-20 13:41:35 -07:00
4a791249bf
[core] fixed a bug on requirement wire model for direction connection which is part of a cb
2024-05-20 12:52:07 -07:00
b554a3d855
[core] code format
2024-05-19 17:24:38 -07:00
56aaa6a1f4
[core] sytax
2024-05-19 17:23:48 -07:00
065d77c679
[core] supporting opin connection to cb in tiles
2024-05-19 17:04:24 -07:00
9079056871
[core] now connect OPIN to CB in top-level module
2024-05-19 14:27:36 -07:00
918bf79ca3
[core] update vtr and developing caches for OPIN lists just for connection blocks
2024-05-19 14:10:00 -07:00
772da3006b
[core] code format
2024-05-18 22:19:17 -07:00
304f34525e
[core] syntax
2024-05-18 22:17:52 -07:00
b533ea4060
[core] now cb module include OPIN nodes
2024-05-18 22:00:02 -07:00
926b9e9739
[core] code format
2024-05-18 12:33:19 -07:00
3b93bea3d1
[core] syntax
2024-05-18 12:29:38 -07:00
0d8c21ca84
[core] add new type 'part_of_cb' for tile direct connections
2024-05-17 18:59:53 -07:00
7848bdaeac
[core] code format
2024-05-09 22:50:49 -07:00
5f37d63061
[core] fixed a bug where incoming edges are not built after loading rr_graph in vpr
2024-05-09 19:38:26 -07:00
7dc2c4951c
[core] add missing header required by clang-11+
2024-05-05 21:56:56 -07:00
3d8107487c
[core] code format
2024-05-03 10:21:39 -07:00
c7501cb9b7
[core] fixed the bugs when there are module renaming
2024-05-03 10:20:19 -07:00
f41a5e8b89
[core] fixed some bugs
2024-05-02 22:49:06 -07:00
c557b0104a
[core] avoid unwanted tab
2024-05-02 21:34:12 -07:00
b85ec28eb8
[core] code format
2024-05-02 21:17:17 -07:00
d3b1e562ad
[core] fixed some bugs on format
2024-05-02 21:11:20 -07:00
bf24382f19
[core] code format
2024-05-02 18:33:07 -07:00
a2fb84dfa9
[core] add fabric hierarchy writer
2024-05-02 18:30:20 -07:00
4d3447f773
[core] rework fabric hierarchy writer
2024-05-02 18:05:38 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
08bd6d00d3
[core] code format
2024-04-11 15:04:08 -07:00
79970719b4
[core] fixed a bug where regex breaks
2024-04-11 14:59:14 -07:00
f63ea06c4e
[core] now support regular expression in module name for fabric pin physical location output
2024-04-11 14:30:27 -07:00
5960cc14aa
[core] fixed a bug
2024-04-11 13:04:47 -07:00
6f94399767
[core] code format
2024-04-10 22:53:52 -07:00
971f0e8838
[core] add a new option '--show_invalid_side'
2024-04-10 22:52:36 -07:00
58708ff727
[core] syntax
2024-04-10 20:08:02 -07:00
435e83c530
[core] add port side to tile ports
2024-04-10 17:38:02 -07:00
f9f7d42d93
[core] add port side attribute and set them when buidling grid/cb/sb modules
2024-04-10 17:10:06 -07:00
d156de060e
[core] adding pin side attribute to module manager
2024-04-10 16:19:28 -07:00
b0be9fe75d
[core] developing xml writer for fabric pin phy loc
2024-04-10 15:51:26 -07:00
47baaff94c
[core] rename command name to 'write_fabric_pin_physical_location`` and start developing exec func
2024-04-10 13:30:02 -07:00
f1334645db
[core] added a new command write_pin_physical_location
2024-04-10 13:07:49 -07:00
0a7915aa77
[core] typo
2024-03-29 12:03:23 -07:00
6a5d3c7cdc
[code] syntax
2024-03-29 11:03:48 -07:00
00de794967
[core] code format
2024-03-29 10:58:48 -07:00
981828c39c
[core] add a new opton ``--dump_waveform`` to command ``write_preconfigured_fabric_wrapper``
2024-03-29 10:57:45 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
59deb97d5d
[core] code format
2024-01-12 14:17:10 -08:00
f1e3d53da6
[core] fixed a bug where pb pin fixup may fail when subtile capacities are not same
2024-01-12 14:16:07 -08:00
bacd845139
[core] code format
2023-12-08 13:41:41 -08:00
5e181cbe72
[core] add a new option for simulator type to verilog full testbench generator
2023-12-08 13:07:25 -08:00
0e945d6e71
[core] fix a bug in ql memory bank tb where VCS failed
2023-12-08 11:36:54 -08:00
tangxifan
chungshien