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3637 Commits

Author SHA1 Message Date
bbleaptrot f963be4cae
Add files via upload 2021-03-30 21:56:43 -06:00
bbleaptrot b8b024048e
Add first draft for Open Cell Libraries tutorial 2021-03-30 21:54:46 -06:00
tangxifan c393ee6959
Merge pull request #271 from lnis-uofu/doc_patch 
Patch the schematic of LUT circuit models to be consistent with netlists
 2021-03-23 22:02:20 -06:00
tangxifan eec52360ee
Merge branch 'master' into doc_patch 2021-03-23 21:33:05 -06:00
tangxifan 68a5c1c8fe
Merge pull request #274 from lnis-uofu/tutorials 
Tutorials
 2021-03-23 21:32:53 -06:00
tangxifan 79ee614160
Merge branch 'master' into tutorials 2021-03-23 21:04:45 -06:00
bbleaptrot 8ee86d78dd
Implement some of the final changes 2021-03-23 20:50:54 -06:00
tangxifan 8989317249
Merge branch 'master' into doc_patch 2021-03-23 19:50:01 -06:00
ganeshgore 3ea62bb4b3
Merge pull request #277 from lnis-uofu/hetergeneous_arch 
Support Verilog-to-Verification for heterogeneous FPGA
 2021-03-23 19:48:35 -06:00
bbleaptrot 16cefdba28
Fix minor changes in page 2021-03-23 18:19:14 -06:00
bbleaptrot 3dea033981
Implement more code blocks for cleaner page 2021-03-23 18:12:27 -06:00
bbleaptrot ccfcae88d7
Update to remove clunky image with code-block 2021-03-23 17:41:55 -06:00
bbleaptrot 191ce358c7
Indent code-blocks 2021-03-23 17:29:34 -06:00
bbleaptrot 34a1df858b
Fix code-block syntax for XML 2021-03-23 17:25:32 -06:00
bbleaptrot 59ecaae23b
Update to use code-block syntax 2021-03-23 17:21:44 -06:00
bbleaptrot 07f05cc942
Update user_defined_temp_tutorial.rst 
Update to remove two images that were hard to read on the webpage and replace with code blocks
 2021-03-23 17:16:27 -06:00
tangxifan 44d97ead86
Merge branch 'master' into hetergeneous_arch 2021-03-23 17:05:03 -06:00
ganeshgore 93abfff2bb
Merge pull request #275 from lnis-uofu/yosys_heterogeneous_block_support 
Yosys heterogeneous block support on DSP block
 2021-03-23 17:04:46 -06:00
bbleaptrot 4317f7add7
Update file to display images w/caps 2021-03-23 16:50:52 -06:00
bbleaptrot b194e9c395
Update index.rst 
Include link to user_defined_temp_tutorial file
 2021-03-23 16:37:44 -06:00
bbleaptrot 4d0e06c332
Update user_defined_temp_tutorial 
Add more sections, robust instructions, and a link to documentation
 2021-03-23 16:34:32 -06:00
tangxifan b00b4f0f5f [HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian 2021-03-23 15:44:53 -06:00
tangxifan d82ffe0cbf [Test] Deploy MAC_8 benchmark to regression test 2021-03-23 15:36:28 -06:00
tangxifan 108c84a022 [HDL] Add HDL for 8-bit single-mode multiplier 2021-03-23 15:36:09 -06:00
tangxifan 145a80de43 [Script] Add an openfpga shell script for heterogeneous fpga verification 2021-03-23 15:35:34 -06:00
tangxifan fdec72b5bc [Arch] Add an example architecture with 8-bit single-mode multiplier 2021-03-23 15:35:06 -06:00
tangxifan be03eafd66 [Benchmark] Add a micro benchmark: 8-bit multiply and accumulate 2021-03-23 15:33:37 -06:00
tangxifan 8c970a792a [Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier 2021-03-23 15:33:00 -06:00
tangxifan 6b0409da60 [Script] Add a template yosys script support only DSP mapping 2021-03-23 15:32:10 -06:00
tangxifan a4bbffd1aa [HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA 2021-03-23 15:30:41 -06:00
tangxifan fff16a01ab [Test] Update tolerance when checking VTR benchmark QoR 2021-03-23 12:27:20 -06:00
tangxifan 781880ed93 [Script] Add tolerance options to check qor script 2021-03-23 12:26:33 -06:00
tangxifan e3f8a6cf7a [Test] Deploy QoR check to VTR benchmark regression test 2021-03-23 11:15:22 -06:00
tangxifan 351dec5935 [Test] Add QoR csv file for vtr benchmarks 2021-03-23 11:15:02 -06:00
tangxifan 23e7f7f1f5 [Script] Update default list of result extraction for openfpga flow 2021-03-23 11:06:42 -06:00
tangxifan adfbd28a7a [Script] Add a simple QoR checker 2021-03-23 11:06:16 -06:00
tangxifan 61eddb08de [Test] Update task configuration by commenting out high-runtime VTR benchmarks 2021-03-22 14:42:42 -06:00
tangxifan 55d1004cf2 [Benchmark] Add missing DPRAM module to LU32PEEng 2021-03-22 14:41:38 -06:00
tangxifan 5fc83ebea3 [Benchmark] Add missing DPRAM modules to LU8PEEng 2021-03-22 14:38:00 -06:00
tangxifan b828f91a78 [Benchmark] Add missing DPRAM and SPRAM modules to mcml 2021-03-22 14:13:05 -06:00
tangxifan d050f1b746 [Script] Enable fast bitstream generation for VTR benchmarks 2021-03-22 12:54:36 -06:00
tangxifan 4bfd0c0a02 [Test] Enable more VTR benchmark in testing 2021-03-22 12:53:30 -06:00
tangxifan b906ab814e [Benchmark] Add missing DPRAM module to mkPktMerge 2021-03-22 12:51:23 -06:00
tangxifan 310c2a9495 [Benchmark] Add missing DPRAM module to mkDelayWorker32B 2021-03-22 12:51:02 -06:00
tangxifan 707247283c [Benchmark] Add missing DPRAM module to mkSMAdapter4B 2021-03-22 12:50:39 -06:00
tangxifan eb056e2afd [Benchmark] Add missing DPRAM module to or1200 2021-03-22 12:50:17 -06:00
tangxifan 7fd345a616 [Script] Solved the problem on BRAM mapping in the yosys script supporting both DSP and BRAMs 2021-03-22 10:39:47 -06:00
tangxifan cc10b10703 [Test] Enable more benchmarks for testing; See problems when mapping BRAMs 2021-03-20 22:53:37 -06:00
tangxifan 169ee53b79 [Benchmark] Add missing modules to VTR benchmarks 2021-03-20 22:53:17 -06:00
tangxifan eca2a35612 [Script] Add route chan width option to vtr openfpga script 2021-03-20 22:00:09 -06:00