tangxifan
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56948244bc
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[Tool] Patch a critical bug in pb pin fixup
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2021-04-22 16:19:54 -06:00 |
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tangxifan
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1dcb8e39a9
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[Test] Unlock more IWLS'2005 benchmarks in testing
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2021-04-22 09:23:33 -06:00 |
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tangxifan
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61a473e479
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[Test] Unlock more IWLS'2005 benchmarks under testing thanks to flexible FF mapping support
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2021-04-21 22:56:19 -06:00 |
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tangxifan
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5a519390ff
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[HDL] Enriched DFF model in yosys technology library
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2021-04-21 22:49:05 -06:00 |
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tangxifan
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ce6018e123
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[Arch] Enriched DFF model to support active-low/high FFs
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2021-04-21 22:48:31 -06:00 |
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tangxifan
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adfea88be2
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[HDL] Rename multi-mode DFF module
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2021-04-21 20:06:03 -06:00 |
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tangxifan
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62497549b6
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[HDL] Add multi-mode DFF module
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2021-04-21 20:04:40 -06:00 |
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tangxifan
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3a5c26c6a1
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[Test] Update IWLS test by using new architecture and customize DFF techmap
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2021-04-21 19:51:25 -06:00 |
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tangxifan
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8cbea6a268
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[HDL] Add technology library for customizable DFF synthesis
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2021-04-21 19:50:51 -06:00 |
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tangxifan
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3d615e1516
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[Script] Add yosys script supporting customize DFF/BRAM/DSP mapping
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2021-04-21 19:50:07 -06:00 |
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tangxifan
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9d9840d9b7
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[Arch] Add architecture using multi-mode DFFs
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2021-04-21 19:49:48 -06:00 |
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tangxifan
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c198273378
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Merge pull request #295 from lnis-uofu/multi_clock
Patches on multi-clock support in repacking stage
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2021-04-21 15:22:53 -06:00 |
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tangxifan
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2e1cc5499d
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[Doc] Add disclaimer for limitations when using repack pin constraints
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2021-04-21 14:14:54 -06:00 |
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tangxifan
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8046b16c15
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[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
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2021-04-21 14:04:34 -06:00 |
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tangxifan
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b203ef7bc2
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[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
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2021-04-21 14:03:51 -06:00 |
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tangxifan
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96ce6b545f
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[Tool] Patch repack to consider design constraints for pins that are not equivalent
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2021-04-21 13:53:08 -06:00 |
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tangxifan
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12f27cf117
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Merge pull request #294 from lnis-uofu/mux_default_path
Support customizable default path in bitstream generation for any interconnect inside pb_type
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2021-04-19 18:29:03 -06:00 |
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tangxifan
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2fa370d7d5
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[Test] Patch regression tests for fpga bitstream
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2021-04-19 17:15:14 -06:00 |
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tangxifan
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9b3dcc65bd
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[Doc] Add new bitstream setting syntex 'interconnect' to documentation
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2021-04-19 16:37:21 -06:00 |
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tangxifan
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17fb532ffa
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Merge branch 'master' into mux_default_path
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2021-04-19 16:23:44 -06:00 |
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tangxifan
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64163edbe6
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[Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting
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2021-04-19 16:15:25 -06:00 |
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tangxifan
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578d81b67a
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[Test] Patch task configuration file
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2021-04-19 16:15:00 -06:00 |
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tangxifan
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f7767ff4df
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Merge pull request #284 from lnis-uofu/tutorials
Tutorials
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2021-04-19 16:00:16 -06:00 |
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tangxifan
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18eb5c9de9
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[Test] Deploy new test to CI
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2021-04-19 15:56:41 -06:00 |
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tangxifan
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5976cc0a1c
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[Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection
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2021-04-19 15:54:18 -06:00 |
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tangxifan
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0aec30bac6
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[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
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2021-04-19 15:53:33 -06:00 |
bbleaptrot
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986ea492f6
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Fix grammar line 38: lookup table ->Look-Up Table
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2021-04-19 14:16:40 -06:00 |
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tangxifan
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5364b94cf8
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[Tool] Update bitstream setting parser/writer to support interconnect-related syntax
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2021-04-19 13:42:12 -06:00 |
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tangxifan
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2ff3dc0a0f
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Merge branch 'master' into tutorials
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2021-04-19 11:35:18 -06:00 |
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bbleaptrot
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bc6e9746c2
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Fix more grammar mistakes
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2021-04-19 09:48:42 -06:00 |
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bbleaptrot
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8431337f39
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Fix grammar errors in fig captions and elsewhere
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2021-04-19 09:36:13 -06:00 |
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bbleaptrot
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86c856d35a
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Fix reference links
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2021-04-19 09:25:54 -06:00 |
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bbleaptrot
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cd6beb5789
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Add one more link to fabric_netlists
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2021-04-19 09:14:47 -06:00 |
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bbleaptrot
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f8810940c3
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Update links
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2021-04-19 09:10:17 -06:00 |
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bbleaptrot
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fcb7ee3283
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Update to properly reference fabric netlist page
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2021-04-19 09:05:30 -06:00 |
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bbleaptrot
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5010fb1e7f
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Update hyperlinks
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2021-04-19 08:52:05 -06:00 |
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bbleaptrot
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291638ee0f
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Trying to resolve hyperlink to right location
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2021-04-19 08:45:02 -06:00 |
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bbleaptrot
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beed1ce31e
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replace hyperlink with more stable :ref: link
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2021-04-19 08:38:09 -06:00 |
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tangxifan
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e85402eaaa
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Merge pull request #293 from lnis-uofu/dff_techmap
Enable correct reset stimuli in testbench generators
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2021-04-18 17:15:28 -06:00 |
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tangxifan
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0b49c22682
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[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
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2021-04-18 16:11:11 -06:00 |
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tangxifan
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82dd09a180
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Merge branch 'master' into dff_techmap
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2021-04-18 12:09:52 -06:00 |
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tangxifan
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6550ea3dfa
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[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
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2021-04-18 12:02:49 -06:00 |
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tangxifan
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0e65442afd
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Merge pull request #292 from lnis-uofu/dff_techmap
Verilog testbench generator now accepts pin constraints on non-clock global ports
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2021-04-17 23:02:35 -06:00 |
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tangxifan
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6e9b24f9bf
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[Tool] Patch the invalid pin constraint net name
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2021-04-17 19:56:30 -06:00 |
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tangxifan
|
253422e7b7
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[Tool] Bugfix due to refactoring
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2021-04-17 19:27:03 -06:00 |
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tangxifan
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02ca51d84b
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[Tool] Reorganize functions in full testbench generator to avoid big-chunk codes
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2021-04-17 17:45:50 -06:00 |
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tangxifan
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d95a1e2776
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[Tool] Encapulate search function in PinConstraint data structure
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2021-04-17 17:31:55 -06:00 |
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tangxifan
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da619fabe7
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[Tool] FPGA-Verilog testbench generator accepts pin constraints in full testbench
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2021-04-17 17:19:34 -06:00 |
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tangxifan
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03a709dce9
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Merge branch 'master' into dff_techmap
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2021-04-17 16:20:55 -06:00 |
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tangxifan
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6e1b58f8a6
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[Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports
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2021-04-17 15:05:22 -06:00 |