tangxifan
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9074bffa68
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[Tool] Support customized default value in pin constraint file
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2021-07-01 23:43:19 -06:00 |
Ganesh Gore
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1de1f2f2e2
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[FLOW] Variable in capital case
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2021-07-01 22:26:00 -06:00 |
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Ganesh Gore
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81f9dff9ff
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[Flow] Allows benchmark specific var declaraton
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2021-07-01 22:19:53 -06:00 |
ganeshgore
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4818e08448
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Merge pull request #327 from lnis-uofu/verilog_testbench
added configuration benchmark files
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2021-07-01 20:38:16 -07:00 |
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tangxifan
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b7356d23aa
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Merge branch 'master' into verilog_testbench
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2021-07-01 21:11:12 -06:00 |
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tangxifan
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947f078a7e
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Merge pull request #353 from lnis-uofu/testbench_patch
Bug fix on the reset stimuli generator
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2021-07-01 21:10:40 -06:00 |
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tangxifan
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d0e4f8521f
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[Tool] Bug fix on the reset stimuli
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2021-07-01 19:58:54 -06:00 |
ANDREW HARRIS POND
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1d281765ea
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fixed tab spacing
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2021-07-01 16:42:04 -06:00 |
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ANDREW HARRIS POND
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808821bb8c
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fixed errors
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2021-07-01 16:40:03 -06:00 |
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ANDREW HARRIS POND
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006b54c4bc
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ready for merge
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2021-07-01 15:35:39 -06:00 |
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ANDREW HARRIS POND
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8513b8a4ff
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Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
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2021-07-01 15:29:39 -06:00 |
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ANDREW HARRIS POND
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2567fbee05
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ready to merge
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2021-07-01 15:28:59 -06:00 |
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tangxifan
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04ceeefb0a
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Merge branch 'master' into verilog_testbench
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2021-07-01 14:43:26 -06:00 |
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ANDREW HARRIS POND
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db9231c225
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tests failing with initial blocks
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2021-07-01 13:52:28 -06:00 |
komaljaved-rs
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be14e4f448
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added design_variables.yml
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2021-07-01 16:31:42 +05:00 |
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komaljaved-rs
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01f79d89b8
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Merge branch 'master' of github.com:RapidSilicon/OpenFPGA_RS
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2021-07-01 16:24:12 +05:00 |
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komaljaved-rs
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ff785569f0
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updated ci_test
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2021-07-01 16:23:55 +05:00 |
komaljaved-rs
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061811994d
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Update ci_test.yml
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2021-07-01 16:05:08 +05:00 |
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komaljaved-rs
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6d11dc275d
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Update ci_test.yml
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2021-07-01 16:01:38 +05:00 |
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komaljaved-rs
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4b8e178947
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Update ci_test.yml
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2021-07-01 15:44:59 +05:00 |
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komaljaved-rs
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2469f25ef4
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updated submodule
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2021-07-01 15:14:59 +05:00 |
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komaljaved-rs
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7a703659e7
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Merge branch 'master' of github.com:RapidSilicon/OpenFPGA_RS
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2021-07-01 15:08:26 +05:00 |
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komaljaved-rs
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6559f71082
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added ci_scripts
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2021-07-01 15:07:37 +05:00 |
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komaljaved-rs
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1e81dd897f
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Update ci_test.yml
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2021-07-01 14:47:59 +05:00 |
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komaljaved-rs
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cbb4b32f7f
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Rename openfpga.yml to ci_test.yml
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2021-07-01 14:45:38 +05:00 |
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komaljaved-rs
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4b6b0273ba
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Create openfpga.yml
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2021-07-01 14:44:48 +05:00 |
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tangxifan
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a2cb153d54
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Merge pull request #349 from lnis-uofu/testbench_flag
More micro benchmarks on adder
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2021-06-30 16:39:21 -06:00 |
Andrew Pond
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fab2b069f0
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added signal gen regression test to shell script
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2021-06-30 16:18:09 -06:00 |
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tangxifan
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602172bb27
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Merge branch 'testbench_flag' of https://github.com/LNIS-Projects/OpenFPGA into testbench_flag
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2021-06-30 15:29:53 -06:00 |
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tangxifan
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a898537474
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[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``
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2021-06-30 15:29:13 -06:00 |
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tangxifan
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9786b52c73
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Merge branch 'master' into testbench_flag
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2021-06-30 15:18:53 -06:00 |
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tangxifan
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83d177b13b
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[Test] Deploy the newly added adder benchmarks to tests
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2021-06-30 15:14:24 -06:00 |
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tangxifan
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4d4577bb83
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[Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders
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2021-06-30 15:13:47 -06:00 |
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komaljaved-rs
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a08de86000
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Update build.yml
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2021-06-30 14:58:13 +05:00 |
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tangxifan
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322238f431
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Merge pull request #348 from lnis-uofu/testbench_flag
Deprecate pre-processing flags ``define_simulation.v`` and enable testbench generation without self checking
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2021-06-29 21:02:05 -06:00 |
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tangxifan
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9eeec05a1f
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[Test] Bug fix
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2021-06-29 19:55:07 -06:00 |
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tangxifan
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f32ffb6d61
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[Test] Bug fix
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2021-06-29 18:51:28 -06:00 |
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tangxifan
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56b0428eba
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[Misc] Bug fix
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2021-06-29 18:48:19 -06:00 |
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tangxifan
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c6089385b0
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[Misc] Bug fix
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2021-06-29 18:34:41 -06:00 |
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tangxifan
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5f5a03f17f
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[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
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2021-06-29 18:28:38 -06:00 |
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tangxifan
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2c1692e6dc
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[Test] Bug fix
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2021-06-29 17:54:25 -06:00 |
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tangxifan
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4fb34642ca
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[Script] Add a new example script for global tile clock running full testbench
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2021-06-29 17:53:56 -06:00 |
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tangxifan
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9655bc35cb
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[Script] Bug fix due to the full testbench generation changes
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2021-06-29 17:04:19 -06:00 |
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tangxifan
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b5df1f9aeb
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[Tool] Bug fix for redundant endif in netlists
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2021-06-29 17:02:16 -06:00 |
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tangxifan
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b83eef47b4
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[Tool] Bug fix for testbench generation without self checking codes
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2021-06-29 16:27:29 -06:00 |
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tangxifan
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cbea4a3cb6
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[Test] Add the test cases to regression test
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2021-06-29 16:08:22 -06:00 |
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tangxifan
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30c2f597f2
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[Test] Added two cases to validate testbench generation without self checking
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2021-06-29 16:06:15 -06:00 |
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tangxifan
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20faf82e64
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[Script] Rename example script
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2021-06-29 16:02:35 -06:00 |
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tangxifan
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01391fd81e
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[Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features
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2021-06-29 15:56:33 -06:00 |
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tangxifan
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7119075253
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[Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated
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2021-06-29 15:52:42 -06:00 |